JP2009081334A - Multi-layer printed wiring board, and manufacturing method thereof - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a multi-layer printed wiring board and a manufacturing method, thereof which prevents a flux remaining on a pad surface from vaporizing to enter a solder bump. <P>SOLUTION: The multi-layer printed wiring board has a non-through hole 6 bored in the outermost resin insulating base 1<SB>-1</SB>, a field via 3 whose non-through hole 6 is filled with a metal plating or conductive paste 9, a pad 4 formed on the edge portion of the field via 3, and a solder resist layer 5 covering except the soldering portion of the pad 4. A Ni plating layer 7 and an Au plating layer 8 are formed on the upper surface of the pad 4 such that the step between the solder resist layer 5 and the soldering portion of the pad 4 is to be in a range of 0 to 20 μm. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a multilayer printed wiring board having a build-up wiring layer, and more particularly to a multilayer printed wiring board having vias as filled vias and a manufacturing method thereof.

The demand for higher density of multilayer printed wiring boards is increasing due to the small size, light weight, multi-functionality, etc. of today's personal computers, digital cameras, mobile phones, automobile mounted devices and the like.
As a multilayer printed wiring board meeting these requirements, there is Patent Document 1 relating to a multilayer printed wiring board having filled vias filled with metal plating in non-through holes in the outer layer.

  First, Patent Document 1 discloses a circuit pattern of at least two layers in which a conductive paste is filled in a through hole of an insulating base material impregnated with a thermosetting resin and a circuit pattern made of a metal foil is applied on both sides. And a laminated portion of a metal foil and an insulating base material impregnated with a thermosetting resin on both front and back surfaces, and a filled via filled with non-through holes by metal plating on the outermost layer A multilayer printed wiring board technology is disclosed.

According to Patent Document 1, when electronic components and semiconductors are mounted on a mother board by heating and pressing solder bumps, the connection pitch of the mounting components is refined to 0.8 to 0.5 mm, and the diameter of the connection pads can be further reduced. It becomes possible. Filling the outermost non-through holes with metal plating enables the formation of small-diameter filled vias and high-density circuits, and does not bite bubbles when forming solder precoat layers when mounting components. An electronic component can be mounted on. And in the semiconductor which transmits a high-speed signal, since the metal plating is filled in the non-through-hole of the outermost layer, the technique that resistance value can be lowered | hung from a conductive paste is disclosed.
JP 2001-276749 A

However, soldering using the technique of Patent Document 1 is as shown in FIGS.
FIG. 7 is a cross-sectional view of the vicinity of a pad portion of a conventional multilayer printed wiring board, and FIG. 8 is an enlarged cross-sectional view when electronic components are joined using solder bumps in the conventional pad portion.
Circuit patterns 101 are formed on both surfaces of the insulating substrate 100 impregnated with a thermosetting resin, and a conductive paste is filled in via holes (not shown) to electrically connect the circuit patterns 101 formed on both surfaces, Further, in the non-through hole 102 formed in the insulating substrate 100, a pad 104 made of metal foil is provided at the end of the filled via 103 filled with metal plating or conductive paste, and the pad 104 is soldered. Only the necessary portions are exposed and the other portions are exposed from the solder resist layer 105 so as not to be soldered. The pad 104 is coated with a flux layer 106 to prevent oxidation of the copper foil, to chemically remove the oxide film, and to improve the wettability of the solder.

Here, as shown in FIG. 8, when the solder bump 200 is used to solder the terminals of the chip 300 as an electronic component to the pad 104, the surface of the pad 104, the solder resist layer 105, and the solder bump 200 are used to surround the pad 104. A closed space 107 is formed.
In particular, as described in Patent Document 1, when the connection pitch of the mounted components is refined to 0.8 to 0.5 mm and the diameter of the pad 104 is further reduced, the surface of the pad 104, the solder resist layer 105, and the solder bump The residual flux between the surface of the pad 104 and the solder resist layer 105 penetrates into the solder bump 200 into the space 107 formed by the 200, forming voids, reducing the bonding strength of the solder bump 200, or reducing the solder bump 200 and its bonding. There is a possibility of cracks on the surface.

  Accordingly, the present invention has been made to solve such a problem, and it is an object of the present invention to provide a printed wiring board in which residual flux on the surface of the pad does not gasify and enter the solder bump and a method for manufacturing the same. is there.

The multilayer printed wiring board according to claim 1 is a non-through hole formed in the outermost resin insulating base material of the multilayer printed wiring board having a build-up wiring layer, and the non-through hole is made of metal plating or conductive paste. An exposed surface used for soldering the solder resist layer and the pad, comprising: a filled filled via; a pad formed at an end of the filled via; and a solder resist layer that covers a portion other than a soldering portion of the pad. The step is set to 20 μm or less.
Here, the outermost interlayer resin insulation base material has two surfaces in the case of double-sided mounting and one surface in the case of single-sided mounting. The filled via may be any one as long as the non-through hole is filled with metal plating or conductive paste and the pad is formed at the end thereof. The solder resist layer is a resist that covers except for the soldered portion of the pad. Usually, a thermosetting epoxy resin film is used. It is not a thing. Further, the step between the solder resist layer of 20 μm or less and the exposed surface used for soldering the pad is raised by the Ni plating layer, Au plating layer, solder plating layer, etc. Also, the solder resist layer can be formed by partially polishing and cutting the solder resist layer. In addition, the said pad means what has plating layers, such as Ni plating layer and Au plating layer, and the thing which does not have a plating layer.

The step between the solder resist layer of the multilayer printed wiring board according to claim 2 and the exposed surface used for soldering the pad is 20 μm or less by forming a Ni plating layer and an Au plating layer on the upper surface of the pad. It is what.
Here, the formation of the pad and the formation of the solder resist layer are the same as in the prior art, and then the Ni plating layer and the Au plating layer are formed on the exposed surface of the pad, so that the solder resist layer is formed from the upper end. The distance to the exposed surface of the soldered portion of the pad is 20 μm or less. Of course, the Ni plating layer and the Au plating layer are thicker than the Ni plating layer, but the thickness of the Ni plating layer is not limited when the present invention is carried out.

  The step of 20 μm or less between the solder resist layer of the multilayer printed wiring board according to claim 3 and the exposed surface used for soldering the pad is in the range of 0 to 20 μm. In particular, when the surface of the solder resist layer is flat, the exposed surface used for soldering may be a convex surface, and can be in the range of 0 to 20 μm.

According to a fourth aspect of the present invention, there is provided a multilayer printed wiring board manufacturing method comprising: a non-through hole formed in an outermost interlayer resin insulating base material of a multilayer printed wiring board having a build-up wiring layer; A filled via filled with a conductive paste, a pad formed at an end of the filled via, and a solder resist layer covering the soldering portion except the soldered portion of the pad are sequentially formed, and the solder resist layer and the pad are soldered The difference in level from the exposed surface used in is finished to 20 μm or less.
Here, the outermost interlayer resin insulation base material has two surfaces in the case of double-sided mounting and one surface in the case of single-sided mounting. The filled via may be any one as long as the non-through hole is filled with metal plating or conductive paste and the pad is formed at the end thereof. The solder resist layer is a resist that covers except for the soldered portion of the pad. Usually, a thermosetting epoxy resin film is used. It is not a thing. Further, the step between the solder resist layer of 20 μm or less and the exposed surface used for soldering the pad is raised by the Ni plating layer, Au plating layer, solder plating layer, etc. Also, the solder resist layer can be formed by partially polishing and cutting the solder resist layer. In general, the step between the solder resist layer and the exposed surface of the pad is adjusted after the solder resist layer is formed on the upper surface of the pad. In addition, the said pad means what has plating layers, such as Ni plating layer and Au plating layer, and the thing which does not have a plating layer.

The level difference between the solder resist layer and the exposed surface used for soldering the pad in the method for manufacturing a multilayer printed wiring board according to claim 5 is obtained by forming a Ni plating layer and an Au plating layer on the upper surface of the pad. 20 μm or less.
Here, the formation of the pad and the formation of the solder resist layer are the same as in the prior art, and then the Ni plating layer and the Au plating layer are formed on the exposed surface of the pad, so that the solder resist layer is formed from the upper end. The distance to the exposed surface used for pad soldering is within a range of 20 μm. Of course, the Ni plating layer and the Au plating layer are thicker than the Ni plating layer, but the thickness of the Ni plating layer is not limited when the present invention is carried out.

  The step of 20 μm or less between the solder resist layer and the exposed surface used for soldering the pad in the method for manufacturing a multilayer printed wiring board according to claim 6 is in the range of 0 to 20 μm. In particular, when the surface of the solder resist layer is flat, the exposed surface used for soldering may be a convex surface, and can be in the range of 0 to 20 μm.

  The multilayer printed wiring board according to claim 1 is a non-through hole formed in the outermost interlayer resin insulating base material of the multilayer printed wiring board having a build-up wiring layer, and the non-through hole is metal-plated or conductive paste. A filled via filled with, a pad formed at an end of the filled via, and a solder resist layer covering except for a soldered portion of the pad, and exposed for use in soldering the solder resist layer and the pad Since the step with respect to the surface is 20 μm or less, when soldering a terminal of an electronic component or the like to the pad using a solder bump, the surface of the pad, the solder resist layer, and the solder bump are used to surround the pad. There is almost no space to be closed, and the space between the surface of the pad and the solder resist layer is in the space. The absolute amount of the residual flux that is gasified is reduced, and it is excluded to the outside by melting the solder bump, so that the residual flux gas and its residue do not enter the solder bump, and the bonding due to the solder bump is reduced. In addition, the occurrence of cracks or voids at the joints is reduced.

  The step between the solder resist layer of the multilayer printed wiring board according to claim 2 and the exposed surface used for soldering the pad is 20 μm or less by forming a Ni plating layer and an Au plating layer on the upper surface of the pad. Therefore, only by forming a plating layer on the upper surface of the pad, the absolute amount of residual flux gasifying between the pad surface and the solder resist layer is reduced, and this is the melting of the solder bump. Therefore, the residual flux gas does not enter the solder bumps, and the bonding due to the solder bumps does not deteriorate and cracks do not occur in the joints.

  The step of 20 μm or less between the solder resist layer of the multilayer printed wiring board according to claim 3 and the exposed surface used for soldering the pad can be within a range of 0 to 20 μm. In addition to the effect of 2, since the exposed surface used for soldering may be a convex surface when the surface of the solder resist layer is flat, it can be in the range of 0 to 20 μm, and the accuracy of the finished surface can be improved. You don't have to be particularly important.

  The method for producing a multilayer printed wiring board according to claim 4 includes: a non-through hole formed in the outermost interlayer resin insulating base material of the multilayer printed wiring board having a build-up wiring layer; A filled via filled with a conductive paste, a pad formed at an end of the filled via, and a solder resist layer covering except for a soldering portion of the pad, and soldering the solder resist layer and the pad Since the step with the exposed surface to be used is 20 μm or less, when soldering a terminal such as an electronic component to the pad using the solder bump, the surface of the pad, the solder resist layer, and the solder bump, There is almost no closed space around the pad, and the pad surface and the solder are in the space. The absolute amount that the residual flux between the dies layer is gasified decreases, and it is excluded to the outside by melting of the solder bump, and the residual flux gas and its residue do not enter the solder bump, There is no decrease in bonding due to the solder bumps, cracks in the bonded portions, or voids.

  The step of the solder resist layer and the exposed surface of the soldered portion of the pad in the method for manufacturing a multilayer printed wiring board according to claim 5 is formed by forming a Ni plating layer and an Au plating layer on the upper surface of the pad, thereby forming a thickness of 20 μm. Since only the formation of the plating layer on the upper surface of the pad, the absolute amount that the residual flux between the surface of the pad and the solder resist layer is gasified decreases, and The solder bumps are excluded to the outside by the melting of the solder bumps, and the residual flux gas does not enter the solder bumps, so that the bonding due to the solder bumps does not deteriorate and the joints do not crack.

  The step of 20 μm or less between the solder resist layer and the exposed surface used for soldering the pad in the method for producing a multilayer printed wiring board according to claim 6 can be within a range of 0 to 20 μm. Alternatively, in addition to the effect of claim 4, in the state where the surface of the solder resist layer is flat, the exposed surface used for soldering may be a convex surface. There is no need to place special emphasis on the accuracy.

Hereinafter, embodiments of the present invention will be described with reference to the drawings. Note that, in the embodiments, the same symbols and the same reference numerals in the drawings are the same or corresponding functional parts, and therefore, redundant description is omitted here.
[Embodiment 1]

  FIG. 1 is a cross-sectional view showing the process of manufacturing a multilayer printed wiring board according to Embodiment 1 of the present invention, and FIG. 2 is a cross-sectional view showing the multilayer printed wiring board according to Embodiment 1 of the present invention. 3 is an enlarged cross-sectional view of the main part of the multilayer printed wiring board according to the first embodiment of the present invention, and FIG. 4 is an enlarged cross-sectional view of the main part before the multilayer printed wiring board of the first embodiment of the present invention is joined by solder bumps. FIG. 5 is an enlarged cross-sectional view of a main part in which the multilayer printed wiring board according to Embodiment 1 of the present invention is joined by solder bumps. FIG. 6 is a cross-sectional view of the multilayer printed wiring board according to Embodiment 1 of the present invention joined by solder bumps.

In the figure, impregnated with plural laminated thermosetting resin interlayer resin insulating substrate 1 (provided that when denote a particular insulating substrate, referred to as 1 _-1, 1 _-2, 1 _-3) and its A circuit pattern 2 is formed on one side or both sides (however, when a specific circuit pattern is meant, it is expressed as 2 ₋₁ , 2 ₋₂ ). A conductive paste 9 is filled in a via hole such as an inner via, and a build-up wiring layer that electrically connects the circuit patterns 2 is provided as necessary. The configuration of the build-up wiring layer of this embodiment is not different from a known build-up wiring layer.

Wherein the outermost build-up wiring layer interlayer resin insulating substrate 1 _-1 becomes the two surfaces in the case of double-sided mounting, the one side in the case of one-side mounting. In addition, the non-through hole 6 which is drilled in the interlayer resin insulating substrate 1 _-1, conductive paste 9 form a filled via 3 are filled. A pad 4 made of a metal foil such as a copper foil is formed at the end. The filled via 3 may be metal plated instead of the conductive paste 9.
That is, if the circuit pattern 2 _-1 side, through the filled vias 3 filled with conductive paste 9 in a non-through hole 6 which is drilled in the interlayer resin insulating substrate 1 _-1, formed in its upper end a metal foil The pad 4 is made energized.

The pad 4 is coated with a solder resist layer 5 so that only the soldered portion is exposed and the other portions are not soldered, and only the soldered portion of the pad 4 is exposed.
As shown in FIG. 3, the pad 4 having an exposed surface used for soldering has a Ni plating layer 7 and an Au plating layer 8 sequentially formed on the surface of the pad 4. The Ni plating layer 7 on the upper surface of the pad 4 is usually formed to have a thickness of about 5 to 20 μm, preferably about 5 to 10 μm. An Au plating layer 8 is formed on the upper surface of about 0.01 to 0.1 μm, preferably about 0.03 to 0.07 μm.
Note that the fact that only the area portion used for soldering the pad 4 is exposed means only the area portion used for soldering the pad 4 when the pad 4 is made of copper foil or the like. When a plating layer such as the Ni plating layer 7 and the Au plating layer 8 is formed on the surface of the surface, the plating layer such as the Au plating layer 8 is soldered, so the area used for soldering the pad 4 The portion means the surface of a plating layer such as the Au plating layer 8.

Usually, the distance from the upper end of the solder resist layer 5 shown in FIG. 1 to the exposed surface used for soldering a pad made of copper foil or the like is about 25 to 35 μm. By sequentially forming the Au plating layer 8, as shown in FIG. 3, the distance from the upper end of the solder resist layer 5 to the uppermost Au plating layer 8 of the soldered portion of the pad 4 is within a range of 0 to 20 μm. It is a thing.
As shown in FIG. 6, the electronic component 20 mounted on the multilayer printed wiring board and the solder resist layer 5 are integrated by an underfill 11 to ensure mounting and bonding stability between the two. Yes.

After sequentially forming the Ni plating layer 7 and the Au plating layer 8 on the surface of the pad 4, the upper surface of the Au plating layer 8 is subjected to a flux treatment in order to improve the wettability of the solder.
Here, when the terminals of the electronic component 20 or the like are soldered to the pads 4 using the solder bumps 10, the surface of the Au plating layer 8 of the pads 4, the solder resist layer 5, and the solder bumps 10 as shown in FIG. There is almost no closed space around the surface of the Au plating layer 8 of the pad 4, and the absolute amount of residual flux between the surface of the Au plating layer 8 of the pad 4 and the solder resist layer 5 is reduced, And it is excluded outside by the melting of the solder bump 10, the residual flux gas and the residue do not enter the solder bump 10, and the bonding by the solder bump 10 may be lowered or the joint may be cracked. Absent. Further, voids are not generated in the solder bumps 10, and the bonding force is not reduced.

  According to the experiments by the inventors, as shown in FIG. 3, if the distance from the upper end of the solder resist layer 5 to the Au plating layer 8 on the uppermost surface of the pad 4 is in the range of 0 to 20 μm, The absolute amount that the residual flux between the surface of the Au plating layer 8 of the pad 4 and the solder resist layer 5 is gasified is reduced, and the residual flux gas is excluded to the outside by melting of the solder bumps 10 and spreading of bonding. Therefore, as a result, it was confirmed that the residual flux gas did not enter the solder bump 10, and it was confirmed that the bonding by the solder bump 10 was not lowered and cracks did not enter the bonded portion.

As shown in FIGS. 4 and 5, since the distance from the upper end of the solder resist layer 5 to the Au plating layer 8 on the uppermost surface of the pad 4 is in the range of 0 to 20 μm, the solder bump 10 and the Au plating layer of the pad 4 Since the bonding with the surface of the solder bump 10 can be visually confirmed, it is easy to confirm conditions such as the temperature and the pressing force of the solder bump 10.
In particular, as shown in FIG. 6, the bonding state of the solder bump 10 can be confirmed before the electronic component 20 mounted on the multilayer printed wiring board and the solder resist layer 5 are integrated by the underfill 11.

As described above, in the first embodiment, the circuit pattern 2 formed on the upper surface and the circuit pattern 2 formed on the lower surface are electrically insulated by the interlayer resin insulating base material 1 and the circuit patterns 2 are required to be mutually connected. In the multilayer printed wiring board having a build-up wiring layer that is electrically connected to each other through a plurality of through-vias, blind vias, inner vias and the like formed in the interlayer resin insulation base material 1 a non-through hole 6 which is drilled in the resin insulating substrate 1 _-1, and filled vias 3 blind holes 6 are filled by metal plating or conductive paste 9, a pad 4 formed on the end of the filled via 3, the pad The solder resist layer 5 is formed so as to cover the solder resist layer 5 and the exposed surface used for soldering the pad 4. Those in the range of 0~20μm by the upper surface of the de 4 forming the Ni plating layer 7 and the Au plating layer 8.

Thus filled, the non-through hole 6 which is drilled in the multilayer printed wiring outermost interlayer resin insulating substrate 1 _-1 of a substrate having a built-up wiring layer, a non-through hole 6 by metal plating or conductive paste 9 The filled via 3, the pad 4 formed at the end of the filled via 3, and the solder resist layer 5 covering except the soldered portion of the pad 4 are provided, and the solder resist layer 5 and the pad 4 are soldered. Since the level difference from the exposed surface of the part is in the range of 0 to 20 μm, when soldering a terminal of the electronic component 20 or the like to the pad 4 using the solder bump 10, the surface of the pad 4 and the solder resist layer 5 and the solder bump 10, there is almost no space closed around the pad 4, and the space between the surface of the pad 4 and the solder resist layer 5 exists in the space. The absolute amount that the residual flux is gasified decreases, and it is excluded to the outside by melting of the solder bump 10, so that the residual flux gas does not enter the solder bump 10. There is no crack in the part.

  In the embodiment, the step between the solder resist layer 5 and the exposed surface used for soldering the pad 4 is within the range of 0 to 20 μm by forming the Ni plating layer 7 and the Au plating layer 8 on the upper surface of the pad 4. However, the difference can also be reduced by polishing and cutting the solder resist layer 5 on the upper surface of the pad 4.

By the way, the multilayer printed wiring board of the said embodiment can also be caught as invention of a manufacturing method.
In other words, the circuit pattern 2 formed on the upper surface and the circuit pattern 2 formed on the lower surface are electrically insulated by the interlayer resin insulating base material 1 and the circuit pattern 2 is intercalated between the interlayer resin insulating base material 1 as necessary. The outermost interlayer resin insulation base material in the manufacturing method of a multilayer printed wiring board having a build-up wiring layer electrically connected to each other through via holes such as a number of through vias, blind vias, inner vias, etc. 1 and the non-through hole 6 which is drilled to _-1, and filled vias 3 filled blind holes 6 by metal plating or conductive paste 9, a pad 4 formed on the end of the filled via 3, soldering of the pad 4 A solder resist layer 5 is formed in order to cover except the portion, and the step between the solder resist layer 5 and the exposed surface of the soldered portion of the pad 4 is set to 0 to 20 μm. It may be the invention of a method of finishing in the range of.

Thus, a non-through hole 6 which is drilled in the multilayer printed wiring outermost interlayer resin insulating substrate 1 _-1 of a substrate having a built-up wiring layer, a non-through holes 6 are filled by metal plating or conductive paste 9 An exposed surface used for soldering the solder resist layer 5 and the pad 4, including the filled via 3, the pad 4 formed at the end of the filled via 3, and the solder resist layer 5 covering except for the soldered portion of the pad 4. The solder bump 10 is used to solder the terminal of the electronic component 20 or the like to the pad 4 by using the solder bump 10 and the solder resist layer 5 and the solder bump 10. , There is almost no space closed around the pad 4, and residual flux between the surface of the pad 4 and the solder resist layer 5 is left in the space. The absolute amount of gasification is reduced, and it is excluded to the outside by melting of the solder bumps 10, so that the residual flux gas does not enter the solder bumps 10, and the bonding by the solder bumps 10 is reduced and cracks are generated in the joints. There is no entry.

  The step between the solder resist layer 5 and the exposed surface used for soldering the pad 4 is finished within a range of 0 to 20 μm by forming the Ni plating layer 7 and the Au plating layer 8 on the upper surface of the pad 4. Therefore, it is not necessary to significantly change the conventional manufacturing method only by changing the plating process of the Ni plating layer 7 and the Au plating layer 8.

  In particular, the surface of the solder resist layer 4 is flat in the range of 0 to 20 μm of the step between the solder resist layer 5 described in the above embodiment and the exposed surface used for soldering the pad 4. In the state, since the exposed surface used for soldering may be a convex surface, it can be manufactured at 20 μm or less, and may have a slightly negative value. That is, the accuracy of the finished surface does not have to be regarded as particularly important.

FIG. 1 is a cross-sectional view showing the process of manufacturing a multilayer printed wiring board according to Embodiment 1 of the present invention. FIG. 2 is a cross-sectional view showing the multilayer printed wiring board according to Embodiment 1 of the present invention. FIG. 3 is an enlarged cross-sectional view of a main part of the multilayer printed wiring board according to Embodiment 1 of the present invention. FIG. 4 is an enlarged cross-sectional view of a main part before the multilayer printed wiring board according to Embodiment 1 of the present invention is joined by solder bumps. FIG. 5 is an enlarged cross-sectional view of a main part in which the multilayer printed wiring board according to Embodiment 1 of the present invention is joined by solder bumps. FIG. 6 is a cross-sectional view of the multilayer printed wiring board according to Embodiment 1 of the present invention joined by solder bumps. FIG. 7 is an enlarged cross-sectional view of the vicinity of a pad portion of a conventional multilayer printed wiring board. FIG. 8 is an enlarged cross-sectional view in the case where electronic components are joined using solder bumps at the pad portion of a conventional multilayer printed wiring board.

Explanation of symbols

1,1 _-1, 1 _-2, 1 _-3 insulating substrates 2 _-1, 2 _-2 circuit pattern 3 filled vias 4 pads 5 solder resist layer 6 blind holes 7 Ni plating layer 8 Au plating layer 9 conductive paste 10 Solder bump 20 Electronic component

Claims (6)

The circuit pattern formed on the upper surface and the circuit pattern formed on the lower surface are electrically insulated by the interlayer resin insulation base material, and a plurality of circuit patterns are formed on the interlayer resin insulation base material as necessary. In a multilayer printed wiring board having a build-up wiring layer that is electrically connected to each other through a via hole of
A non-through hole formed in the outermost interlayer resin insulation base material, a filled via filled with the non-through hole with metal plating or conductive paste, a pad formed at an end of the filled via, and the pad And a solder resist layer covering except for the area used for soldering,
A multilayer printed wiring board, wherein a step difference between the solder resist layer and an exposed surface used for soldering the pad is 20 μm or less.   The step difference between the solder resist layer and the exposed surface used for soldering the pad is set to 20 μm or less by forming a Ni plating layer and an Au plating layer on the upper surface of the pad. A multilayer printed wiring board according to 1.   3. The multilayer according to claim 1, wherein the step difference of 20 μm or less between the solder resist layer and the exposed surface used for soldering the pad is within a range of 0 to 20 μm. Printed wiring board. The circuit pattern formed on the upper surface and the circuit pattern formed on the lower surface are electrically insulated by the interlayer resin insulation base material, and a plurality of circuit patterns are formed on the interlayer resin insulation base material as necessary. In a method for manufacturing a multilayer printed wiring board having a build-up wiring layer that is electrically connected to each other via via holes,
A non-through hole formed in the outermost interlayer resin insulation base material, a filled via filled with the non-through hole with metal plating or conductive paste, a pad formed at an end of the filled via, and the pad And a solder resist layer covering the soldered portion of the multilayer printed wiring board, wherein a step difference between the solder resist layer and the exposed surface of the soldered portion of the pad is finished to 20 μm or less. Production method.   The step difference between the solder resist layer and the exposed surface used for soldering the pad is finished to 20 μm or less by forming a Ni plating layer and an Au plating layer on the upper surface of the pad. 5. A method for producing a multilayer printed wiring board according to 4.   6. The multilayer according to claim 4, wherein a range of 20 μm or less of a step between the solder resist layer and an exposed surface used for soldering the pad is within a range of 0 to 20 μm. A method for manufacturing a printed wiring board.

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