JP2002367941A - Method for manufacturing semiconductor integrated circuit device - Google Patents

Abstract

(57) [Summary] (with correction) [PROBLEMS] To provide a technique in a CMP technique that can automatically detect the life of a retainer ring. A life detecting hole is provided in a retainer ring, and one end of the life detecting hole on the polishing pad side is closed.
The other end is released and a constant pressure is applied, and the life of the retainer ring 5 is automatically detected by reading a change in the pressure 7 applied to the life detection hole 6 when the closed side is released.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a technique for manufacturing a semiconductor integrated circuit device, and more particularly, to chemical mechanical polishing for flattening irregularities on a surface of an insulating film or a metal film deposited on a substrate. The present invention relates to a technique which is effective when applied to a method of manufacturing a semiconductor integrated circuit device using the (CMP) method.

[0002]

2. Description of the Related Art Pressing C while holding a semiconductor wafer
Various structures have been proposed for the processing head of the MP apparatus. Most commonly, a wafer chuck for holding a semiconductor wafer, a retainer ring for preventing the semiconductor wafer from coming off during polishing, a backing film for maintaining a surface reference, and a housing for applying pressure while holding these. The processing head is mainly composed of the elements.

The structure of the processing head of the CMP apparatus is described in, for example, "Semiconductor Flattening CMP Technology" published by the Industrial Research Institute of Japan on July 15, 1998, by Toshiro Dohi,
It is described in Toshio Kasai and Takeo Nakagawa, pp. 69-74.

[0004] In CMP, generally, a run-out occurs on a semiconductor wafer. As one of means for minimizing this weeping phenomenon and ensuring the uniformity of the processing surface, a processing head having a retainer ring arranged on the outer periphery of a semiconductor wafer is used. The retainer ring is provided to prevent the semiconductor wafer from coming off during polishing. However, if the retainer ring arranged on the outer periphery of the semiconductor wafer is treated as a processing dummy, the run-out can be reduced.

[0005]

When a retainer ring is used as the processing dummy, the retainer ring can be removed simultaneously with the polishing of the semiconductor wafer. Therefore, it is necessary to replace the retainer ring when a certain amount of shaving is reached. However, when the present inventor studied, the life of the retainer ring, that is, the amount of scraping is managed by the cumulative use time, but the cumulative use time of the retainer ring and the amount of scraping of the retainer ring are not simply proportional, For this reason, it became clear that the retainer ring was excessively scraped despite the life time.

Since the life of the retainer ring cannot be accurately grasped, the pressure for suppressing the semiconductor wafer and the pressure for suppressing the retainer ring due to excessive cutting of the retainer ring cannot be balanced, and the uniformity of the polishing amount in the semiconductor wafer surface deteriorates. Or the semiconductor wafer pops out.

An object of the present invention is to provide a technique capable of automatically detecting the life of a retainer ring in the CMP technique.

The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[0009]

SUMMARY OF THE INVENTION Among the inventions disclosed in the present application, the outline of a representative one will be briefly described.
It is as follows.

According to the present invention, a semiconductor wafer is held by using a processing head having a retainer ring having a life detecting hole.
In the CMP step of pressing and polishing the surface of various films formed on the semiconductor wafer, one end of the life detection hole on the polishing pad side is closed, and the other end is opened and a constant pressure is applied, The life of the retainer ring is detected by detecting a pressure that fluctuates due to opening of one end of the life detection hole on the polishing pad side.

[0011]

Embodiments of the present invention will be described below in detail with reference to the drawings. In all the drawings for describing the embodiments, members having the same functions are denoted by the same reference numerals, and the repeated description thereof will be omitted.

FIGS. 1 and 2 are schematic views showing a cross section of a processing head of a CMP apparatus according to an embodiment of the present invention. FIG. 1 shows a processing head when the amount of shaving of the retainer ring is relatively small, and FIG. 2 shows a processing head when the amount of shaving of the retainer ring is relatively large. In the figure, 1
Is a semiconductor wafer, 2 is a processing head, 3 is a polishing platen, 4 is a polishing pad, 5 is a retainer ring, 6 is a life detecting hole, 7
Is a pressure, 8 is a supply line, and 9 is air.

A semiconductor wafer 1, which is a material to be polished, is held by a processing head 2 of an air bag system, and the surface of the semiconductor wafer 1 is polished by a polishing pad 4 stuck on a rotating polishing platen 3. Although not shown, the surface of the polishing pad 4 is cut using a dresser in order to reproduce its function. During polishing, the polishing pad 4
The slurry is supplied from a supply nozzle installed above the.

The processing head 2 can pressurize the semiconductor wafer 1 and has a rotation function. The semiconductor wafer 1 is held by a spring of an elastic plate, and the wafer chuck is in a so-called floating state with respect to the processing head 2.

The processing head 2 includes a semiconductor wafer 1
A retainer ring 5 for preventing the semiconductor wafer 1 from coming off during polishing and for reducing the run-off of the semiconductor wafer 1 is provided on the outer periphery of the region where the semiconductor wafer 1 is provided.

The retainer ring 5 is provided with a life detecting hole 6 (shown by hatching in the figure), and a constant pressure 7 is always applied from a supply line 8. The life detecting hole 6 is provided in the retainer ring 5 substantially vertically, for example, toward the polishing pad 4. In the case of an unused retainer ring 5, one end of the life detecting hole 6 on the polishing pad 4 side is closed, The other end is open and connected to the supply line 8.

When the semiconductor wafer 1 is polished, the retainer ring 5 is also shaved at the same time. However, if the amount of shaving of the retainer ring 5 is small and the retainer ring 5 is not shaved until it reaches the life detecting hole 6 (FIG. 1), the above-described constant Pressure 7 is applied. However, when the retainer ring 5 is shaved until it reaches the life detecting hole 6 (FIG. 2), one end of the life detecting hole 6 is opened, so that the pressure 7 fluctuates. The life of the retainer ring 5 can be detected by detecting the fluctuation of the pressure 7.

As described above, according to the present embodiment, the life detecting hole 6 is provided in the retainer ring 5 provided in the processing head 2, and the change in the pressure 7 applied to the life detecting hole 6 is read, so that the retainer ring 5 The life can be automatically detected. As a result, the retainer ring 5 can be replaced when the polishing amount reaches a certain level, and the uniformity of the polishing amount in the surface of the semiconductor wafer 1 is degraded due to excessive shaving of the retainer ring 5, or the semiconductor wafer 1 jumps out. Can be prevented.

Next, a CMOS to which the present embodiment is applied
An example of a method of manufacturing a (complementary metal oxide semiconductor) device will be described in the order of steps with reference to FIGS.

First, as shown in FIG. 3, a semiconductor substrate 11 made of, for example, a p ^- type single crystal is prepared, and an element isolation region 12 is formed on the main surface of the semiconductor substrate 11. Next, impurities are ion-implanted using the patterned photoresist film as a mask to form a p-well 13 and an n-well 14. The p-well 13 has impurities of p-type conductivity,
For example, boron (B) is ion-implanted, and an impurity showing n-type conductivity, for example, phosphorus (P) is ion-implanted into n-well 14. Thereafter, impurities for controlling the threshold voltage of the MISFET may be ion-implanted into each well region.

Next, a silicon oxide film serving as the gate insulating film 15, a polycrystalline silicon film serving as the gate electrode 16, and a silicon oxide film serving as the cap insulating film 17 are sequentially deposited to form a laminated film. The laminated film is etched using the resist film as a mask. The gate insulating film 15 is formed, for example, by a thermal oxidation method or a thermal CVD (chemic) method.
al vapor deposition) method,
Gate electrode 16 can be formed by, for example, a CVD method.

Next, for example, a CV
After a silicon oxide film is deposited by the method D, the silicon oxide film is anisotropically etched to form the gate electrode 16.
A sidewall spacer 18 is formed on the side wall of. Thereafter, using the patterned photoresist film as a mask, an n-type impurity (for example, phosphorus or arsenic (As)) is ion-implanted into the p-well 13 to form p-type impurities on both sides of the gate electrode 16.
An n-type semiconductor region 19 is formed in the well 13. The n-type semiconductor region 19 is formed in a self-aligned manner with respect to the gate electrode 16 and the side wall spacer 18, and has an n-channel MISFET (metal insulator semiconductor field).
function transistor). Similarly, using the patterned photoresist film as a mask, a p-type impurity (for example, boron fluoride (BF ₂ )) is ion-implanted into the n-well 14 to form a gate electrode 16.
P-type semiconductor regions 20 are formed in the n-wells 14 on both sides of the semiconductor device. The p-type semiconductor region 20 is formed in a self-aligned manner with respect to the gate electrode 16 and the sidewall spacer 18, and functions as a source and a drain of the p-channel MISFET.

Next, as shown in FIG.
After a silicon oxide film 21 is formed thereon, the silicon oxide film 21 is
The surface is flattened by polishing using an apparatus. The silicon oxide film 21 is made of, for example, TEOS (tetra ethyl
ortho silicate: Si (OC ₂ H ₅ )) and ozone (O ₃ )
And a TEOS oxide film deposited by a plasma CVD method using these as a source gas.

Next, the silicon oxide film 2 is etched by using the patterned photoresist film as a mask.
1 are formed with connection holes 22. The connection hole 22 is formed in a necessary portion such as on the n-type semiconductor region 19 or the p-type semiconductor region 20.

Next, a titanium nitride film is formed on the entire surface of the semiconductor substrate 11 including the inside of the connection hole 22 by, for example, the CVD method, and a tungsten (W) film for filling the connection hole 22 is formed by, for example, the CVD method. . Then, the connection hole 22
The plug 23 is formed inside the connection hole 22 by removing the titanium nitride film and the tungsten film in the region other than the region using, for example, a CMP apparatus having the processing head 2.

Subsequently, as shown in FIG.
After a tungsten film, for example, is formed on the entire surface of the substrate 1, the tungsten film is processed by etching using the patterned photoresist film as a mask to form the wiring 24 of the first wiring layer. The tungsten film can be formed by a CVD method or a sputtering method.

Next, as shown in FIG. 6, after forming an insulating film covering the wiring 24, for example, a silicon oxide film, the insulating film is polished using, for example, a CMP apparatus having the processing head 2. Thereby, an interlayer insulating film 25 having a flattened surface is formed. Next, a connection hole 26 is formed in the interlayer insulating film 25 by etching using the patterned photoresist film as a mask.

Next, a barrier metal layer is formed on the entire surface of the semiconductor substrate 11 including the inside of the connection hole 26,
A copper (Cu) film for embedding 6 is formed. The barrier metal layer is made of, for example, titanium nitride (TiN), tantalum (T
a), tantalum nitride (TaN) or the like;
Formed by method D. The copper film functions as a main conductor layer and can be formed by, for example, a plating method. Before forming a copper film by plating, a thin copper film can be formed as a seed layer by, for example, a CVD method or a sputtering method. Thereafter, the plug 27 is formed by removing the copper film and the barrier metal layer in a region other than the connection hole 26 using, for example, a CMP apparatus having the processing head 2.

Next, as shown in FIG.
Then, a stopper insulating film 28 is formed on the plug 27 and an insulating film 29 for forming a wiring is formed. The stopper insulating film 28 is a film serving as an etching stopper when a groove is formed in the insulating film 29, and is made of a material having an etching selectivity with respect to the insulating film 29. The stopper insulating film 28 is, for example, a silicon nitride film, and the insulating film 29 is, for example, a silicon oxide film. Note that a second wiring layer described below is formed on the stopper insulating film 28 and the insulating film 29. Therefore, the total film thickness is determined by the design film thickness required for the second wiring layer. Next, a wiring groove 30 is formed in a predetermined region of the stopper insulating film 28 and the insulating film 29 by etching using the patterned photoresist film as a mask.

Next, a barrier metal layer 31 is formed on the entire surface of the semiconductor substrate 11 including the inside of the wiring groove 30. The barrier metal layer 31 is made of, for example, a tantalum film, and its thickness can be, for example, about 50 nm on a substrate plane. The tantalum film is formed by, for example, a sputtering method. The barrier metal layer 31 may be made of titanium nitride, tantalum nitride, or the like.

Next, although not shown, a copper seed layer is formed on the barrier metal layer 31. The seed layer is formed by, for example, a CVD method or a sputtering method.
For example, it is about 100 nm on the substrate plane. Further, a copper plating layer is formed on the seed layer by using an electrolytic plating method. The thickness of the plating layer is, for example, 600 n on the substrate plane.
m. Thereby, the wiring groove 30 is buried.

Next, the plating layer and the seed layer are polished using a CMP apparatus having the processing head 2. Since the polishing rate of copper is high, the copper portion is removed first.
Further, the polishing is continued, and the barrier metal layer 31 on the insulating film 29 is removed. As a result, the copper film (plating layer and seed layer) and the barrier metal layer 3 in a region other than the wiring groove 30 are formed.
1 is removed to form the wiring 32 of the second wiring layer.

Then, after further forming the upper wiring,
By covering the entire surface of the semiconductor substrate 11 with the passivation film, the CMOS device is substantially completed.

In the present embodiment, the CMP technique is
The case where the present invention is applied to a method for manufacturing a MOS device has been described. However, the present invention is not limited to this, and is applicable to any method for manufacturing a semiconductor device.

In this embodiment, the case where the CMP technique is applied to the wiring step has been described. However, the present invention can be applied to any step requiring flattening. The present invention can be applied to formation of a region.

Although the invention made by the inventor has been specifically described based on the embodiments of the present invention, the present invention is not limited to the above embodiments, and various modifications may be made without departing from the gist of the invention. Needless to say, it can be changed.

For example, in the above embodiment, the life detecting hole is provided in the retainer ring, and the life of the retainer ring is automatically detected by reading the change in the pressure applied to the life detecting hole. Therefore, every time the retainer ring is replaced, the work of connecting the supply pipe and the life detecting hole can be omitted.

[0038]

The effects obtained by typical ones of the inventions disclosed in the present application will be briefly described as follows.

By providing a life detecting hole in the retainer ring and reading the change in pressure applied to the life detecting hole, the CMP is performed.
The life of the retainer ring in the technology can be automatically detected.

[Brief description of the drawings]

FIG. 1 is a schematic diagram illustrating a cross section of a processing head of a CMP apparatus according to an embodiment of the present invention.

FIG. 2 is a schematic view showing a cross section of a processing head of the CMP apparatus according to one embodiment of the present invention.

FIG. 3 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the CMOS device according to the embodiment of the present invention;

FIG. 4 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the CMOS device according to one embodiment of the present invention;

FIG. 5 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the CMOS device according to the embodiment of the present invention;

FIG. 6 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the CMOS device according to the embodiment of the present invention;

FIG. 7 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the CMOS device according to the embodiment of the present invention;

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Semiconductor wafer 2 Processing head 3 Polishing surface plate 4 Polishing pad 5 Retaining ring 6 Life detecting hole 7 Pressure 8 Supply pipeline 9 Air 11 Semiconductor substrate 12 Element isolation region 13 P well 14 N well 15 Gate insulating film 16 Gate electrode 17 Cap Insulating film 18 Sidewall spacer 19 N-type semiconductor region 20 P-type semiconductor region 21 Silicon oxide film 22 Connection hole 23 Plug 24 Wiring 25 Interlayer insulating film 26 Connection hole 27 Plug 28 Stopper insulating film 29 Insulating film 30 Wiring groove 31 Barrier metal layer 32 Wiring

Claims (3)

[Claims] 1. A CM for holding a semiconductor wafer using a processing head having a retainer ring provided with a life detecting hole and polishing the surfaces of various films formed on the semiconductor wafer.
A method of manufacturing a semiconductor integrated circuit device having a P step, wherein one end of the life detecting hole on the polishing pad side is closed, and the other end is opened and a constant pressure is applied. A method for manufacturing an integrated circuit device. 2. A CM for holding a semiconductor wafer using a processing head having a retainer ring provided with a life detecting hole and polishing the surface of various films formed on the semiconductor wafer.
A method of manufacturing a semiconductor integrated circuit device having a P step, wherein one end of the life detecting hole on the polishing pad side is closed, and the other end is opened and a constant pressure is applied, A method for manufacturing a semiconductor integrated circuit device, comprising detecting a life of the retainer ring by detecting a pressure that fluctuates due to opening of one end on a polishing pad side. 3. A CM for holding a semiconductor wafer using a processing head having a retainer ring provided with a life detecting hole and polishing the surface of various films formed on the semiconductor wafer.
A method of manufacturing a semiconductor integrated circuit device having a P step, wherein one end of the life detection hole on the polishing pad side is closed, and the other end is opened and a constant pressure is applied, and the life detection hole is A method for manufacturing a semiconductor integrated circuit device, wherein the semiconductor integrated circuit device is provided in the retainer ring substantially vertically toward a polishing pad.