US20020048884A1

US20020048884A1 - Vertical source/drain contact semiconductor

Info

Publication number: US20020048884A1
Application number: US09/510,102
Authority: US
Inventors: Shyue Quek; Ting Ang; Sang Loong; Puay Ong
Original assignee: Chartered Semiconductor Manufacturing Pte Ltd
Current assignee: GlobalFoundries Singapore Pte Ltd
Priority date: 2000-02-22
Filing date: 2000-02-22
Publication date: 2002-04-25
Also published as: US6653674B2; US20030006462A1

Abstract

A semiconductor device and manufacturing process therefor is provided in which angled dopant implantation is followed by the formation of vertical trenches in the silicon on insulator substrate adjacent to the sides of the semiconductor gate. A second dopant implantation in the exposed the source/drain junctions is followed by a rapid thermal anneal which forms the semiconductor channel in the substrate. Contacts are then formed which connect vertically to the exposed source/drain junctions either directly or through salicided contact areas.

Description

TECHNICAL FIELD

The present invention relates generally to semiconductor devices, and more particularly to silicon on insulator transistors.

BACKGROUND ART

Semiconductor devices such as transistors, resistors, capacitors, and other circuit elements, are formed in and upon semiconductor substrates. These circuit elements are interconnected by contacts and vias, which connect to patterned conductor layers which are separated by various dielectric layers.

A critical objective of the semiconductor industry has been to continually decrease the size of semiconductor devices to increase performance and reduce cost.

The ability to reduce performance degrading parasitic capacitances resulting from diffusion of junction dopants into semiconductor substrates has been accomplished through the use of silicon on insulator (SOI) technology. The SOI technology consists of forming the desired semiconductor devices in a layer of silicon which overlies an insulator layer deposited on a conventional semiconductor substrate.

As semiconductor technology has advanced, there has been a continuing concentration on reducing the size of the semiconductor devices to allow for increased levels of circuit integration, improved performance, and higher density.

However, when the length and width of a semiconductor device are reduced, the length and width of the contacts connected to the semiconductor device must also be reduced. When the length and width of the contacts are reduced, the cross-sectional area is reduced by the square of the length or width and the resistance generally increases by the square (power of 2). The industry is currently reaching the point where the size is so small that the relative resistance is so high as to render connection to small devices impossible.

As devices continue to be reduced in size, it is clear that a breakthrough solution to this problem is required for continued success in reducing semiconductor device size and thus increasing device integration, performance, and function while at the same time reducing cost.

DISCLOSURE OF THE INVENTION

The present invention provides a semiconductor device and manufacturing process therefor in which vertical trenches are formed in the semiconductor or the silicon on insulator substrate adjacent to the sides of the semiconductor gate to expose the source/drain junctions. The contacts connect vertically to the exposed source/drain junctions either directly or through salicided contact areas to provide a smaller semiconductor device (transistor) footprint.

The present invention further provides a semiconductor device and manufacturing process therefor in which vertical trenches are formed in the semiconductor or the silicon on insulator substrate adjacent to the sides of the semiconductor gate to expose the source/drain junctions. The contacts connect vertically to the exposed source/drain junctions either directly or through salicided contact areas to provide a contact to silicon connection.

The present invention further provides a semiconductor device and manufacturing process therefor in which angled implantation of dopant followed by formation of vertical trenches which are also implanted with dopant. A rapid thermal anneal forms source/drain extension junctions in the semiconductor or the silicon on insulator substrate which are below the surface thereof to provide reduced junction parasitic capacitance.

The present invention further provides a semiconductor device and manufacturing process therefor in which vertical trenches are formed in the semiconductor or the silicon on insulator substrate adjacent to the sides of the semiconductor gate to expose the source/drain junctions. The contacts connect vertically to the exposed source/drain junctions either directly or through salicided contact areas to provide increased area vertical electrical connections between the contact and the silicon.

The present invention further provides a semiconductor device and manufacturing process therefor in which vertical trenches are formed in the semiconductor or the silicon on insulator substrate adjacent to the sides of the semiconductor gate to expose the source/drain junctions. The contacts connect vertically to the exposed source/drain junctions either directly or through salicided contact areas to provide a new method of forming contact to silicon connections.

The above and additional advantages of the present invention will become apparent to those skilled in the art from a reading of the following detailed description when taken in conjunction with the accompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a cross section of a semiconductor device in an initial stage of formation; [0014]
FIG. 2 is the structure of FIG. 1 after a sacrificial layer (not shown) is deposited on the semiconductor layer and patterned for the formation and growth of an insulator layer; [0015]
FIG. 3 is the structure of FIG. 2 after successive depositions of a gate dielectric, a floating gate electrode, an inner gate layer, and a control gate electrode. [0016]
FIG. 4 is the structure of FIG. 3 after a photoresist is deposited, patterned, and developed in a conventional manner followed by an etch process to remove unprotected portions of the layers above the substrate to form a gate stack; [0017]
FIG. 5 is the structure of FIG. 4 undergoing source/drain (S/D) extension junction implantation to form S/D extension junctions; [0018]
FIG. 6 is the structure of FIG. 5 having a barrier layer and a spacer layer deposited thereon; [0019]
FIG. 7 is the structure of FIG. 6 after an anisotropic etch to remove portions of the spacer layer and a subsequent etch to remove portions of the barrier layer to expose the SOI layer and to form a sidewall spacer; [0020]
FIG. 8 is the structure of FIG. 7 during a low-angle, four-quadrant implantation; [0021]
FIG. 9 is the structure of FIG. 8 after a rapid thermal anneal (RTA) which causes enhanced thermal diffusion (TED) of the S/D junctions and the S/D extension junctions; [0022]
FIG. 10 is the structure of FIG. 9 after the deposition, patterning, developing, and etching of a contact interlayer dielectric (ILD) and a channel layer ILD; [0023]
FIG. 11 is a top view of the structure of FIG. 10; [0024]
FIG. 12 is an alternate embodiment to the structure shown in FIG. 10; and [0025]
FIG. 13 is a top view of the structure of FIG. 12.[0026]

BEST MODE FOR CARRYING OUT THE INVENTION

The present invention as hereinafter described is embodied in a silicon on insulator (SOI) transistor device, but it should be understood that it is applicable to many different semiconductor devices which require reduced length and widths without a corresponding decrease in the contact area. [0027]
The term “horizontal” as used in this application is defined as a plane parallel to the conventional plane or surface of a wafer or substrate, regardless of the orientation of the wafer or substrate. The term “vertical” refers to a direction perpendicular to the horizontal as just defined. Prepositions, such as “on”, “side” (as in “sidewall”), “higher”, “lower”, “over”, and “under” are defined with respect to the conventional plane or surface being on the top surface of the wafer or substrate, regardless of the orientation of the wafer or substrate. [0028]
Referring now to FIG. 1, therein is shown a [0029] semiconductor device 10 in an initial stage of formation. A semiconductor substrate, such as a silicon substrate 12, has an insulator layer, such as a silicon oxide layer 14, and a second semiconductor substrate, such as a doped silicon on insulator (SOI) layer 16, successively deposited thereon.
Referring now to FIG. 2, therein is shown the structure of FIG. 1 after a sacrificial layer (not shown) is deposited on the [0030] SOI layer 16 and patterned for the formation and growth of an insulator layer, a field oxide 18. The sacrificial layer is removed and a chemical mechanical polishing process planarizes the field oxide and the SOI layer 16.
Chemical-mechanical polishing (referred to as “CMP”) typically involves mounting a wafer face down on a holder and rotating the wafer face under pressure against a polishing pad mounted on a polishing platen, which in turn is rotating or is in orbital state. A slurry containing a chemical that chemically interacts with the facing wafer layer and an abrasive that physically removes that layer is flowed between the wafer and the polishing pad or on the pad near the wafer. A combination of the chemical reaction between the slurry and the layer being polished and the mechanical interaction between abrasives within the slurry and the layer being polished cause the planarization of the layer. During integrated circuit fabrication, this technique is commonly applied to planarize various wafer layers, such as dielectric layers, metallization, etc. [0031]
Referring now to FIG. 3, therein is shown the structure of FIG. 2 after successive depositions of a gate dielectric, a floating gate electrode, an inner gate layer, and a control gate electrode. In the preferred embodiment, the gate dielectric layer is a gate oxide (GOX) [0032] layer 20, the floating gate electrode is a polysilicon (Si) layer 22, the inner gate layer is a tungsten (W) layer 24, and the control gate electrode is a silicon oxynitride (SiON) layer 26.
Referring now to FIG. 4, therein is shown the structure of FIG. 3 after a photoresist (not shown) is deposited, patterned, and developed in a conventional manner followed by an etch process to remove unprotected portions of the layers above the substrate to form a [0033] gate stack 28. The photoresist mask is then removed to provide the structure shown in FIG. 4.
Referring now to FIG. 5, therein is shown the structure of FIG. 4 undergoing source/drain (S/D) [0034] extension junction implantation 30 to form S/ D extension junctions 32 and 34 adjacent to the sides of the gate stack 28. The implantation 30 is a high-angle implantation to cause the dopant being implanted to be implanted under the GOX layer 20 as well as in the SOI layer 16.
Referring now to FIG. 6, therein is shown the structure of FIG. 5 having a [0035] barrier layer 38, generally an oxide layer, and a spacer layer 40, generally of an oxide or oxynitride deposited thereon. The barrier layer 38 tends to be much thinner than the spacer layer 40.
Referring now to FIG. 7, therein is shown the structure of FIG. 6 after an anisotropic etch to remove portions of the [0036] spacer layer 40 and a subsequent etch to remove portions of the barrier layer 38 to expose the SOI layer 16 and to form the sidewall spacer 44.
The [0037] sidewall spacer 44 is then used during an over-etch process of the SOI layer 16, which exposes the oxide layer 14 to form S/ D contact trenches 46 and 48.
Referring now to FIG. 8, therein is shown the structure of FIG. 7 during a low-angle, four-[0038] quadrant implantation 50. The implantation 50 implants dopants which form S/ D junctions 52 and 54 in the SOI layer 16.
Referring now to FIG. 9, therein is shown the structure of FIG. 8, after a rapid thermal anneal (RTA) which causes enhanced thermal diffusion (TED) of the S/[0039] D junctions 52 and 54 and the S/ D extension junctions 32 and 34. The S/ D junctions 52 and 54 extend vertically and the S/ D extension junctions 32 and 34 extend horizontally.
The TED causes the closest point of the S/[0040] D extension junctions 32 and 34 to be below the surface of the SOI layer 16 rather than just at the surface of the SOI layer 16 and under the GOX layer 20. This closest distance is called the “channel” and is conventionally at the surface of the silicon just below the GOX layer 20. By having the closest point of the channel in the SOI layer 16, the capacitance effect caused by the overlap of the S/ D extension junctions 32 and 34 under the GOX layer 20 and the polysilicon layer 22 are reduced. By reducing these parasitic capacitances, the performance of the semiconductor device 10 will be improved.
Also shown in FIG. 9 are salicided S/[0041] D contact areas 56 and 58 and a gate contact area 60. The contact areas are generally vertical and are of such materials as tungsten silicide (WSi) or titanium silicide (TiSi) which form in the presence of silicon. Thus, the SOI layer 16 is completely salicided.
Referring now to FIG. 10, therein is shown the structure of FIG. 9 after the deposition, patterning, developing, and etching of a contact interlayer dielectric (ILD) [0042] 62 and a channel layer ILD 64. Also shown is the deposition of a conductive metal channel 68 and a conductive metal contact 70 to the salicided contact area 56 and of a channel 72 and its contact 74 to the salicided contact area 58. The channel 68 and its contact 70 can be deposited at one time as can the channel 72 and its contact 74, which can be metals such as aluminum (Al) and tungsten (W). The conductive metal contacts 70 and 74 make and form vertical S/D contacts with the salicided contact areas 56 and 58.
Referring now to FIG. 11, therein is shown a top view of the structure of FIG. 10. A top view of the [0043] gate stack 28 is shown with the contacts 70 and 74 and the salicided contact areas 56 and 58 in the contact trenches 46 and 48. It should be noted that the contacts 70 and 74 are generally square in cross section and are not of equal length to the salicided contact areas 56 and 58, respectively. This is because the saliciding provides a sufficiently low resistance surface that a large cross-sectional contact area is not required.
Referring now to FIG. 12, therein is shown an alternate embodiment to the structure shown in FIG. 10. The same numbers are used to describe the same elements as in FIG. 10. In FIG. 12, the saliciding step is eliminated which means that [0044] contacts 70′ and 74′ will be in conductive contact directly with the SOI layer 16. Where there is direct contact between the contact metal and silicon, the conductivity will be reduced. Thus, the resistance between the contacts 70′ and 74′ and the SOI layer 16 is relatively large.
Referring now to FIG. 13, therein is shown a top view of the structure of FIG. 12. To increase the conductivity and reduce the resistance, [0045] 70′ and 74′ are made rectangular to cover as much of the S/ D junctions 52 and 54, and the S/ D extension junctions 32 and 34 as possible. Thus, the conductive metal contacts 70′ and 74′ make and form vertical S/D contacts.
While the invention has been described in conjunction with a specific best mode, it is to be understood that many alternatives, modifications, and variations will be apparent to those skilled in the art in light of the aforegoing description. Accordingly, it is intended to embrace all such alternatives, modifications, and variations which fall within the spirit and scope of the included claims. All matters set forth herein or shown in the accompanying drawings are to be interpreted in an illustrative and non-limiting sense. [0046]

Claims

The invention claimed is:

1. A semiconductor device comprising:

a semiconductor substrate;

a gate dielectric having two opposite sides disposed over the semiconductor substrate, the gate dielectric having an edge adjacent the semiconductor substrate;

a gate having two opposite sides disposed over the gate dielectric, the gate having an edge over the edge of the gate dielectric;

source/drain junctions disposed adjacent the sides of the gate dielectric in the semiconductor substrate;

the semiconductor substrate having contact trenches provided therein adjacent the sides of the gate dielectric and exposing the source/drain junctions; and

conductive contacts disposed in the contact trenches conductively connected to the source/drain junctions.

2. The semiconductor device as claimed in claim 1 wherein the conductive contacts completely fill the contact trenches.

3. The semiconductor device as claimed in claim 1 including saliciding with a metal silicide around and in the contact trenches and wherein the conductive contacts fill a portion of the contact trenches.

4. The semiconductor device as claimed in claim 1 wherein the source/drain junctions have vertical areas exposed by the contact trenches.

5. The semiconductor device as claimed in claim 1 wherein the conductive contacts have vertical conductive connections.

6. The semiconductor device as claimed in claim 1 wherein the source/drain junctions include extension source/drain junctions in the semiconductor substrate around the contact trenches, the extension source/drain junctions are closest together below the surface of the semiconductor substrate.

7. The semiconductor device as claimed in claim 1 including an insulator layer disposed below the semiconductor substrate; and a further semiconductor substrate disposed below the insulator layer.

8. The semiconductor device as claimed in claim 1 including an isolation insulator disposed around the source/drain junctions and the contact trenches, the isolation insulator disposed in the semiconductor substrate.

9. A semiconductor device comprising:

a silicon substrate;

a gate oxide layer having two opposite sides disposed over the silicon substrate, the gate oxide layer having an edge adjacent the silicon substrate;

a polysilicon gate having two opposite sides disposed over the gate oxide layer, the polysilicon gate having an edge over the edge of the gate oxide layer;

source/drain junctions disposed adjacent the sides of the gate oxide layer in the silicon substrate;

the silicon substrate having contact trenches provided therein adjacent the sides of the gate oxide layer and exposing the source/drain junctions; and

10. The semiconductor device as claimed in claim 9 wherein the conductive contacts completely fill the contact trenches.

11. The semiconductor device as claimed in claim 9 including saliciding with a metal silicide around and in the contact trenches and wherein the conductive contacts fill portions of the contact trenches.

12. The semiconductor device as claimed in claim 9 wherein the source/drain junctions have vertical areas exposed by the contact trenches.

13. The semiconductor device as claimed in claim 9 wherein the conductive contacts have vertical conductive connections.

14. The semiconductor device as claimed in claim 9 wherein the source/drain junctions include extension source/drain junctions in the silicon substrate around the contact trenches, the extension source/drain junctions are closest together below the surface of the silicon substrate.

15. The semiconductor device as claimed in claim 9 including an insulator layer disposed below the silicon substrate; and a further silicon substrate disposed below the insulator layer.

16. The semiconductor device as claimed in claim 9 including an isolation trench disposed around the source/drain junctions and the contact trenches, the isolation trench disposed in the silicon substrate.

17. A method of manufacturing a semiconductor device, comprising the steps of:

providing a semiconductor substrate;

forming a gate dielectric layer over the semiconductor substrate;

forming a gate layer over the gate dielectric layer;

etching the gate dielectric layer and the gate layer to form a gate stack;

implanting source/drain junctions adjacent the sides of the gate stack;

forming contact trenches in the semiconductor substrate to expose the source/drain junctions, the contact trenches adjacent the opposite sides of the gate stack; and

forming conductive contacts in the contact trenches conductively connected with the source/drain junctions.

18. The method of manufacturing a semiconductor device as claimed in claim 17 wherein the step of forming the conductive contacts completely fills the contact trenches.

19. The method of manufacturing a semiconductor device as claimed in claim 17 including a step of saliciding with a metal silicide around and in the contact trenches and wherein the step of forming conductive contacts fills portions of the contact trenches.

20. The method of manufacturing a semiconductor device as claimed in claim 17 wherein the step of forming the source/drain junctions implanting dopant into the exposed source/drain junctions in the contact trenches.

21. The method of manufacturing a semiconductor device as claimed in claim 17 wherein the step of forming the conductive contacts forms vertical conductive connections.

22. The method of manufacturing a semiconductor device as claimed in claim 17 wherein the step of forming the source/drain junctions include forming extension source/drain junctions in the semiconductor substrate around the contact trenches and forming the extension source/drain junctions closest together below the surface of the semiconductor substrate.

23. The method of manufacturing a semiconductor device as claimed in claim 17 including the steps of forming the semiconductor substrate on an insulator layer and. of forming the insulator layer on a further semiconductor substrate.

24. The method of manufacturing a semiconductor device as claimed in claim 17 including a step of forming an isolation insulator around the source/drain junctions and the contact trenches, the isolation insulator formed in the semiconductor substrate.

25. A method of manufacturing a semiconductor device, comprising the steps of:

providing a silicon substrate;

forming a gate oxide layer over the silicon substrate;

forming a polysilicon gate layer over the gate oxide layer;

etching the gate oxide layer and the polysilicon gate layer to form a gate stack;

implanting source/drain junctions adjacent the sides of the gate stack;

forming contact trenches in the silicon substrate to expose the source/drain junctions, the contact trenches adjacent the opposite sides of the gate stack; and

forming conductive contacts in the contact trenches in conductive connection with the source/drain junctions.

26. The method of manufacturing a semiconductor device as claimed in claim 25 wherein the step of forming the conductive contacts completely fills the contact trenches.

27. The method of manufacturing a semiconductor device as claimed in claim 25 including the step of saliciding with a metal silicide around and in the contact trenches and wherein the step of forming the conductive contacts fills portions of the contact trenches.

28. The method of manufacturing a semiconductor device as claimed in claim 25 wherein the step of forming the source/drain junctions forms vertical areas exposed by the contact trenches.

29. The method of manufacturing a semiconductor device as claimed in claim 25 wherein the step of forming the conductive contacts forms vertical conductive connections.

30. The method of manufacturing a semiconductor device as claimed in claim 25 wherein the step of forming the source/drain junctions include forming extension source/drain junctions in the silicon substrate around the contact trenches, the extension source/drain junctions are formed closest together below the surface of the silicon substrate.

31. The method of manufacturing a semiconductor device as claimed in claim 25 including the step of providing an insulator layer disposed below the silicon substrate and providing a further silicon substrate disposed below the insulator layer.

32. The method of manufacturing a semiconductor device as claimed in claim 25 including the step of forming an isolation trench around the source/drain junctions and the contact trenches, the isolation trench formed in the silicon substrate.