JP2002359372A - Semiconductor device - Google Patents

Abstract

[PROBLEMS] To reduce the on-resistance of a vertical FET while ensuring a withstand voltage. The semiconductor device includes a transistor having a vertical trench gate structure in which a high-concentration drain region, a low-concentration drain region, a channel region, and a source region are sequentially formed. The bottom of the gate conductor layer is located on a boiling layer formed by diffusion of impurities into the drain region. Further, the channel region has a lower concentration than the impurity concentration of the low concentration drain region. Since the corner of the trench does not reach the semiconductor substrate having a high impurity concentration, the reliability of the gate insulating film can be improved. In addition, the depletion layer that limits the breakdown voltage expands on the channel region side than the drain region, and the breakdown voltage is improved. An on-resistance is reduced by forming an accumulation layer in a portion of the semiconductor layer that is in contact with the trench side wall.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly, to a technology effective when applied to a semiconductor device having a trench gate structure.

[0002]

2. Description of the Related Art Power transistors are used in power amplification circuits, power supply circuits, converters, power supply protection circuits, and the like. However, these power transistors require high breakdown voltage and large current to handle large power. Required. MISFE
T (Metal Insulator Semiconductor Field Effect Tra
In the case of the transistor (nsistor), as a method of achieving a large current, it is dealt with by increasing the channel width.

In order to prevent the chip area from increasing by increasing the channel width, for example, a mesh gate structure is used. In the mesh gate structure, the gates are arranged in a planar lattice pattern to increase the channel width per unit chip area.

Conventionally, such a power FET has been used in a planar structure because of its simple process and easy formation of an oxide film serving as a gate insulating film. However, in a planar FET, when the cell size is reduced to reduce the resistance, a depletion layer of an adjacent cell collides,
The current stops flowing. Therefore, the resistance does not decrease even if the size is reduced. This is called the JFET effect. Therefore, there has been a limit in reducing the resistance of a planar FET by miniaturization.

For this reason, a FET having a trench gate structure without the JFET effect has been conceived because it is possible to further improve the degree of integration of cells and to reduce the on-resistance. What is a trench gate structure?
A conductor layer serving as a gate is provided in a groove extending through the main surface of the semiconductor substrate via an insulating film; a deep portion of the main surface of the semiconductor substrate is used as a drain region; a surface layer portion of the main surface is used as a source region; And a semiconductor layer between the source region and the source region as a channel formation region. This type of MISFET having a trench gate structure is disclosed in, for example, JP-A-8-23092.

[0006]

In such a power transistor, a reduction in on-resistance is always required. Particularly, in a low breakdown voltage product, the on-resistance is required to be reduced to the limit. Up to now, in the FET having the trench gate structure, the on-resistance has been reduced by the cell shrink that reduces the unit cell area. However, such an on-resistance reduction causes the epitaxial layer constituting the main surface of the semiconductor substrate to have a smaller overall on-resistance. The proportion occupied by resistance is increasing.
Therefore, techniques such as reducing the resistivity of the epitaxial layer in which the drain region or the channel region is formed or reducing the thickness of the epitaxial layer have been adopted. There is a limit to conversion.

An object of the present invention is to provide a technique capable of solving these problems and further reducing the on-resistance of a vertical FET. The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[0008]

SUMMARY OF THE INVENTION Among the inventions disclosed in the present application, the outline of a representative one will be briefly described.
It is as follows. A semiconductor device having a vertical transistor in which a gate conductor layer is buried via a dielectric film in a groove provided in a semiconductor substrate and a high-concentration drain region, a low-concentration drain region, a channel region, and a source region are sequentially formed. The bottom of the gate conductor layer is located on a boiling layer formed by diffusing impurities from the high-concentration drain region to the adjacent low-concentration drain region. Furthermore,
An impurity concentration of the channel region is lower than an impurity concentration of the low-concentration drain region.

According to the present invention described above, by positioning the bottom of the trench gate in the boiling layer, the corner of the trench does not reach the semiconductor substrate having a high impurity concentration, so that the reliability of the gate insulating film is improved. Can be done. Further, by setting the impurity concentration of the channel layer lower than that of the drain layer, the depletion layer for limiting the breakdown voltage spreads more to the channel region side than the drain region, and the breakdown voltage is improved. The on-resistance is reduced by forming an accumulation layer up to a low-resistance boiling layer in a portion of the semiconductor layer in contact with the trench sidewall. As a result, a power FET with low on-resistance and high reliability of the gate insulating film can be formed.

Hereinafter, embodiments of the present invention will be described. In all the drawings for describing the embodiments, components having the same functions are denoted by the same reference numerals, and repeated description thereof will be omitted.

[0011]

FIG. 1 is a partial longitudinal sectional view showing a unit cell of a vertical power MISFET used in a semiconductor device according to the present embodiment. This vertical power MISFET
Is formed on an n + type semiconductor substrate 1 made of, for example, single crystal silicon.
For example, the epitaxial layer 2 is formed by epitaxial growth.
Is formed on the semiconductor substrate on which is formed. This MISFET
In a cell formation region surrounded by a field insulating film provided in a rectangular ring along the outer periphery of a semiconductor substrate, cells having a trench gate structure having a stripe shape, a rectangular shape, or a polygonal shape in a planar shape are regularly arranged. A plurality of gates are arranged in a stripe or lattice shape in a plane, and the cells are connected in parallel to form a stripe or mesh gate structure.

In each cell, an n− type lightly doped drain region 2a is formed on an n + type semiconductor substrate 1, which is a heavily doped drain region, a p type channel region 2b is formed on a lightly doped drain region 2a, and a channel region is formed. N + type source region 2
This is a vertical FET in which c is formed.

The gate conductor layer 3 is formed via a gate insulating film 4 in a groove extending from the main surface of the semiconductor substrate to the low concentration drain region 2a. The gate conductor layer 3 is made of, for example, polycrystalline silicon doped with impurities, and the gate insulating film 4 is made of, for example, a silicon oxide multilayer film in which a thermal oxide film and a deposited film are sequentially formed.

The upper surface of the gate conductor layer 3 according to the present embodiment is covered with a cap insulating film 5. For example, silicon is applied to the exposed source region 2 c of the semiconductor substrate main surface defined by the cap insulating film 5. The source electrode 6 using the contained aluminum is electrically connected.
Further, the gate conductor layer 3 is connected to a gate electrode in the same layer as the source electrode 6 at a peripheral portion of the semiconductor substrate.

On the entire surface of the main surface of the semiconductor substrate, for example, a silicon oxide film by a plasma CVD method using tetraethoxysilane (TEOS) gas as a main source gas and a protective insulating film 7 using polyimide are formed. Insulating film 7
An opening for partially exposing the gate electrode and the source electrode 6 connected to the gate conductor layer 3 is provided. The opening serves as a connection region for the gate and the source, and the connection region is electrically connected by wire bonding or the like. Done.

As a drain connection region, a drain electrode 8 conducting to the n + type semiconductor substrate 1 is formed on the entire back surface of the semiconductor substrate, for example, a metal layer in which nickel, titanium, nickel and silver are sequentially laminated, or titanium, nickel And gold are sequentially laminated, and the surface using the silver or gold of the drain electrode 8 is connected to a lead frame by, for example, a conductive adhesive material, so that electrical connection is made.

The n + type semiconductor substrate 1 has a high impurity concentration to reduce the resistance. Since the low concentration drain region 2a is in contact with the semiconductor substrate 1, the n + type semiconductor substrate 1 has a low impurity concentration. A so-called boiling, in which impurities penetrate into the drain region 2a, occurs. Therefore, as shown in FIG. 2, a boiling layer 12 having a high impurity concentration is formed at a portion in contact with the semiconductor substrate 1 as shown in the profile of the impurity concentration. 12, the impurity concentration of the epitaxial layer 22 of the drain region 2a in contact with the channel region 2c is also high. In the present embodiment, the bottom of the trench gate is located in this boiling layer 12, and it is therefore desirable that the thickness of the boiling layer 12 be 1 μm or more.

The boiling layer 12 is removed from the semiconductor substrate 1.
Since the change in the impurity concentration from the boiling layer 12 and the change in the impurity concentration from the boiling layer 12 to the epitaxial layer 22 are continuous, the boundary of the boiling layer 12 is not clear. Therefore, here, the range in which the impurity concentration changes by 20%, that is, the impurity concentration is 0.8 times (80 times) the concentration of the semiconductor substrate 1.
%) To 1.2 times the concentration of the epitaxial layer 22 (12
0%) (for example, when the impurity concentration of the semiconductor substrate 1 is 1E18 / cm ⁻³ and the impurity concentration of the epitaxial layer 22 is 1E16 / cm ⁻³ , the impurity concentration is 8E1).
The region that changes from 7 / cm ^{−3 to} 1.2E16 / cm ⁻³ ) is defined as the boiling layer 12.

By locating the bottom of the trench gate in the boiling layer 12, the corner of the trench does not reach the semiconductor substrate 1 having a high impurity concentration, so that the reliability of the gate insulating film 4 can be improved. it can. As described above, the reliability can be further improved by forming the gate insulating film 4 as a multilayer film in which a thermal oxide film and a deposited film are sequentially formed as described above.

That is, although the thermal oxide film as the gate insulating film 4 has good film quality and excellent interface characteristics with the semiconductor substrate, it is formed while taking in impurities of the semiconductor substrate during oxidation. The impurities remaining in the metal lower the reliability. However, since the deposited film does not contain impurities,
By forming the insulating film with a multilayer film in which a thermal oxide film and a deposited film are sequentially formed, the reliability is improved as compared with the case where the insulating film having the same withstand voltage, that is, the same thickness is formed only with the thermal oxide film. I do.

As exemplified by a broken line in FIG.
Conventionally, the impurity concentration of the channel region 2b is
In this embodiment, the impurity concentration of the channel region 2b is set higher than the impurity concentration of the drain region 2a.
Is lower than the impurity concentration. For this reason, the depletion layer that limits the breakdown voltage is larger in the channel region 2 than the drain region 2a.
Since the expansion is performed on the b side, the withstand voltage is improved.

On the other hand, when a voltage is applied to the gate conductor layer 3 to turn on the FET, carriers are accumulated in a portion of the epitaxial layer 2 which is in contact with the trench side wall, as shown by a broken line in FIG. An accumulation layer 9, which is a layer, is formed. Since the low-resistance accumulation layer 9 is formed up to the boiling layer having a high impurity concentration, the on-resistance is reduced. Therefore, it is possible to form a power FET of the gate insulating film 4 with low on-resistance and high reliability.

In the power transistor of the present embodiment,
Since the on-resistance is low and the avalanche resistance is high, the VRM (Voltage Reg
ulator Module) is effective. In a personal computer, the operating voltage of an arithmetic unit (CPU) for processing data for high-speed processing and low power consumption is 2
In many cases, the operating voltage is changed to V or less depending on the situation. For this reason, the prepared power supply voltage of 5 V
Alternatively, a VRM is used to stably supply an operating voltage obtained by lowering 3.3 V. In such a VRM,
As shown in FIG. 3, two powers F
The ET is turned on and off alternately to convert the 5V or 3.3V power supply voltage input from the terminal Vin into a predetermined operating voltage of 2V or less, smooth the voltage with the choke coil L and the capacitor C, and supply the same to the CPU from the terminal Vout. .

The power transistor of the present embodiment is also effective when used in a protection circuit for a lithium ion battery used in a mobile phone.

As described above, the invention made by the present inventor is:
Although the present invention has been specifically described based on the above embodiments, the present invention is not limited to the above embodiments, and it is needless to say that various modifications can be made without departing from the gist of the present invention. For example, in the above description, the n-type power M
Although the ISFET has been described, the present invention can be applied to a p-type power MISFET, and the power M
In addition to ISFET, IGBT (Integrated Gate Bipo
lar Transistor).

[0026]

The effects obtained by the representative ones of the inventions disclosed in the present application will be briefly described as follows. (1) According to the present invention, there is an effect that the reliability of the gate insulating film can be improved by locating the bottom of the trench gate in the boiling layer. (2) According to the present invention, by setting the impurity concentration of the channel layer lower than the impurity concentration of the drain layer, the depletion layer for limiting the breakdown voltage spreads more to the channel region side than the drain region, thereby improving the breakdown voltage. There is an effect that can be. (3) According to the present invention, since the accumulation layer is formed up to the boiling layer in the portion of the semiconductor layer in contact with the trench side wall, there is an effect that the on-resistance can be reduced. (4) According to the present invention, the above effects (1), (2), and (3) have an effect that the ON resistance can be reduced and the reliability of the gate insulating film can be increased.

[Brief description of the drawings]

FIG. 1 is a longitudinal sectional view showing a semiconductor device according to an embodiment of the present invention.

FIG. 2 is a graph showing an impurity concentration profile of the semiconductor device shown in FIG.

FIG. 3 is an equivalent circuit diagram of a VRM using a semiconductor device according to an embodiment of the present invention.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Semiconductor base, 2 ... Epitaxial layer, 2a ... Low-concentration drain region, 2b ... Channel region, 2c ... Source region, 3 ... Gate conductor layer, 4 ... Gate insulating film, 5 ... Cap insulating film, 6 ... Source electrode, 7: protective insulating film, 8: drain electrode, 9: accumulation layer, 12: boiling layer, 22: epitaxial layer.

Claims (4)

[Claims] 1. A vertical transistor in which a gate conductor layer is buried in a groove provided in a semiconductor substrate via an insulating film, and a high-concentration drain region, a low-concentration drain region, a channel region, and a source region are sequentially formed. Wherein the bottom of the gate conductor layer is located in a boiling layer formed by diffusing impurities from the high-concentration drain region to an adjacent low-concentration drain region. apparatus. 2. A vertical transistor in which a gate conductor layer is buried in a groove provided in a semiconductor substrate via an insulating film, and a high-concentration drain region, a low-concentration drain region, a channel region, and a source region are sequentially formed. Wherein the bottom of the gate conductor layer is located in a boiling layer formed by diffusing impurities from the high-concentration drain region to an adjacent low-concentration drain region, and the impurity in the channel region is provided. A semiconductor device having a concentration lower than the impurity concentration of the low-concentration drain region. 3. The semiconductor device according to claim 1, wherein the boiling layer has a thickness of 1 μm or more. 4. The semiconductor device according to claim 1, wherein said insulating film is formed by laminating a thermal oxide film and a deposited film.
The semiconductor device according to claim 1.