JP2008199037A - Power semiconductor device and power supply circuit - Google Patents

Abstract

An ON resistance per chip area of a lateral power MOSFET is reduced.
A lateral power MOSFET according to the present invention is a low-resistance punching that penetrates from a semiconductor surface in a p-type semiconductor region on a low-resistance p-type semiconductor substrate connected to an external source electrode to the p-type semiconductor region. A conductive region is provided, two or more n-type drain regions electrically connected to the drain electrode are formed in a semiconductor region sandwiched between the low-resistance punched conductive regions, and an external drain region on the active region is provided.
[Selection] Figure 1

Description

  The present invention relates to a high-frequency compatible power semiconductor device, and more particularly, to a low on-resistance of a high-frequency compatible power MOSFET and a power supply circuit system using the same.

  Conventionally, vertical power MOSFETs with excellent low on-resistance have been mainly used in DC / DC power supply circuits such as personal computers and VRMs. However, as power supply circuits have become higher in frequency, power supply efficiency has been improved in the past. In addition to the demanded low on-resistance of power MOSFETs, a reduction in feedback capacitance has been demanded. For example, in the case of a Buck type power supply circuit, in order to reduce the switching loss of the upper power MOSFET, it is necessary to reduce the feedback capacitance for high efficiency.

  There is a lateral power MOSFET as a structure that can reduce the feedback capacitance, but there is a problem that it is difficult to reduce the on-resistance per chip area. In particular, in the case of a lateral power MOSFET using a substrate as a source electrode, since the area of the low resistance punching diffusion layer that connects the semiconductor back surface and the semiconductor surface to a low resistance is large, it is further difficult to reduce the on-resistance per chip area.

As a method for reducing the on-resistance per chip area in the lateral power MOSFET, the above-mentioned low resistance punching diffusion layer is separated from the source layer by a p-type punching diffusion layer portion that serves as a current path between the low resistance source substrate and the semiconductor surface, Japanese Laid-Open Patent Publication No. 6-232396 (Patent Document 1) discloses a method in which an area corresponding to a required resistance value is formed and connected by metal wiring.
JP-A-6-232396

  In JP-A-6-232396, although attention is paid to reducing the p-type punching diffusion layer portion in order to reduce the on-resistance per chip area, the p-type punching diffusion layer portion is removed from the source layer. No suitable specific proposal has been made regarding a planar structure and a sectional structure including a specific electrode wiring structure. For this reason, there has been a problem that the on-resistance cannot always be reduced. Moreover, the parasitic resistance reduction method and mounting method of a conventional power transistor having a drain withstand voltage specification of about 30 V or less have not been sufficiently studied.

  Furthermore, an effective connection method of a Schottky diode connected to prevent the parasitic diode operation of the power MOSFET and improve the efficiency of the power supply circuit or the like has not been sufficiently studied.

  An object of the present invention is made in consideration of the above-described problems, and relates to a feedback capacitance and an on-resistance of a power semiconductor device, and provides a method for improving the efficiency of a circuit in which the semiconductor device is used. There is to do.

The outline of the semiconductor device of the present invention is enumerated as follows.
(1) A multi-drain type element in which two or more drain regions are provided between the low-resistance punched diffusion layers 3 of the lateral power MOSFET.
(2) In order to realize a multi-drain lateral power MOSFET, the planar layout of the first electrode layer 12a has been made new.
(3) A lateral power MOSFET in which a drain pad is provided on an active region.
(4) The low-resistance punched conductive region forms a low-resistance p-type semiconductor region or a silicon trench with a small planar size, and is embedded with an elongated polycrystalline silicon layer or metal layer.
(5) The lead is electrically connected to the external terminal region through a bump electrode or a conductive adhesive so as to cover the main active region. Particularly, as a means for connecting the power transistor and the Schottky diode in parallel, they are arranged adjacently and connected.
(6) Transistors are connected vertically through bumps.
(7) A pre-driver transistor is provided on the same chip as the power transistor.
(8) The power transistor chip input and the control IC output terminal are connected by a lead wire using a bump at the external gate terminal or the external input terminal.
(9) A metal or a metal compound is embedded in at least a part of the low-resistance semiconductor substrate so that the resistance in the thickness direction of the low-resistance semiconductor substrate decreases.
(10) The thickness of the low resistance semiconductor substrate with a power transistor with a withstand voltage of 100 V or less is set to 60 μm or less.

  According to the semiconductor device of the present invention, power semiconductor devices such as power transistors can be reduced in loss and capacity, and adverse effects due to parasitic impedance can be reduced. Further, the efficiency of the power supply circuit can be improved by using the power transistor of the present invention.

  As described above, according to the present invention, a power MOSFET having a low capacitance, a low on-resistance, and a low parasitic inductance can be realized, which is effective in reducing the cost of an element and improving the efficiency of a power supply device using the power MOSFET. .

  Hereinafter, the power supply apparatus according to the present invention will be described in detail with reference to the accompanying drawings.

<Example 1>
FIG. 1 is a cross-sectional view of a power semiconductor device according to the present embodiment, FIG. 2 is a plan view, and FIG. 3 is a cross-sectional view taken along line aa and bb in FIG. As shown in FIGS. 1 to 3, a p-type epitaxial layer 2 a having a higher resistance than the p-type semiconductor substrate 1 is provided on a p-type semiconductor substrate 1 that is a low-resistance substrate connected to the back electrode 17, and p The type epitaxial layer 2 has a low resistance punching diffusion layer 3 penetrating from the semiconductor surface to the p type semiconductor substrate 1, and the p type epitaxial layer 2a sandwiched between the low resistance punching diffusion layers 3 has a low resistance punching diffusion layer. 3 and an n-type source region 8c formed adjacent to the low resistance punching diffusion layer 3 are provided. Reference numeral 8b denotes an n-type drain region.

  As shown in FIG. 2 and FIG. 3B, the n-type source region 8c formed away from the low-resistance punched diffusion layer 3 is connected to the low-resistance punched diffusion layer 3 via the tungsten plug 11 and the first electrode layer 12a. It is connected. The n-type drain region 8b is connected to the second electrode layer 14a through the tungsten plug 11 and the first electrode layer 12b, and the second electrode layer 14a portion not covered with the protective film 15, that is, 16a is an external drain electrode. It is an electrode pad that acts as. Here, the electrode pad 16c is formed via the insulating layer 10 on the active region where the transistor-operated gate electrode 6a is disposed.

  In the conventional lateral power transistor, the first electrode layer 12b and the gate electrode 6a on the n-type drain region 8b are extended to the outside of the active region, and the drain electrode pad and the gate electrode pad are provided outside the active region. . For this reason, the first electrode layer 12a, which is a drain electrode, is elongated to increase the drain resistance, and the active region becomes smaller due to the space of the drain pad region. In contrast, in this embodiment, the drain resistance can be reduced.

  By the way, although the lateral transistor structure has a small capacitance between the drain and the gate, the low resistance punching diffusion layer 3 is usually formed by a diffusion process, so that not only the vertical direction but also the horizontal direction diffusion proceeds, so the on-resistance per unit area is reduced. There was a problem that was difficult to do.

  In the present embodiment, the low resistance punching diffusion layer 3 is formed by a new wiring method from the n-type source region 8c formed away from the above-described low resistance punching diffusion layer 3 to the first electrode layer 12a. In the meantime, only one n-type drain region 8b is arranged, but two n-type drain regions 8b can be arranged. In the prior art, two source regions are arranged between the low resistance punching diffusion layers 3. In this embodiment, three source regions are arranged (one source diffusion region not provided adjacent to the low resistance punching diffusion layer 3). Can be increased). For this reason, the gate width of the MOSFET per unit area becomes long, and the on-resistance can be reduced. In this embodiment, three source regions and two drain regions are formed between the low-resistance punched diffusion layers 3. Similarly, five source regions and three drain regions are used. It is also possible to arrange a larger number of source regions and drain regions.

  In the present embodiment, there is shown a case where there are three source regions provided between the low resistance punching diffusion layers 3 (one source diffusion region not provided adjacent to the low resistance punching diffusion layer 3). Although the channel resistance increases as the number of n-type source regions 8c not provided adjacent to the diffusion layer 3 increases, the low resistance punching diffusion layer 3 and the n-type drain region 8b (current flows in the depth direction in FIG. 2). The resistance component and the resistance component of the source first electrode layer 12a increase. For this reason, when the drain withstand voltage is about 30V to 40V or less, the n-type source region 8c, which is not normally provided with the low resistance punching diffusion layer 3 adjacent thereto, has an on-resistance per unit area in the range of one to three. There is a minimum value.

  The n-type drain region 8b, the source electrode and the p-type region 4a are p-well regions and are formed under the n-type source regions 8a and 8c and the gate electrode layer 5 in order to control the threshold voltage. In 11a to 11d, a second electrode layer 14 is formed via a tungsten plug, a first electrode layer 12, and an insulating layer 13.

  In this embodiment, a low concentration n-type semiconductor region 7 is provided adjacent to the n-type drain region 8b in order to ensure a high drain-source breakdown voltage.

  Note that the semiconductor device of this embodiment has an n-channel MOSFET (gate electrode 6b, source diffusion layer 8d, drain diffusion layer 8a, low-concentration drain diffusion layer 7b) for shutting down the power MOSFET, and an n-well diffusion layer 18 as low as possible. A p-channel MOSFET (gate electrode 6c, source diffusion layer 9d, drain diffusion layer 9c, low-concentration drain diffusion layer 19) or gate electrode 6d for turning on the power MOSFET by adding a concentration p-type diffusion region to the process is used. The capacitor can be formed on the same chip. Further, an increase in the occupied area can be prevented by arranging the capacitor under the electrode pad 16b.

  Reference numeral 14b is a second electrode layer formed simultaneously with 14a and 14c, and is disposed between the power transistor and the control MOSFET in order to reduce noise from the power transistor.

  In the present embodiment, the lateral power MOSFET in the case of the p-type epitaxial layer 2a has been described as an example, but the same applies to the lateral power MOSFET in which the corresponding semiconductor layer is an n-type epitaxial layer.

<Example 2>
FIG. 4 is a circuit diagram of the power semiconductor device of this embodiment. The power semiconductor device of the first embodiment can be used for the upper arm power MOSFET chip 401 or the lower arm power MOSFET chip 402 or both. The circuit of this embodiment is a Buck type power supply circuit that is a non-insulated DC / DC power supply circuit, and is a circuit that obtains an output voltage Vout of 5V to 0.5V by reducing the voltage of the input voltage Vin of about 48V to 5V. is there. Reference numeral 311 denotes a load such as a microprocessor, 309 denotes an inductance, and 310 denotes a capacitor. The power MOSFETs 401 and 402 incorporate power MOSFETs 100 and 200, and in this embodiment, n-channel MOSFETs 103 and 203 and gate protection polycrystalline silicon diodes 107 and 209 are shown.

  The external drain terminals are 501 and 505, the external source terminals are 502 and 506, the external gate terminals are external terminals 509 and 510, and external input terminals 503 and 507 for shutting off the power MOSFETs 100 and 200 are provided.

  Reference numeral 403 is a control IC, 303 and 314 are switches for turning on the power MOSFET 100, and 313 is a switch for turning off the power MOSFET 100. 315 and 317 are switches for turning on the power MOSFET 200, 316 is a switch for turning off the power MOSFET 200, 307 is a booster circuit for controlling the gate voltage of the power MOSFET to be equal to or higher than Vin, and 302 and 301 are bootstraps. Circuit diodes and capacitors. Here, when a power source higher than Vin can be used to turn on the upper arm power MOSFET 100, 302, 301, and 307 can be omitted. Reference numerals 509, 514, 515, 516, and 517 are external terminals of the control IC 403.

  When the lateral power MOSFET of the first embodiment is used for the upper arm power MOSFET chip 401, the power supply efficiency can be improved because the feedback capacitance is small and the on-resistance is low. Further, when the lateral power MOSFET of the first embodiment is used for the lower-arm power MOSFET chip 402, the feedback capacitance is small, so that the power MOSFET 100 is turned on when the drain voltage increases rapidly, that is, when the power MOSFET 200 is turned off. At this time, the voltage of the internal gate terminal coupled by the drain-gate capacitance rises, and the self-turn-on malfunction that the power MOSFET is turned on even if it is going to be shut off by an external circuit can be prevented and the loss can be reduced. Even if the control n-channel MOSFETs 103 and 203 are not built in, it is effective for increasing the efficiency.

  Further, when the n-channel MOSFETs 103 and 203 are built on the same chip as the power MOSFETs 100 and 200, the parasitic gate impedance can be reduced, so that the power MOSFETs 100 and 200 can be accurately controlled off even when the gate drive frequency increases. This stabilizes the output voltage Vout and stabilizes the output current flowing through the load, thereby improving the efficiency of the power supply.

<Example 3>
FIG. 5 is a circuit diagram of the power semiconductor device of this embodiment. The power semiconductor device of the first embodiment is used for one or both of the upper arm power MOSFET chip 401 and the lower arm power MOSFET chip 402 of the present embodiment.

  The difference between the present embodiment and the second embodiment is that the p-channel MOSFETs 102, 104, 202, and 204 are built in the power MOSFET chip. As a result, the number of external terminals of the power MOSFET chip can be reduced, and the configuration of the control IC 403 is simplified. Gate protection diodes 106 and 206 are also added. Furthermore, the capacitors 108 and 208 are also built in with the structure shown in the first embodiment. This capacitor is provided to stabilize the power supply voltage of the control MOSFET. The capacitances of the capacitors 108 and 208 are preferably larger than the gate capacitance of the power MOSFET. Therefore, when the capacitors 108 and 208 and the gate oxide film of the power MOSFET have the same thickness, it is desirable to make the gate oxide film area of the capacitor larger than the gate oxide film area of the power MOSFET. Reference numerals 509, 510, 511 and 512 are external terminals of the control IC. The switches 303 and 305 are used to raise the external input terminals 503 and 507 of the power MOSFET 401 and 402 chips, and the switches 304 and 306 are used to lower the external input terminals 503 and 507 of the power MOSFET 401 and 402 chips. Used for. In this embodiment, in order to make the internal gate voltage of the power MOSFETs 100 and 200 and the phase of the external gate terminals of the power MOSFET chips 401 and 402 the same, a two-stage CMOS circuit is built in the power MOSFET chip. This is because a signal from a control IC that drives a normal power MOSFET is used. If it is not necessary to be compatible with a normal power MOSFET, the CMOS inverter may be a single stage.

  In this embodiment, since the p-channel MOSFET is also formed on the same chip, the power MOSFET can be turned on with low impedance, and the power MOSFET can be turned on more accurately even when the gate drive frequency is increased.

<Example 4>
6 and 7 are schematic views of the power semiconductor device of this embodiment. The present embodiment is a method of mounting a power MOSFET so that the parasitic resistance is reduced by taking the circuit shown in FIG. 4 as an example. 6 is a plan view, and FIG. 7 is a cross-sectional view taken along the lines aa ′, bb ′, and cc ′ shown in FIG.

  In this embodiment, both the external drain terminals 501 and 505 and the external source terminals 502 and 506 of the power MOSFET chips 401 and 402 are electrically conductive adhesives such as solder, bumps 900 and the like without using conventional bonding wires. It is in surface contact with the metal substrate which is the conductive electrode 800 which becomes the ground through the conductive electrode. Here, the conductive electrodes 800, 801, and 802 have a thickness of 0.2 mm or more and a maximum cross-sectional length of 1 mm or more. In addition, the external drain terminals 501 and 505, the external source terminals 502 and 506, etc., which are all main current external terminals of the power semiconductor element, cover at least 60% or more of the area of the active region, that is, the region where the transistor operation or rectification operation is performed. Is formed.

  For this reason, the resistance of the power MOSFET and the Schottky diode can be reduced, and adverse effects due to parasitic inductance can be reduced. In particular, a Schottky diode 308 connected in parallel with the power MOSFET 200 and a semiconductor chip are arranged adjacent to each other, and a conductive adhesive such as solder or a bump as the conductive electrode 900 is used by using the common conductive electrodes 800 and 802. Is connected to low impedance. In the prior art, since a bonding wire is used, there is an inductance that cannot be ignored in series with the power MOSFET 200 and the Schottky diode 308. For this reason, there is a problem that it takes a long time to switch the current between the power MOSFET 200 and the Schottky diode 308 and the loss of the power supply circuit cannot be reduced. However, in this embodiment, the loss can be reduced. In this embodiment, the case where a large number of elements are arranged in the package is described. However, when only the power MOSFET 200 and the Schottky diode 308 are enclosed in the same package, or the power MOSFET 200 and the Schottky diode 308 are formed on the same chip. And the power MOSFET 200 and the Schottky diode 308 may be connected to each other via a conductive adhesive such as solder or a conductive electrode such as a bump without using a bonding wire.

  In this embodiment, the conductive electrodes 808 and 810 are also used for the wiring between the control IC and the input terminal of the power transistor chip, and the impedance is lowered through a conductive adhesive such as solder or a bump as the conductive electrode 900. Connected. Reference numerals 805, 806, 807, and 809 are lead wires (conductive electrodes) from the control IC and are connected to the external terminals 516, 517, 518, and 519 of the control IC by bumps. In this case, since the signal from the control IC is transmitted to the gate of the power MOSFET chip with low impedance, malfunction and control delay are reduced even when the control circuit is not built in the power MOSFET chip.

  In this embodiment, the power MOSFET 100 and the power MOSFET 200 that operate differently in the same package are connected. However, the semiconductor chips are stacked vertically using the bumps or the conductive adhesive shown in this embodiment. The method of connecting and wiring using a low resistance plate such as a lead wire can also be used for connecting external terminals of two or more semiconductor chips in parallel in a package. That is, the power MOSFET chip can be used to connect the external drain terminal, the external source terminal, and the external gate terminal in parallel in the package. Alternatively, the external anode terminal and external cathode terminal of the diode can be used in parallel connection within the package. In this case, there is an effect that the on-resistance seen from the user can be reduced without improving the on-resistance of the semiconductor element as the chip performance. Further, by reducing the silicon chip thickness of the transistor chips to be stacked vertically (for example, 100 μm or less), an increase in the thickness of the package can be suppressed.

<Example 5>
FIG. 8 is a cross-sectional view of the power semiconductor device of this embodiment. In this embodiment, instead of the low resistance punching diffusion layer 3 of the first embodiment, a narrow and narrow groove is formed by anisotropic etching in a silicon chip, and polycrystalline silicon doped with impurities is embedded in the low resistance. Changed to punching area 3a. In this case, even if the dimension X is the same, the dimension Y can be narrowed, so the on-resistance per unit area can be further reduced. Further, in order to further reduce the on-resistance, it is desirable to reduce the thickness Z of the p-type semiconductor substrate 1 so that the thickness of the semiconductor chip is 60 μm or less. This is effective when the on-resistance of the power MOSFET is 3 mΩ or less or when the withstand voltage specification between the drain and source is 30 V or less. This is because the low resistance substrate of silicon is currently limited to about 2 to 3 mΩcm. Therefore, unless the resistance of the thick silicon of about 200 μm applied to the power element of the prior art is reduced to 60 μm or less, the on-resistance component This is because the balance is poor. Furthermore, when using a substrate such as SiC, which has a resistance to decrease in substrate resistance, the resistivity of the SiC substrate is about five times that of silicon. Is less than 300V. In order to make the drain breakdown voltage specification 30V or less, it is necessary to effectively make the SiC substrate 12 μm or less.

<Example 6>
FIG. 9 is a cross-sectional view of the power semiconductor device of this embodiment. In this embodiment, instead of the low resistance punching diffusion layer 3 of the first embodiment, a deep and narrow groove is formed by anisotropic etching on a silicon chip, and a plug 3b made of a metal such as tungsten or a metal compound is embedded therein. Reduce the effective wafer thickness. In the case of this embodiment as well as the fifth embodiment, even if the dimension X is the same, the dimension Y can be narrowed, so that the on-resistance per unit area can be further reduced, and the low efficiency of the low-resistance punching region 3a is lowered. Can be realized.

  As a method for reducing the resistance of the p-type semiconductor substrate 1, in this embodiment, a silicon groove is formed, and a metal such as copper or aluminum or a metal compound 20 is embedded therein. In this embodiment, the metal or metal compound 20 is used to reduce the resistance of the silicon thickness not sufficiently reduced. In the case of the present embodiment, the effective thickness U of the semiconductor substrate 1 (the thickness of the semiconductor substrate where the metal or metal compound 20 does not enter) can be set to 20 μm or less. This is effective in reducing the substrate resistance component of a power transistor in which the substrate resistance is unlikely to decrease.

  FIG. 9 shows a case where a metal or metal compound 20 is embedded in a fine etching groove, but only a part of the silicon chip, for example, immediately below the active region, is etched so that the silicon chip is not easily broken, and a conductive adhesive such as solder is mounted during mounting. The same applies to filling with a metal or a metal compound.

  Although the present invention has been specifically described above based on the embodiments, it is needless to say that the present invention is not limited to the above-described embodiments and can be variously modified without departing from the gist thereof. For example, although the case of a flat package structure has been described as the packaging structure, the present invention is not limited to this and can be variously modified. For example, a BGA (Ball Grid Array) package structure may be used. The transistor is not limited to a power MOSFET, and may be a junction field effect transistor, SIT, or MESFET. Further, the above description has been given mainly for the case where the present invention is applied to a DC / DC power supply. However, the present invention is not limited to this, and can be applied to power supply circuits of other circuits.

1 is a cross-sectional view of a power semiconductor device of Example 1. FIG. 1 is a plan view of a power semiconductor device of Example 1. FIG. 1 is a cross-sectional view of a power semiconductor device of Example 1. FIG. 6 is a circuit diagram of a power semiconductor device of Example 2. FIG. 6 is a circuit diagram of a power semiconductor device of Example 3. FIG. 6 is a plan view of a power semiconductor device of Example 4. FIG. FIG. 6 is a cross-sectional view of a power semiconductor device of Example 4. FIG. 6 is a cross-sectional view of a power semiconductor device of Example 5. 6 is a cross-sectional view of a power semiconductor device of Example 6. FIG.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 1 ... p-type semiconductor substrate, 2, 2a ... p-type epitaxial layer, 3 ... Low resistance punching diffusion layer, 3a ... Low resistance punching region, 3b ... Plug, 4a ... p-type region, 5 ... Gate electrode layer, 6a, 6b , 6c, 6d ... gate electrode, 7 ... low concentration n-type semiconductor region, 7b, 19 ... low concentration drain diffusion layer, 8a, 8c ... n-type source region, 8b ... n-type drain region, 8d, 9d ... source diffusion layer , 9c ... drain diffusion layer, 10, 13 ... insulating layer, 11, 11a, 11b, 11c, 11d ... tungsten plug, 12, 12a, 12b ... first electrode layer, 14, 14a, 14b, 14c ... second electrode layer 15 ... protective film, 16a, 16b, 16c ... electrode pad, 17 ... back electrode, 18 ... n-well diffusion layer, 20 ... metal or metal compound, 100, 200 ... power MOSFET, 102, 104, 202, 04 ... p-channel MOSFET, 103,203 ... n-channel MOSFET, 106,206 ... diode, 107,209 ... polycrystalline silicon diode, 108,208,301,302,310 ... capacitor, 303,304,305,306,313 , 314, 315, 316 ... switch, 307 ... booster circuit, 308 ... Schottky diode, 309 ... inductance, 311 ... load, 401, 402 ... power MOSFET chip, 501, 505 ... external drain terminal, 502, 506 ... external source terminal , 503, 507 ... external input terminals, 509, 510, 511, 512, 513, 514, 515, 516, 517, 518, 519 ... external terminals of the control IC, 800, 801, 802, 803, 808, 810, 900: Conductive electricity , 805,806,807,809 ... leads.

Claims (19)

A power transistor drain low resistance semiconductor region, a source low resistance semiconductor region and a gate electrode are provided on the first surface of the semiconductor chip, and an external source terminal is connected to the low resistance substrate region which is the second surface of the semiconductor chip. And
In order to form a low-resistance ohmic connection between the low-resistance semiconductor region for source and the low-resistance substrate region, a low-resistance punched conductive region is provided between the first surface and the second surface of the semiconductor chip. ,
A power semiconductor device, wherein a drain external terminal is formed in a region where an insulating layer is separated on a transistor active region where the gate electrode is formed.   2. The power semiconductor device according to claim 1, wherein the low resistance punching conductive region is a semiconductor region of the same conductivity type as the low resistance substrate region.   2. The power semiconductor device according to claim 1, wherein a part of the low resistance punching conductive region is a metal or a metal compound.   4. The power semiconductor device according to claim 3, wherein a part of the low resistance punching conductive region is tungsten or a tungsten compound.   2. The power semiconductor device according to claim 1, wherein a part of the low resistance punching conductive region is a low resistance polycrystalline silicon layer.   6. The elongated structure according to claim 1, wherein a value obtained by dividing the length of the low-resistance punching conductive region by the minimum width of the low-resistance punching conductive region is 1.5 or more. Power semiconductor device.   2. The drain external terminal and the package lead cover more than half of the active region of the power transistor and are electrically connected to the drain external terminal region through a bump electrode. 6. The power semiconductor device according to any one of items 5.   A conductive electrode plate is used as means for connecting the cathode external terminal of the Schottky diode and the anode external terminal in parallel with the drain external terminal and the source external terminal of the power transistor, and the conductive electrode plate and the external terminal A power semiconductor device characterized by being connected to an electrode.   The drain external terminal or the source external terminal is vertically stacked with a drain external terminal of a second transistor or a source external terminal of the second transistor via a bump. The power semiconductor device according to any one of claims 1 to 8.   The power transistor, an external gate terminal for turning on the power transistor, a pre-driver transistor used for turning off the power transistor, and an external input terminal for controlling the pre-driver transistor on the same chip The power semiconductor device according to claim 1, wherein the power semiconductor device is provided on the power semiconductor device.   10. The power transistor, a pre-driver transistor that controls the power transistor, and an external input terminal that controls the pre-driver transistor are provided on the same chip. The power semiconductor device according to the item.   A control IC and the power transistor are built in the same package, and the output terminal of the control IC and the external gate terminal or external input terminal of the power transistor are connected by a lead wire to drive the power transistor. The power semiconductor device according to any one of claims 1 to 11.   The metal or metal compound is embedded in at least a part of the low-resistance semiconductor substrate so that the resistance in the thickness direction of the low-resistance semiconductor substrate is lowered. Power semiconductor device.   The metal of any one of claims 1 to 9, wherein at least a part of the low resistance substrate is etched and a metal is embedded in a mounting process so that the resistance in the thickness direction of the low resistance substrate is lowered. Power semiconductor device.   The power semiconductor device according to any one of claims 1 to 14, wherein the power transistor is a power MOSFET.   16. The power semiconductor device according to claim 1, wherein the power transistor is a junction field effect transistor.   A semiconductor device comprising a drain using a silicon low resistance semiconductor substrate, a source and a gate, wherein the drain-source breakdown voltage is 30 V or less and the thickness of the silicon low resistance semiconductor substrate is 60 μm or less. A power semiconductor device.   15. The power semiconductor device according to claim 13, wherein the low-resistance semiconductor substrate or the low-resistance substrate is SiC.   18. A power supply circuit using the power semiconductor device according to claim 1 as a DC / DC power supply transistor.