JP2003008019A - Semiconductor device - Google Patents

Abstract

[PROBLEMS] To reduce the on-resistance of a vertical FET while ensuring a withstand voltage. SOLUTION: A gate conductor layer is embedded in a groove provided in a semiconductor substrate via an insulating film, and a high-concentration first semiconductor region, a low-concentration first semiconductor region, a second semiconductor region, and a third semiconductor region are sequentially formed. In the semiconductor device having the formed vertical transistor, an impurity concentration in a portion near the side wall of the gate conductor layer in the low-concentration first semiconductor region is higher than an impurity concentration in another portion of the low-concentration first semiconductor region. I do. Further, a conductor layer was buried in a groove provided in the semiconductor substrate via an insulating film, and a high-concentration first semiconductor region, a low-concentration first semiconductor region, a second semiconductor region, and a third semiconductor region were sequentially formed. The impurity concentration in the vicinity of the side wall of the gate conductor layer in the second region of the semiconductor device having a vertical transistor,
The impurity concentration is set lower than the impurity concentration in the other portion of the second region.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to a technique effectively applied to a semiconductor device having a trench gate structure.

[0002]

2. Description of the Related Art Power transistors are used in power amplifier circuits, power supply circuits, converters, power supply protection circuits, etc. However, since these power transistors handle a large amount of electric power, they are required to have a high breakdown voltage and a large current. Required. MISFE
T (Metal Insulator Semiconductor Field Effect Tra
In the case of (nsistor), it is dealt with by increasing the channel width as a method of achieving a large current.

A mesh gate structure, for example, is used in order to prevent the chip area from increasing due to such an increase in channel width. In the mesh gate structure, the gates are arranged in a grid in a plan view to increase the channel width per unit chip area.

Conventionally, such a power FET has a planar structure because of its simple process and easy formation of an oxide film to be a gate insulating film. However, in the planar FET, when the cell size is reduced to reduce the resistance, the depletion layers of adjacent cells collide with each other,
The current stops flowing. For this reason, the resistance does not decrease even if miniaturization is attempted. This is called the JFET effect, and therefore there is a limit to the reduction in resistance due to miniaturization in the planar FET.

For this reason, a trench gate structure FET having no JFET effect has been considered for the reasons that the degree of cell integration can be further improved and the on-resistance can be reduced. What is a trench gate structure?
A conductor layer serving as a gate is provided in a groove extending in the main surface of the semiconductor substrate via an insulating film, a deep layer portion of the main surface of the semiconductor substrate is a drain region, a surface layer portion of the main surface is a source region, and the drain region is The semiconductor layer between the source region and the source region serves as a channel formation region. This type of trench gate structure MISFET is disclosed in, for example, Japanese Patent Application Laid-Open No. 8-23092.

[0006]

In such a power transistor, there is a constant demand for reduction in on-resistance, and particularly for products with low breakdown voltage, there is a demand for low on-resistance. Up to now, in the FET of the trench gate structure, the on-resistance has been reduced by the cell shrink for reducing the unit cell area. However, such reduction of the on-resistance reduces the on-resistance of the epitaxial layer forming the main surface of the semiconductor substrate with respect to the overall on-resistance. The proportion of resistance is increasing.
Therefore, methods such as lowering the resistivity of the epitaxial layer in which the drain region or the channel region is formed or reducing the thickness of the epitaxial layer have been adopted. There is a limit to conversion.

An object of the present invention is to provide a technique capable of solving these problems, further reducing the on-resistance of the vertical FET, and improving the avalanche withstand capability. The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

[0008]

Among the inventions disclosed in the present application, a brief description will be given to the outline of typical ones.
It is as follows. A gate conductor layer is embedded in a groove provided in a semiconductor substrate via an insulating film, and a high-concentration first semiconductor region, a low-concentration first semiconductor region, a second semiconductor region, and a third semiconductor region are sequentially formed in a vertical direction. Type semiconductor device having a low-concentration first semiconductor region, wherein an impurity concentration in a portion of the low-concentration first semiconductor region near a side wall of the gate conductor layer is higher than an impurity concentration in another portion of the low-concentration first semiconductor region. .

Further, a conductor layer is embedded in a groove provided in the semiconductor substrate via an insulating film, and a high-concentration first semiconductor region, a low-concentration first semiconductor region, a second semiconductor region, and a third semiconductor region are sequentially formed. A semiconductor device having a formed vertical transistor, wherein the impurity concentration of a portion of the second region near the side wall of the gate conductor layer is lower than the impurity concentration of another portion of the second region described above. According to the present invention, the impurity concentration of the portion near the side wall of the gate conductor layer in the low-concentration first semiconductor region is made higher than the impurity concentration of other portions of the low-concentration first semiconductor region, so that the low on-resistance is low. Can be realized. In addition, the tip of the depletion layer is located on the side wall of the trench during avalanche breakdown, and electric field concentration at the bottom of the trench is suppressed, so that the avalanche withstand capability is improved.

By making the impurity concentration of the second semiconductor region lower than that of the low-concentration first semiconductor region, the depletion layer that limits the breakdown voltage is closer to the second semiconductor region than the low-concentration first semiconductor region. Since it spreads, the breakdown voltage is improved.

Embodiments of the present invention will be described below. In all the drawings for explaining the embodiments, the same reference numerals are given to those having the same function, and the repeated description thereof will be omitted.

[0012]

1 and 2 are partial vertical cross-sectional views showing the structure of a unit cell of a vertical power MISFET used in a semiconductor device of this embodiment. This vertical power MISFET is formed on an n + type semiconductor substrate 1 made of single crystal silicon, for example, on a semiconductor substrate having an epitaxial layer 2 formed by epitaxial growth. This MISFET is a cell having a trench gate structure in which a planar shape is a stripe shape, a rectangular shape, or a polygonal shape in a cell forming region surrounded by a field insulating film provided in a rectangular ring shape along the outer periphery of a semiconductor substrate. Are regularly arranged and each gate is arranged in a plane in a stripe shape or a lattice shape, and each cell is connected in parallel to form a stripe or mesh gate structure.

In each cell of the present embodiment, the first semiconductor region is the drain region, the second semiconductor region is the channel region, and the third semiconductor region is the source region, and the n + type semiconductor is a high-concentration drain region. A vertical FET in which an n-type low-concentration drain region 2a is formed on the substrate 1, a p-type channel region 2b is formed on the low-concentration drain region 2a, and an n + type source region 2c is formed on the channel region 2b. ing.

The gate conductor layer 3 is formed via a gate insulating film 4 in a groove extending from the main surface of the semiconductor substrate to the low concentration drain region 2a. The gate conductor layer 3 is made of, for example, polycrystalline silicon doped with impurities, and the gate insulating film 4 is made of, for example, a silicon oxide multilayer film in which a thermal oxide film and a deposited film are sequentially formed.

The upper surface of the gate conductor layer 3 of the present embodiment is covered with the cap insulating film 5, and the source region 2c of the exposed portion of the main surface of the semiconductor substrate defined by the cap insulating film 5 is made of, for example, silicon. The source electrode 6 using the contained aluminum is electrically connected.
The gate conductor layer 3 is connected to the gate electrode in the same layer as the source electrode 6 in the peripheral portion of the semiconductor substrate.

On the entire main surface of the semiconductor substrate, for example, a protective insulating film 7 using a silicon oxide film and polyimide is formed by a plasma CVD method using tetraethoxysilane (TEOS) gas as a main source gas, and this protection is performed. Insulation film 7
An opening for partially exposing the gate electrode and the source electrode 6 connected to the gate conductor layer 3 is provided, and this opening serves as a connection region for the gate and the source, and an electrical connection is made to this connection region by wire bonding or the like. Done.

As the drain connection region, a drain electrode 8 electrically connected to the n + type semiconductor substrate 1 is formed on the entire back surface of the semiconductor substrate, for example, a metal film in which nickel, titanium, nickel and silver are sequentially laminated, or titanium, nickel. And gold are sequentially laminated to form a metal film, and the surface of the drain electrode 8 made of silver or gold is connected to a lead frame by, for example, a conductive adhesive to make an electrical connection.

In the structure of the vertical transistor of this embodiment shown in FIG. 1, the impurity concentration is present in the low concentration drain region 2a in the vicinity of the sidewall adjacent to the sidewall of the trench gate conductor layer 3 through the gate insulating film 4. A high-concentration layer 10a higher than the other portions of the low-concentration drain region 2a is formed. The high-concentration layer 10a can reduce the resistance of the low-concentration drain region 2a when the FET is on. Also,
The high-concentration layer 10a makes it difficult for the depletion layer at the time of avalanche breakdown to extend on the sidewall of the trench gate conductor layer 3 as shown by the broken line.

Since the electric field is concentrated at the corners of the lower surface of the trench gate, conventionally, since the depletion layer extends, this portion often becomes a breakdown point at the time of avalanche breakdown, so that the breakdown voltage is ensured. The thickness of the low-concentration drain region 2a under the trench gate conductor layer 3 is secured to reduce the concentration of electric field.

However, in this embodiment, since the tip of the depletion layer is located not at the corner of the lower surface of the trench gate conductor layer 3 but at the side wall of the trench gate, the electric field is concentrated on the corner of the lower surface of the trench gate conductor layer 3. Since this can be suppressed, this portion is less likely to become a breakdown point, and the avalanche withstand capability is improved. As a result, it is possible to reduce the thickness of the low-concentration drain region 2a below the trench gate conductor layer 3, and thereby reduce the resistance of the low-concentration drain region 2a.

In addition, since the breakdown point occurs at a place other than the corner of the lower surface of the trench gate conductor layer 3, specifically, immediately below the portion connected to the source electrode 6,
The parasitic bipolar transistor becomes difficult to operate, and the avalanche withstand capability increases.

In the structure shown in FIG. 2, the impurity concentration in the channel region 2b in the vicinity of the sidewall adjacent to the sidewall of the trench gate conductor layer 3 via the gate insulating film 4 is higher than that in the other portions of the channel region 2b. A low low concentration layer 10b is formed. The low-concentration layer 10b can increase the transfer conductance. The increased transfer conductance facilitates low threshold voltage control during low voltage drive with a narrow allowable operating voltage range. FIG. 3 shows a configuration in which the above-described configurations are integrated together.

Further, in the present embodiment, as shown in FIG. 4 as an impurity concentration profile, the channel region has an impurity profile having a plurality of peaks, whereby the concentration profile of the channel region is flattened and the transfer conductance is further reduced. A high element can be obtained.

Next, a method of manufacturing the above-mentioned semiconductor device will be described with reference to FIGS. First, an n-type epitaxial layer 2 having a lower concentration than that of the semiconductor substrate 1 is epitaxially grown on the n + type semiconductor substrate 1 made of single crystal silicon in which arsenic (As) is introduced to a thickness of 5 μm.
Insulating film 11 deposited on the main surface of the semiconductor substrate having a thickness of about m
Then, a pattern of the gate conductor layer 4 is opened by photolithography, and a groove having a depth of, for example, about 1.6 μm is formed as a trench of the gate conductor layer 4 on the main surface of the semiconductor substrate by dry etching using the insulating film 11 as a mask. Form.

In this state, in order to form the high-concentration layer 10a of the low-concentration drain region 2a and the low-concentration layer 10b of the channel region 2b in the vicinity of the trench gate trench, impurities are added to the trench gate trench thus formed. Inject. In this implantation, as shown by a broken line in FIG. 5, n-type impurities such as phosphorus or arsenic are introduced by step ion implantation in which ions are obliquely implanted into the wafer in four directions, and a portion near a sidewall is introduced. Then, the impurity layer 10 is formed.

Although the impurity layer 10 has a single impurity concentration by collective ion implantation, the high concentration layer 10a
In order to introduce the impurities for forming the low concentration layer 10b, ion implantation is selectively performed between the high concentration layer 10a and the low concentration layer 10b by a method such as forming a mask on the side wall surface, and the respective impurity concentrations are changed. It may be optimized.

After that, a gate insulating film 4 is formed, and a polycrystalline silicon film serving as a conductive film of the gate conductor layer 3 is formed by CVD on the entire main surface of the semiconductor substrate including the inside of the groove, and this polycrystalline silicon film is formed. Etch back to form the gate conductor layer 3 in the groove.
To form.

Subsequently, p-type impurities (for example, boron) are ion-implanted on the entire surface of the epitaxial layer 2 and a thermal diffusion process is performed to form a channel region 2b. By this ion implantation, the n-type impurity layer 10 near the side wall of the channel region 2b is canceled by the implanted p-type impurity, and the channel region 2b near the side wall of the impurity layer 10 has a lower concentration p-type than other portions. It becomes the channel region low-concentration layer 10b and is separated from the impurity layer 10 of the low-concentration drain region 2a which is the low-concentration drain region 2a and the high-concentration drain region 2a.

Further, an n-type impurity (for example, arsenic) is selectively ion-implanted and an annealing process is performed to form a source region 2c. It should be noted that in the source region 2c, the n-type impurity implanted into the side wall of the source region 2c has almost no influence because the source region 2c has a much higher concentration of n-type. And
Epitaxial layer 2 in which these impurities are not introduced
The deep layer, specifically, the epitaxial layer 2 located between the channel region 2b and the semiconductor substrate 1 becomes the low-concentration drain region 2a. This state is shown in FIG.

After that, the silicon oxide film deposited on the entire surface is patterned to form a cap insulating film 5 covering the gate conductor layer 3, and a contact hole is formed by etching using a resist mask having a predetermined pattern. A conductive film made of a metal such as aluminum containing silicon is formed on the entire main surface of the semiconductor substrate including the inside of the hole, and the metal film is patterned to form the gate electrode and the source electrode 6. Plasma C using tetraethoxysilane (TEOS) gas as the main constituent of
Polyimide is applied and laminated on a silicon oxide film formed by VD to form a protective insulating film 7 covering the entire main surface of the semiconductor substrate, and openings are formed in the protective insulating film 7 to expose the connection regions of the gate electrode and the source electrode 6. To do. A drain electrode 8 is formed on the back surface of the n + type semiconductor substrate 1 by, for example, vapor deposition,
The state shown in FIG. 3 is obtained.

In the power transistor of this embodiment,
Since the on-resistance is low and the aparanche resistance is high, VRM (Voltage Reg) used in personal computers etc.
It is effective when used as an emulator module). In a personal computer, the operating voltage of an arithmetic unit (CPU) for processing data is 2 for high-speed processing and low power consumption.
In many cases, the operating voltage is changed to V or lower depending on the situation. Therefore, the prepared power supply voltage of 5V
Alternatively, VRM is used to stably supply an operating voltage that is 3.3V down.

In such a VRM, as shown in FIG.
The control chip turns on and off the two power FETs alternately, and inputs 5V or 3.3V from the terminal Vin.
Is converted to a predetermined operating voltage of 2 V or less, smoothed by the choke coil L and the capacitor C, and then the terminal Vout
Supply to the CPU.

The power transistor of this embodiment is also effective when used in a protection circuit for a lithium ion battery used in a mobile phone.

As described above, the inventions made by the present inventor are
Although the specific description has been given based on the above-described embodiment, the present invention is not limited to the above-described embodiment, and it goes without saying that various modifications can be made without departing from the scope of the invention. For example, in the above description, the n-type power M
Although the ISFET has been described, the present invention can also be applied to a p-type power MISFET, and the power M
Besides ISFET, IGBT (Integrated Gate Bipo
lar Transistor) is also applicable.

[0035]

The effects obtained by the typical ones of the inventions disclosed in the present application will be briefly described as follows. (1) According to the present invention, the impurity concentration in the portion near the side wall of the gate conductor layer in the low-concentration drain region is made higher than the impurity concentration in other portions, so that the low on-resistance can be achieved. There is an effect. (2) According to the present invention, the impurity concentration in the portion near the side wall of the gate conductor layer in the low-concentration drain region is made higher than the impurity concentration in other portions, so that the depletion layer of the avalanche breakdown is formed. Since the tip is located on the side wall of the trench and the electric field concentration at the bottom of the trench is suppressed, the breakdown voltage can be improved. (3) According to the present invention, by making the impurity concentration of the channel layer lower than that of the drain layer, the depletion layer that limits the breakdown voltage expands to the channel region side rather than the drain region, so the breakdown voltage improves. There is an effect.

[Brief description of drawings]

FIG. 1 is a vertical sectional view showing a semiconductor device according to an embodiment of the present invention.

FIG. 2 is a vertical cross-sectional view showing a semiconductor device according to an embodiment of the present invention.

FIG. 3 is a vertical sectional view showing a semiconductor device according to an embodiment of the present invention.

4 is a graph showing an impurity concentration profile of the semiconductor device shown in FIG.

FIG. 5 is a vertical cross-sectional view showing the manufacturing process of the semiconductor device according to the embodiment of the present invention.

FIG. 6 is a vertical cross-sectional view showing the manufacturing process of the semiconductor device according to the embodiment of the present invention.

FIG. 7 is an equivalent circuit diagram of a VRM using the semiconductor device according to the embodiment of the present invention.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Semiconductor substrate, 2 ... Epitaxial layer, 2a ... Low concentration drain region, 2b ... Channel region, 2c ... Source region, 3 ... Gate conductor layer, 4 ... Gate insulating film, 5 ... Cap insulating film, 6 ... Source electrode, 7 ... Protective insulating film, 8 ... Drain electrode, 10 ... Impurity layer, 10a ... High concentration layer, 10b
... Low concentration layer, 11 ... Insulating film.

Claims (4)

[Claims] 1. A high-concentration first semiconductor region, a low-concentration first semiconductor region, a second semiconductor region, and a third semiconductor region are formed by embedding a gate conductor layer in a groove provided in a semiconductor substrate via an insulating film. A semiconductor device having vertical transistors sequentially formed, wherein an impurity concentration in a portion of the low-concentration first semiconductor region near the sidewall of the gate conductor layer is set to an impurity concentration in another portion of the low-concentration first semiconductor region. A semiconductor device characterized in that the concentration is higher than the concentration. 2. A conductor layer is embedded in a groove provided in a semiconductor substrate via an insulating film, and a high-concentration first semiconductor region, a low-concentration first semiconductor region, a second semiconductor region, and a third semiconductor region are sequentially formed. A semiconductor device having a formed vertical transistor, wherein an impurity concentration in a portion near the sidewall of the gate conductor layer in the second region is set to be lower than an impurity concentration in another portion of the second region. Characteristic semiconductor device. 3. The semiconductor device according to claim 1, wherein the second semiconductor region has an impurity profile having a plurality of peaks. 4. The first semiconductor region is a drain region, the second semiconductor region is a channel region, and the third semiconductor region is a source region. The semiconductor device according to claim 1.