JP2002118224A - Multi-chip module - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a multichip module having excellent reliability to thermal stress or the like. SOLUTION: In this multichip module, at least two or more semiconductor chips have the chip electrode of the semiconductor chip, conductive wiring electrically connected to the chip electrode, a conductive land electrically connected to the wiring, an external terminal placed in the land, and a stress relief layer included between the land and semiconductor chip, and are placed on the packaging substrate via the external terminal. The stress relief layer of a first semiconductor chip having the stress relief layer has thickness that is equal to that of the stress relief layer of a second semiconductor chip where distance from the external terminal positioned at an endmost section and the center of the semiconductor chip is smaller than that of the first semiconductor chip or more.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a multi-chip module in which a plurality of semiconductor chips are mounted on a mounting board.

[0002]

2. Description of the Related Art In recent years, with the rapid spread of mobile phones, notebook computers, PDAs (Personal Digital Assistance), etc., these consumer electronic systems have been rapidly reduced in size, weight, and function. In order to realize this, it is necessary to have a technology in which semiconductor devices such as a CPU, a microcomputer, a logic, a memory, and the like and passive electronic components are densely mounted and assembled as a system module.

The ultimate form is a system-on-a-chip in which all devices are built in one chip, but there is a possibility that the yield may be reduced due to the difficulty in manufacturing different devices at the same time. Such a system module is custom-made for each product, and it is easy to produce a small amount in a different configuration, and there is a problem that if such a product is redesigned from the device stage, it is not worth the cost. Therefore, an MCM that mounts multiple chips made separately at a high density with the shortest possible wiring length and assembles them into one system module
(Multi-chip module) technology development is active.

As an example of a conventional MCM, see Japanese Patent Application Laid-Open No. 10-1
No. 26044, an MCM having a structure in which a plurality of semiconductor chips are flip-chip mounted on a base substrate via solder, and a sealing resin is poured between the semiconductor element and the base substrate.
There is a description.

In Japanese Patent Application Laid-Open No. 2000-196008, three or more semiconductor chips are arranged in a plane on a substrate, electrically connected by thin wires, and the whole of the semiconductor chip and the thin wires are sealed with a sealing resin. There is a description of a multi-chip type semiconductor device in which a ball grid array serving as an external electrode is formed on a back surface of a substrate.

[0006]

SUMMARY OF THE INVENTION However, Japanese Patent Laid-Open No.
0-126044, JP-A-2000-196008
None of the above publications describes improving the reliability of the entire multi-chip module against thermal stress and the like.

Therefore, an object of the present invention is to provide a multi-chip module having high reliability against thermal stress and the like.

[0008]

In order to overcome the above-mentioned problems, a multichip module according to the present invention is configured as follows.

According to a first aspect of the present invention, there is provided a multi-chip module in which a plurality of semiconductor chips each having a semiconductor element are mounted on a mounting substrate, wherein at least two or more of the semiconductor chips include a chip electrode of the semiconductor chip, A conductive wiring electrically connected to the electrode; a conductive land electrically connected to the wiring; an external terminal provided on the land; and a stress interposed between the land and the semiconductor chip. A stress relaxation layer of a first semiconductor chip having a stress relaxation layer, being disposed on the mounting substrate via the external terminal, and having the stress relaxation layer, has the stress relaxation layer and is located at an end portion. The distance between the external terminal and the center of the semiconductor chip is thicker than the stress relaxation layer of the second semiconductor chip smaller than the first semiconductor chip.

In order to improve the reliability of the multichip module of the present invention, if the reliability of the semiconductor chip having a plurality of stress relaxation layers mounted thereon is to be adjusted accordingly, the chip having the longer outermost terminal distance has a higher stress. Strain absorption by the relaxation layer must be greater. In the stress relaxation layer, the smaller the elastic modulus of the material and the thicker the thickness, the higher the ability to absorb the strain. Assuming that the same material is used for the stress relaxation layer, the difference in reliability of the external terminals can be reduced by increasing the thickness of the stress relaxation layer as the outermost terminal distance increases.

A semiconductor chip having a plurality of stress relaxation layers mounted on a mounting board is a small chip-sized package in which external terminals are arranged in a range close to or in the plane of the semiconductor chip. When a temperature change is applied to the board while the board is mounted, the strain due to the difference in thermal expansion between the semiconductor chip and the mounting board tends to concentrate on the external terminals sandwiched between them, but the stress relief layer interposed between the external terminals and the semiconductor chip This deformation can absorb this strain and improve the life of the external terminal in a temperature cycle. Even when the underfill reinforcement used in the conventional multi-chip module using bare chip mounting is not performed, the reliability of the external terminals can be improved, so that the underfill process during mounting can be omitted and the low Cost. Also,
Repair after mounting becomes possible. In this case, it is preferable to have a space around the external terminal from the viewpoint of effective cooling. Also, wiring on the semiconductor chip,
Since the external terminals are arranged at a wide pitch with respect to the chip electrode pitch of the chip, mounting on the board is easy,
It does not require a high-density mounting board. Further, since the stress relaxation layer absorbs the displacement difference due to thermal expansion, the stress generated in the chip can be reduced. Also, chip cracks can be suppressed. Thus, a highly reliable MCM can be obtained at low cost. An MCM that can be easily mounted on a substrate and can suppress chip cracks can be obtained.

At least two or more of the semiconductor chips include a chip electrode of the semiconductor chip, a conductive wiring electrically connected to the chip electrode, and a conductive land electrically connected to the wiring. An external terminal installed on the land, a stress relaxation layer interposed between the land and the semiconductor chip, installed on the mounting board via the external terminal, and around the external terminal A space is provided, and the distance between the end of the first semiconductor chip having the stress relieving layer and the end of the second semiconductor chip having the stress relieving layer disposed adjacent to the first semiconductor chip is increased. 1
It is preferable to form a multi-chip module smaller than mm.

In underfill mounting, the underfill is formed so as to extend outward from the end of the semiconductor chip toward the surface of the mounting substrate (underfill fillet). Also, in order to allow the nozzle for injecting the underfill to pass through, the interval between the semiconductor chips mounted adjacently needs to be about 1 to 2 mm. On the other hand, when the underfill is omitted in the semiconductor device having the stress relaxation layer of the multi-chip module of the present invention, the semiconductor device can be formed in the same size as the semiconductor chip. Is possible. At this time, effective cooling can be performed even if the components are mounted at a high density. For example, it is conceivable that the distance between adjacent semiconductor chips is less than 1 mm and, for example, about 0.5 mm or less in order to further increase the mounting density. Further, both chip ends can be made narrow enough not to make contact.

According to a second aspect of the present invention, there is provided a multi-chip module including a semiconductor chip having a plurality of the stress relaxing layers, wherein the stress relaxing layer of the first semiconductor chip having the stress relaxing layer includes the stress relaxing layer. And wherein the projected area of the outermost terminal located at the end is thicker than the stress relaxation layer of the second semiconductor chip which is larger than the first semiconductor chip.

The life of the external terminal varies depending on the size of the external terminal. The larger the size of the external terminal, the greater the absorption of strain by the external terminal itself, and thus the higher the reliability of the external terminal. Therefore, when the pitch or the like for arranging the external terminals is small and the size of the external terminals is small, the thickness of the stress relaxation layer is increased as described above to correct the difference in the overall stress absorbing power, and as a whole, Can be improved in reliability.

However, when the cost reduction merit by unifying the process is great, the stress relaxation layer having such a thickness that the reliability can be ensured in the semiconductor device with the stress relaxation layer having the longest outermost terminal distance is replaced by another stress relaxation layer. It may be formed also in a semiconductor device with a layer.

[0017] In the multi-chip module, at least one of the semiconductor devices having the stress relieving layer includes the wiring, the land, the external terminal, and an end of the stress relieving layer, It is preferable to be formed inside the end of the semiconductor chip. In this case, for example, it is preferable to use a thin film wiring as the wiring.

Conventionally, Si has been mainly used as a material for a semiconductor chip, but in recent years, for example, compound semiconductors such as GaAs and InP have been used for high-speed signal processing and optical signal processing in communication systems. Since such a compound semiconductor is generally brittle compared to Si, the problem of the chip crack described above becomes remarkable. In the multi-chip module of the present invention, by applying the semiconductor device with the stress relaxation layer to the above-described compound semiconductor semiconductor chip, the stress applied to the semiconductor chip can be reduced and chip cracks can be prevented.

[0019]

The present invention can be applied to a multichip module having a function of operating as a system by mounting a plurality of semiconductor devices and passive electronic components on a substrate at high density. Examples of the semiconductor device mounted on the mounting board include a CPU, a microcomputer, a logic, and a memory (DRAM, SRAM, Flash, etc.).
h) or a chip dedicated to image processing, a dedicated chip in which an interface or the like is integrated into one chip, and the like. Passive components, such as chip capacitors and resistors, are incorporated mainly for circuit stabilization, such as noise reduction, and may be incorporated inside a mounting board.

FIG. 1 is a plan view showing a first embodiment of the present invention, and FIG. 2 is a sectional view showing the first embodiment. As shown in FIG. 1, in the first embodiment of the present invention, two semiconductor devices, a first semiconductor chip 10 and a second semiconductor chip 20, and four passive components 4 are mounted on a mounting substrate 1. This is an example of a basic configuration that has been performed.

FIG. 2 is a cross-sectional view (section AA in FIG. 1) including the first semiconductor chip 10 and the second semiconductor chip 20 according to one embodiment of the present invention. As shown in FIG. 2, on the surface of the first semiconductor chip 10, a chip electrode 11, a conductive wiring 12 drawn from the chip electrode 11, and a conductive land 1 connected thereto are provided.
3, a stress relaxation layer 14 interposed at least between the semiconductor chip 10 and the land 13, and an external terminal 15 bonded to the land 13. The first semiconductor device with a stress relaxation layer 2 is mounted on the mounting board 1 via the external terminals 15. Similarly, the second semiconductor chip 20 also has a chip electrode 21, a conductive wiring 22, a conductive land 23, a stress relaxation layer 24, and an external terminal 25. The semiconductor device 3 with the second stress relaxation layer is mounted on the mounting substrate 1 via the external terminals 25.

The external terminals 15 and 25 are made of, for example, a solder material (Pb-Sn eutectic, Sn-Ag-Cu, Sn-
Ag-Cu-Bi system) is used, and is formed in a ball shape.

In the multichip module of the present invention, the first semiconductor chip 10 and the second semiconductor chip 20
In both cases, the stress relaxation layer 14 or 2
4, the strain caused by the difference in thermal expansion between the semiconductor chip and the mounting board is absorbed by the deformation of the stress relaxation layer, and the strain generated in the solder bumps as the external terminals is reduced. Improves life cycle.

When a semiconductor chip is mounted on a substrate via a bare chip, that is, an external terminal formed directly on a chip electrode, the external terminal quickly fatigues due to the above-described distortion due to a difference in thermal expansion between the semiconductor chip and the mounting substrate. Therefore, a resin called an underfill is injected between the semiconductor chip and the mounting substrate to reinforce the periphery of the external terminal, thereby ensuring the reliability of the external terminal. However, the underfill has problems such as a high material cost, a long time in the implantation step, and the need for reliable injection method know-how that does not generate voids.

In the multichip module of the present invention, the reliability of the external terminals can be ensured by the deformation of the stress relaxation layer. In addition, when the reinforcement by the underfill resin is omitted, the cost can be further reduced. It is also conceivable to increase the cooling effect. Because it is mounted with solder bumps,
It can be easily removed by melting the solder by heat. For this reason, replacement of a defective chip is easier than underfilling.

In the conventional bare chip mounting,
Since the board is mounted by external terminals formed on chip electrodes arranged at a narrow pitch (generally less than 100 μm),
It is required that the positioning accuracy at the time of mounting the substrate is considerably high. On the other hand, the semiconductor device with a stress relaxation layer of the present invention is:
Since the pitch is increased by the wiring routed from the chip electrode, it is possible to eliminate the need for high alignment accuracy.

As described above, in the multi-chip module of the present invention, the pitch of the external terminals is larger than that of the conventional multi-chip module using bare chips, and there is no need for underfill. It is characterized in that the chip can be easily mounted on a mounting board and repair after mounting is possible. Further, in order to increase the pitch of the external terminals, the pitch of the lands for bonding the external terminals can be increased on the mounting substrate side, so that an inexpensive substrate can be used.

The semiconductor chip to be mounted is mainly made of Si as a main material. For example, a chip for processing a high-frequency signal for communication, which is used in a mobile phone or the like, is used. In some cases, a compound semiconductor such as GaAs or InP is used. A strain caused by a difference in thermal expansion between the semiconductor chip and the mounting substrate is absorbed, and a large stress is generated in the semiconductor chip, thereby suppressing a load on the semiconductor chip. In the semiconductor device with the stress relaxation layer according to the present invention, the thermal strain can be absorbed by both the external terminal and the stress relaxation layer, so that the stress generated in the semiconductor chip can be extremely reduced. Therefore, it is desirable to assemble a semiconductor chip using a material brittler than Si as described above into a semiconductor device with a stress relaxation layer and mount it on a mounting substrate.

In underfill mounting, the underfill is formed so as to extend outward from the end of the semiconductor chip toward the surface of the mounting substrate (underfill fillet). Also, in order to allow the nozzle for injecting the underfill to pass through, the interval between the semiconductor chips mounted adjacently needs to be about 1 to 2 mm. On the other hand, the semiconductor device with a stress relaxation layer of the multi-chip module of the present invention,
The semiconductor chip can be formed in the same size as the semiconductor chip, and a plurality of semiconductor chips can be mounted at a higher density by omitting underfill mounting. For example, the distance between the end portions of adjacent semiconductor chips with a stress relaxation layer can be set to less than 1 mm, for example, 0.5 mm or less.

The above-mentioned stress relaxation layer has a smaller elastic modulus and a larger thickness, so that the ability to absorb strain is higher and the reliability of the external terminal can be improved.

In order to satisfy the reliability level required for the multi-chip module, it is necessary to increase the reliability of the external terminals in all the mounted semiconductor devices. On the other hand,
The required specifications of the stress relaxation layer to satisfy this reliability level are not the same.

Assuming that a semiconductor device with a stress relaxation layer having a stress relaxation layer of the same material and thickness is applied to a plurality of different semiconductor chips, the semiconductor device having the plurality of stress relaxation layers has an external terminal. Life is different. This is because the difference in displacement due to thermal expansion between the semiconductor chip and the mounting board increases as the distance from the center of the semiconductor chip increases, so that a larger distortion may occur at an external terminal located farther from the center of the semiconductor chip. . Therefore, the larger the distance between the outermost external terminal and the center of the semiconductor chip (hereinafter, referred to as the outermost terminal distance), the greater the possibility that extra distortion occurs in the external terminal.

Therefore, in order to improve the reliability of the present multi-chip module, the first semiconductor device 2 with a stress relaxation layer
Assuming that the outermost terminal distance is larger than that of the second semiconductor device 3 with a stress relaxation layer, the first semiconductor device with a stress relaxation layer is required to make the reliability of both external terminals equal. No. 2 increases the absorption of strain by the stress relaxation layer. If the same material is used for the stress relaxation layer, the capacity of the strain absorption can be increased by increasing the thickness of the stress relaxation layer. The thickness 14a of the layer 14 is made larger than the thickness 24a of the stress relaxation layer 24 in the semiconductor device 3 with the second stress relaxation layer. In addition, instead of the distance between the outermost terminals, the distance between the outermost terminals is compared, and the thickness of the stress relaxation layer of the larger chip is made larger than the thickness of the smaller stress relaxation layer.

The life of the external terminal also changes depending on the size of the external terminal. The larger the size of the external terminal, the greater the absorption of strain by the external terminal itself, and thus the higher the reliability of the external terminal. Therefore, when the arrangement pitch of the external terminals of the second semiconductor device 3 with the stress relaxation layer is small and the external terminal size is smaller than the semiconductor device 2 with the first stress relaxation layer, the second terminal is smaller than the first semiconductor device 2. The thickness of the stress relaxation layer of the semiconductor device 3 is increased.

The diameter of the land (for example, the land diameter of the outermost terminal) is compared with the external terminal size, and the thickness of the stress relaxation layer of the semiconductor device having the smaller diameter is larger than that of the semiconductor device having the larger diameter. Increase the thickness.

Also, as an example, even when the semiconductor device 3 with the second stress relaxation layer has a smaller outermost terminal distance, the pitch at which the external terminals are arranged is small, and the size of the external terminals must be reduced. In this case, the reliability may not be obtained unless the thickness of the stress relaxation layer is larger than that of the first semiconductor device 2 with a stress relaxation layer having a longer outermost terminal distance. In such a case, the size of the external terminal is small.
It is conceivable to increase the thickness of the stress relaxation layer in the semiconductor device 3 having the stress relaxation layer.

As the thickness of the stress relaxation layer is increased, the reliability of the external terminal is improved. On the other hand, as the stress relaxation layer is increased, the material cost of the stress relaxation layer is increased. Further, when a wiring connecting the chip electrode and the land on the stress relieving layer is formed by a thin film wiring process, if the stress relieving layer becomes thicker, it becomes difficult to expose and develop the photoresist. Therefore, the thickness of the stress relaxation layer is adjusted to an extent that a required reliability level can be ensured in the two semiconductor devices with the stress relaxation layer, and the thickness is not increased further.

When there is a great merit of cost reduction by unifying the processes, both stress relaxation layers may be formed to have the same thickness.

Further, even in a semiconductor device having a stress relaxation layer having a small number of external terminals, for example, when a formation process (for example, connection by leads or wires) is used in which wiring formation is not so difficult even when the stress relaxation layer is thick. It is easy to form a stress relaxation layer.

Therefore, depending on the conditions, a stress relaxation layer thicker than a semiconductor device with a stress relaxation layer having a large number of external terminals can be formed.

Examples of the material of the stress relaxation layer include a polyimide resin, a polyetherimide resin, a polyimideamide resin, an acryl-modified epoxy resin, an epoxy resin containing rubber, and a silicone resin, and have an effect of absorbing strain. Therefore, the longitudinal elastic modulus at room temperature is 2
It is desirable to have low elasticity of about 000 MPa or less.
At this time, it is desirable to secure elasticity of about 100 MPa or more. Practically, 500 to 1000 MPa
A range of degrees can be used.

In the configuration of the semiconductor device with a stress relaxation layer shown in the sectional view of FIG. 2, only members necessary for explaining the main effects of the present invention are described, and detailed configurations are omitted. I have. FIG. 3 is a plan view showing an example of a detailed configuration of the first semiconductor device 2 with a stress relaxation layer according to the first embodiment.
FIG. 4 shows a cross-sectional view. FIG. 3 shows a state in which the external terminals and a part of the surface protective film have been removed so that the internal structure can be seen.

As shown in FIG. 3, the first semiconductor chip 1
Reference numeral 0 indicates that the chip electrodes 11 are arranged on the four sides of the chip periphery and are drawn out to the center by the wiring 12, and the lands 13 to which the external terminals 15 are joined have a larger pitch than the chip electrodes 11. They are arranged. For example, when the number of external terminals is as large as several hundred as in a microcomputer, the chip electrodes are often arranged in a peripheral part rather than a central part. FIG. 4 shows a sectional view. The stress relieving layer 14 absorbs thermal strain by being interposed at least between the land 13 and the first semiconductor chip 10, thereby improving the reliability of the external terminal.

Hereinafter, members omitted in FIG. 2 will be described. The passivation film 16 is a very thin film formed to cover the surface of the semiconductor chip 10 on which the chip electrodes 11 are formed, and can be formed in a wafer process to protect the surface of the semiconductor chip.

The passivation film 16 and the stress relaxation layer 14
The insulating film 17 may be formed so as to be interposed between them. In the semiconductor device 2 with the present stress relaxation layer, the thick stress relaxation layer 14 is provided between the wiring 12 and the internal wiring of the semiconductor chip 10.
, The capacitance between them can be reduced, and malfunction due to crosstalk noise is unlikely to occur. However, since the wiring 12 is formed directly on the thin passivation film 16 around the chip electrode 11, when high-speed operation is required, the capacitance of this portion may be a problem. The insulating film 17 is formed around the chip electrode 11 by the wiring 12 and the semiconductor chip 10.
, The capacitance at this portion can be greatly reduced.

On the outermost surface of the semiconductor device 2 having the stress relaxation layer, a surface protective film 1 is provided mainly for the purpose of protecting the wiring.
8 is formed. An opening is formed on the land 13 on the surface protection film 18, and the land 13 and the external terminal 15 are joined.

As shown in FIG. 2, the distance from the center of the semiconductor chip 10 in plan view to the external terminal at the farthest position is the above-described outermost terminal distance 19.

FIG. 5 is a plan view showing an example of a detailed configuration of the second semiconductor device 3 with a stress relaxation layer according to the first embodiment.
FIG. 6 shows a cross-sectional view. FIG. 5 shows a state in which the external terminals and a part of the surface protective film have been removed so that the internal structure can be seen.

The basic structure is the same as that of the first semiconductor device 2 with a stress relaxation layer, except that the chip electrodes 21 are arranged at the center of the semiconductor chip 20. When the number of external terminals is relatively small, such as several tens, such as in a memory product, the chip electrodes may be arranged in the center as in this example. As shown in FIG. 5, the external terminal 2 is drawn out from the central chip electrode 21 to the periphery by the wiring 22.
The lands 23 to which 5 is joined are arranged with a larger pitch than the chip electrodes 21. The members omitted in FIG. 2 are the same as those of the semiconductor device with the first stress relaxation layer, and the surface of the semiconductor chip 20 is provided with the passivation film 1.
6, a surface protection film 18 is formed on the outermost surface of the semiconductor device, and an insulating film 17 interposed between the passivation film 16 and the stress relaxation layer 14 may be formed.

The arrangement of the chip electrodes is not limited to the arrangement of the four sides on the periphery shown in FIG. 3 and the arrangement of one line in the center shown in FIG. 5, but, for example, as shown in the plan view of FIG. In some cases. Further, various arrangements are conceivable, for example, when arranging both in the periphery and in the center, and when arranging them in two or more rows. The semiconductor device with the stress relaxation layer having such various arrangements is the first semiconductor device with the stress relaxation layer of this embodiment or the second semiconductor device with the stress relaxation layer.
May be used for the semiconductor device with the stress relaxation layer. The arrangement of the external terminals is not limited to the arrangement shown in the present embodiment.

Further, in the semiconductor device with the stress relaxation layer illustrated in FIGS. 3 to 7, since all the constituent members are formed in the plane of the semiconductor chip, it may be manufactured at the wafer level. That is, in a conventional semiconductor device manufacturing process, a large number of semiconductor chips are formed on a wafer, and from a state in which a passivation film is formed, wiring and external terminals are formed on each of the semiconductor chips cut out by dicing. Although the semiconductor device manufacturing process such as formation was performed, in the semiconductor device with the present stress relaxation layer, the stress relaxation layer, wiring, etc. were formed in the state of the wafer, the external terminals were formed, and then dicing was performed. It is possible to apply a wafer-level manufacturing method of separating semiconductor devices into individual semiconductor devices. Thereby, rather than performing the work of assembling each semiconductor chip into a semiconductor device,
Production costs may be significantly reduced. When manufacturing at the wafer level, it is desirable that the stress relaxation layer is formed by a printing method using, for example, a screen mask. As a result, the wafer can be formed in a lump,
In addition, it is easy to form it except on the chip electrode. In addition, since the wirings and lands are formed in a single wafer, it is desirable to use a thin-film wiring forming process using sputtering, plating, or the like.

When a wafer-level manufacturing method is used, as the number of semiconductor devices that can be obtained per wafer increases, the manufacturing cost can be reduced. However, if there are few good semiconductor chips that can be obtained per wafer, for example, because the semiconductor chips are large or the yield of the semiconductor chips is low, it is better to manufacture each semiconductor chip. In some cases, the cost may be lower.

FIGS. 8 and 9 show cross-sectional views of an example of the configuration of a semiconductor device having a stress relaxation layer on the assumption that manufacturing is performed for each chip. FIG. 8 shows a case where a chip electrode 31 is arranged in a peripheral portion of a semiconductor chip 30. Passivation film 3 formed on the surface of semiconductor chip 30
A stress relieving layer 34 is formed on 6 except for the chip electrode 32, and a tape 37 on which the wiring 32 and the land 33 are provided is attached. The wiring 32 has a lead portion that partially protrudes from the tape-like material 37, and the tip of the lead portion is connected to the chip electrode 32 to obtain electrical connection. Then, a lead portion of the wiring 32 and a connection portion with the chip electrode 32 are sealed with a sealing resin 38.

Also in this configuration, the thermal strain is absorbed by the stress relaxation layer 34, and the reliability of the external terminals can be improved. Further, in the multi-chip module of the first embodiment, even when the semiconductor device with the stress relaxation layer of the present configuration is applied to one or both of the first and second semiconductor devices with the stress relaxation layer, In order to satisfy the reliability of the multi-chip module, a semiconductor device with a stress relief layer having a longer outermost terminal distance or a smaller external terminal has a thicker or equal stress relief layer. However, in the semiconductor device with the stress relaxation layer of the present configuration, the connection between the wiring on the stress relaxation layer and the chip electrode is performed by the lead, and therefore, compared to the configurations of FIGS. Even if the stress relieving layer becomes thicker, the wiring formation is not so difficult. Therefore, when the present configuration is applied to the second semiconductor device with a stress relaxation layer, the ease of forming the stress relaxation layer and the existing equipment can be maintained as compared with the merit of reducing the material cost by making the stress relaxation layer thinner. If the merit such as use is greater, the stress relaxation layer may be formed thicker, knowing that the reliability will be overspecified.

FIG. 9 shows an example in which the chip electrodes 31 are arranged at the center of the semiconductor chip 32, although the configuration is almost the same as that of FIG. Chip electrode 31 in the center of the chip
The part where the wiring 32 is drawn out to the peripheral part from the
The rest is the same as the configuration of FIG. Further, in the present configuration, since the manufacturing is performed for each chip, the stress relaxation layer 34 and the tape-like material 37 may protrude from the end of the semiconductor chip 30. In that case, the external terminals may be formed outside the end of the semiconductor chip.

As shown in FIG. 2, the multi-chip module according to the present invention has a plurality of semiconductor chips and passive electronic components mounted on a substrate at high density, and has a function of operating as one system. . This module is secondarily mounted on a motherboard via external terminals 41 such as solder balls as shown in a sectional view of FIG. 10, for example. The mounting substrate 1 has a multi-layer wiring layer, and is electrically drawn out from the land 42 on the semiconductor chip mounting surface to the rear surface by the wiring 43 and the through hole 44, and the external terminal 41 is provided via the land 45 on the rear surface. Have been. It is mounted on the motherboard via the external terminal 41. FIG. 10 shows an example in which the through hole 44 penetrating the mounting board is provided, but the wiring may be drawn out to the back surface through a plurality of through holes not penetrating the mounting board.

Further, in the multi-chip module of the present invention, since the pitch of the external terminals is increased and then mounted on the mounting substrate, a dedicated substrate on which lands are arranged at a high density like a conventional multi-chip module using bare chips is mounted. Therefore, the semiconductor device with the stress relaxation layer and the passive electronic component may be directly mounted on the motherboard. That is, the mounting substrate 1 in FIG. 2 is a part of the motherboard, and is a part of the motherboard on which the above-mentioned electronic components are mounted at a high density, and is regarded as a multichip module having a function as one system.

In the multichip module of the present invention, three or more semiconductor chips may be mounted. At least two or more of them are joined to a mounting substrate in the form of a semiconductor device with a stress relaxation layer as shown in FIGS.

A certain reliability level is required for the multi-chip module. In a semiconductor device having a plurality of stress relaxation layers mounted thereon, stress relaxation is sufficient to ensure the reliability level at the longest outermost terminal distance. The thickness of the stress relief layer is increased as the outermost terminal distance is increased so as not to be formed thicker than the thickness of the layer. This is preferable from the viewpoint of reducing the material cost of the stress relaxation layer. However, if the advantage of cost reduction by unifying the process is great, a stress relaxation layer of the same thickness should be formed for the one with the shortest outer terminal distance in accordance with the one with the longest outer terminal distance. You may.

Further, in a semiconductor device with a stress relaxation layer in which the size of the external terminal is smaller than that of the others, the stress relaxation layer is formed thicker than the other semiconductor device with a stress relaxation layer in which the outermost terminal distance is large. Ensuring overall reliability is also conceivable. If the size of the external terminal has a greater effect on the life of the external terminal than the outermost terminal distance, the thickness of the stress relaxation layer is increased as the size of the external terminal becomes smaller. As a result, overall reliability can be ensured.

Further, when a semiconductor device having a stress relaxation layer for performing wiring connection by leads as shown in FIGS. 8 and 9 is mounted, the semiconductor device is compared with a device using thin film wiring.
Even if the stress relaxation layer becomes thicker, wiring formation is not so difficult.Therefore, the ease of forming the stress relaxation layer and the existing equipment can be used as is, rather than reducing the material cost by making the stress relaxation layer thinner. If the merit, such as performing, is greater, knowing that the reliability will be overspecified, the stress relaxation layer may be formed thicker than the semiconductor device with the stress relaxation layer with the longest outermost terminal distance. is there. Further, the multichip module of the present invention may include a semiconductor chip which is not in the form of a semiconductor device with a stress relaxation layer. For example, when the outermost terminal distance is relatively small and the size of the external terminal is relatively large, the reliability of the external terminal may be ensured without absorbing the strain by the stress relaxation layer. In such a case, as shown in the cross-sectional view of FIG. 11, a configuration without a stress relaxation layer may be used. In this case, in order to reduce the capacitance between the wiring 62 and the internal wiring of the semiconductor chip, the wiring 6
It is desirable to form an insulating film 67 between the passivation film 2 and the passivation film 66.

A multi-chip package in which a plurality of semiconductor chips are combined into one package may be included. FIG. 12 is a cross-sectional view illustrating an example of the configuration of a multichip package. A semiconductor chip 70 is attached to a dedicated substrate 71 via an adhesive layer 72 on a surface opposite to the surface on which the chip electrode 73 is formed. And the semiconductor chip 70 and the dedicated substrate 71 are electrically connected. A land 78 formed from the bonding pad 74 via the wiring 76 and the through hole 77 on the surface of the dedicated substrate 70 opposite to the surface on which the semiconductor chip 70 is bonded.
Until then, the external terminals 79 are joined to the lands 78 electrically. The semiconductor chip 70, the wires 75, and the vicinity of the joint are sealed with a sealing resin 80.
FIG. 10 shows an example in which the through hole 44 penetrating the mounting board is provided, but the wiring may be drawn out to the back surface through a plurality of through holes not penetrating the mounting board.

[0063]

According to the present invention, a multi-chip module having high reliability against thermal stress and the like can be provided.

[Brief description of the drawings]

FIG. 1 is a schematic plan view of a multichip module according to a first embodiment of the present invention.

FIG. 2 is a schematic cross-sectional view of the multichip module according to the first embodiment of the present invention.

FIG. 3 shows a first embodiment included in the first embodiment of the present invention.
FIG. 2 is a schematic plan view showing a detailed structure of a semiconductor device with a stress relaxation layer of FIG.

FIG. 4 illustrates a first embodiment included in the first embodiment of the present invention.
FIG. 2 is a schematic cross-sectional view showing a detailed structure of a semiconductor device with a stress relaxation layer of FIG.

FIG. 5 shows a second embodiment included in the first embodiment of the present invention.
FIG. 2 is a schematic plan view showing a detailed structure of a semiconductor device with a stress relaxation layer of FIG.

FIG. 6 shows a second embodiment included in the first embodiment of the present invention.
FIG. 2 is a schematic cross-sectional view showing a detailed structure of a semiconductor device with a stress relaxation layer of FIG.

FIG. 7 is a schematic plan view showing a detailed structure of a semiconductor device with a stress relaxation layer in which chip electrodes are arranged on two sides on the periphery.

FIG. 8 is a schematic cross-sectional view of a semiconductor device with a stress relaxation layer (disposed around a chip electrode) for manufacturing each semiconductor chip.

FIG. 9 is a schematic cross-sectional view of a semiconductor device with a stress relaxation layer (centered at a chip electrode) for manufacturing each semiconductor chip.

FIG. 10 is a schematic cross-sectional view of the multichip module of the present invention in which external terminals are formed on the back surface of a mounting board.

FIG. 11 is a schematic cross-sectional view of a semiconductor device in which a stress relaxation layer is not formed.

FIG. 12 is a schematic cross-sectional view of a multi-chip package on which a plurality of semiconductor chips are mounted.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Mounting board, 2 ... Semiconductor device with 1st stress relaxation layer,
3. Semiconductor device with second stress relaxation layer 4. Passive component
10: first semiconductor chip, 11: chip electrode, 12 ...
Wiring, 13 land, 14 stress relaxation layer, 14a thickness of stress relaxation layer, 15 external terminal, 16 passivation film, 17 insulating film, 18 surface protection film, 19 outermost terminal distance, 20 ... second semiconductor chip, 21 ... chip electrode, 22 ... wiring, 23 ... land, 24 ... stress relaxation layer, 2
4a: thickness of stress relaxation layer, 25: external terminal, 26: passivation film, 27: insulating film, 28: surface protection film, 3
0: semiconductor chip, 31: chip electrode, 32: wiring, 3
3 land, 34 stress relaxation layer, 35 external terminal, 36
Passivation film, 37 tape-like material, 38 sealing resin, 41 external terminal, 42 land, 43 wiring, 44
... Through hole, 45 ... Land, 60 ... Semiconductor chip,
61 ... chip electrode, 62 ... wiring, 63 ... land, 65 ...
External terminals, 66: passivation film, 67: insulating film,
68 surface protection film, 70 semiconductor chip, 71 dedicated substrate, 72 adhesive layer, 73 electrode electrode, 74 bonding pad, 75 wire, 76 wiring, 77 through hole, 78 land, 79 External terminals, 80: sealing resin

 ──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Hideo Miura 502, Kandate-cho, Tsuchiura-shi, Ibaraki Pref. Machinery Research Laboratory, Hitachi, Ltd. Hitachi, Ltd. Semiconductor Group

Claims (5)

[Claims] 1. A multi-chip module in which a plurality of semiconductor chips having semiconductor elements are mounted on a mounting substrate,
At least two or more of the semiconductor chips include a chip electrode of the semiconductor chip, a conductive wiring electrically connected to the chip electrode, a conductive land electrically connected to the wiring, An external terminal to be installed, a stress relaxation layer interposed between the land and the semiconductor chip, and a first semiconductor chip having a stress relaxation layer, which is installed on the mounting substrate via the external terminal. The stress relaxation layer has a stress relaxation layer, and the distance from the center of the semiconductor chip to the outermost terminal located at the end is smaller than the stress relaxation layer of the second semiconductor chip smaller than the first semiconductor chip. Multi-chip module characterized by being thick. 2. A multi-chip module in which a plurality of semiconductor chips having semiconductor elements are mounted on a mounting board,
At least two or more of the semiconductor chips include a chip electrode of the semiconductor chip, a conductive wiring electrically connected to the chip electrode, a conductive land electrically connected to the wiring, An external terminal to be installed, a stress relaxation layer interposed between the land and the semiconductor chip, and a first semiconductor chip having a stress relaxation layer, which is installed on the mounting substrate via the external terminal. The stress relief layer has a stress relief layer, and the projected area of the outermost terminal located at the end is thicker than the stress relief layer of the second semiconductor chip larger than the first semiconductor chip. Chip module. 3. The multi-chip module according to claim 1, wherein at least one of the semiconductor devices having the stress relaxation layer includes the wiring, the land, the external terminal, and the stress relaxation layer. Is formed inside the end of the semiconductor chip. 4. The multi-chip module according to claim 1, wherein said semiconductor device having said stress relaxation layer includes GaAs or InP as a substrate material of said semiconductor chip. 5. A multi-chip module in which a plurality of semiconductor chips having semiconductor elements are mounted on a mounting board,
At least two or more of the semiconductor chips include a chip electrode of the semiconductor chip, a conductive wiring electrically connected to the chip electrode, a conductive land electrically connected to the wiring, An external terminal to be installed, having a stress relaxation layer interposed between the land and the semiconductor chip, installed on the mounting board via the external terminal, providing a space around the external terminal, The distance between the end of the first semiconductor chip having the stress relieving layer and the end of the second semiconductor chip having the stress relieving layer arranged adjacent to the first semiconductor chip is less than 1 mm. Features multi-chip module.