JP2005094040A - Semiconductor device and mounting structure of semiconductor device - Google Patents

Abstract

In a small-sized semiconductor device that can be manufactured at a wafer level, an external terminal is highly reliable against a distortion caused by a difference in thermal expansion between a semiconductor element and a printed circuit board, and the capacitance of the wiring is reduced to make electrical Realize semiconductor devices with excellent performance.
SOLUTION: A low-elasticity and thick stress relaxation layer 5 is interposed between a semiconductor element 1 and a wiring 7 and a land 6 to absorb distortion caused by a difference in thermal expansion between the semiconductor element 1 and a printed circuit board 10 and externally. The reliability of the terminal 9 is improved, and the thick stress relaxation layer 5 is interposed, so that the capacitance between the wiring 7 and the internal wiring of the semiconductor element 1 is reduced and the electrical performance is improved. Also around the element electrode 2 where the stress relaxation layer 5 is not formed, the insulating film 4 is interposed between the wiring 7 and the semiconductor element 1 to reduce the capacitance of this portion. Since the land 11 on the printed circuit board 10 side protrudes into the external terminal 9 and the land 11 is miniaturized, the reliability of the external terminal 9 can be further improved and the external terminals 9 can be narrowed.
[Selection] Figure 5

Description

  The present invention relates to a small semiconductor device having an external terminal electrically connected to a semiconductor element, and a mounting structure of a semiconductor device in which the semiconductor device is mounted on a printed circuit board.

  In recent years, with the spread of portable terminals and the like, devices equipped with semiconductor devices are becoming smaller and lighter, and it is necessary to develop semiconductor devices corresponding to the miniaturization.

  Therefore, there is a technique for making the size of the semiconductor device as close as possible to the size of the semiconductor element. A package of a semiconductor device based on such a technique is generally called CSP (abbreviation of chip size package or chip scale package).

  In a typical structure of a CSP, metal bumps are arranged in the plane of a semiconductor element, and the semiconductor element is mounted on a printed circuit board via the metal bump. Solder is the most common material for the metal bumps.

  As described above, in a mounting structure in which a CSP is mounted on a substrate, when a temperature change is applied, a thermal deformation amount difference due to a difference in coefficient of linear expansion between the semiconductor element and the substrate is generated, and the semiconductor element is sandwiched between the semiconductor element and the substrate. The solder bumps are repeatedly subjected to thermal distortion, and the solder bumps are fatigued. Therefore, securing the life of the solder connection part in the temperature cycle test becomes a problem.

  As a conventional example of a CSP considering the life of a solder, for example, in Patent Document 1, a tape with an external terminal is provided on a circuit forming surface of a semiconductor element via a flexible material (elastomer resin), and the external terminal and the semiconductor element A CSP having a structure in which the electrode is electrically connected is described. Since the flexible elastomer resin is deformed to absorb the thermal strain, the strain generated in the solder bump can be reduced and the life can be improved.

  Patent Document 2 describes a structure in which a semiconductor element is mounted on a ceramic substrate provided with a through hole, an electrode is provided on the opposite surface of the ceramic substrate, and mounted on a printed circuit board. By using a ceramic substrate having a smaller linear expansion coefficient than the printed circuit board to be mounted, the difference in linear expansion coefficient between the semiconductor element and the printed circuit board is absorbed, and the life of the solder bumps is ensured.

  Many semiconductor elements are formed on a single wafer at a time. However, the above CSP examples are based on the premise that each semiconductor element is processed after being cut out from the wafer. is there.

  In recent years, technological development has been carried out to manufacture a small semiconductor device of the same size as a semiconductor element at a lower cost by packaging a large number of semiconductor elements in a wafer state. Yes.

  An example of a CSP that can be manufactured in a wafer state is proposed in Non-Patent Document 1. In the semiconductor device described in this document, a rewiring is formed on a semiconductor element, a metal via post having a height of about 100 μm is formed on the rewiring, the periphery of the via post is sealed with a resin, and the upper surface of the via post is sealed. Metal bumps are formed through the barrier metal layer. The sealing resin relaxes the difference in linear expansion coefficient between the semiconductor element and the printed circuit board, and reduces the stress generated in the metal bump connection portion.

  Further, in the semiconductor device disclosed in Patent Document 3, a low elastic modulus layer having an electrode arrangement region in which an element electrode is arranged is formed on a main surface of a semiconductor element, and an external portion is formed on the low elastic modulus layer. A metal wiring pattern is formed by forming a land to be an electrode and integrating the pad on the element electrode and the metal wiring for connecting the land, and the surface is covered with a solder resist, and the land is opened to form a metal ball. Are joined.

  In the above configuration, thermal stress can be absorbed by deformation of the low elastic modulus layer. In addition, since the end portion near the opening of the low elastic modulus layer is processed to have a slope shape, stress concentration on the metal wiring can be avoided and disconnection can be prevented.

  Further, a passivation film for protecting the semiconductor element may be further provided in a region other than the pad on the main surface of the semiconductor element. This conventional technique is considered to have a higher stress relaxation function than a structure using the above-described sealing resin if a sufficiently low elastic and thick low elastic modulus layer is used.

  In the same structure, a resin layer having a linear expansion coefficient between the semiconductor element and the low elastic modulus layer is interposed between the semiconductor element and the low elastic modulus layer, so that the semiconductor element and the low elastic modulus layer are interposed. Patent Document 4 describes a structure that prevents peeling of the film.

JP-T 6-504408 JP-A-6-224259 Japanese Patent Laid-Open No. 11-54649 JP-A-11-204560 Nikkei Microdevices April 1998 "Introducing a cheap way to make a CSP for chip size mounting" (pages 164-167)

  However, the conventional semiconductor device is considered to have the following problems.

  In the conventional semiconductor device described in Patent Document 3, stress due to the difference in thermal expansion between the semiconductor element and the mounting substrate is absorbed by elastic deformation of the low elastic modulus layer, thereby sufficiently ensuring the reliability of the metal bumps. In order to achieve this, it is considered that the low elastic modulus layer needs to be sufficiently thick.

  In the conventional semiconductor device, the thickness is preferably 10 to 150 μm. In addition, the opening is formed after the low elastic modulus layer is formed flat, and then, for example, exposure is performed using scattered light so that the side surface of the opening is not vertical but inclined.

  However, if such processing is performed on a thick film having a thickness of 100 μm or more, for example, the shape of the side surface is controlled, and the opening end of the bottom is controlled to a size close to the end of the fine device electrode. Requires very high-precision processing technology.

  Considering that this conventional semiconductor device is manufactured at the wafer level, the wafer is greatly warped when the thick low elastic modulus layer is formed on the entire surface of the wafer. It is difficult to perform high-precision processing.

  Another problem with CSP manufactured at the wafer level is that there is a problem with electrical characteristics. When manufacturing at the wafer level, it is difficult to form a thick resin film due to problems such as warpage of the wafer. The thickness of the insulating layer interposed between the semiconductor element and the semiconductor element tends to be thin, and the wiring capacity tends to increase.

  When the wiring capacitance increases, a large noise is generated in the signal line, and the device may malfunction. Therefore, how to secure the thickness of the insulating layer between the package wiring and the surface of the semiconductor element becomes a problem.

  The technique described in Patent Document 4 relates to a semiconductor device in which a resin layer is interposed between a semiconductor chip and a low elastic modulus layer. The elastic modulus and linear expansion coefficient of the semiconductor chip and the low elastic modulus layer are Because of the large difference, a resin film having an elastic modulus and a linear expansion coefficient between the semiconductor chip and the low elastic modulus layer is interposed in order to prevent stress from concentrating at the interface between the two and causing cracks and peeling. The stress is relieved.

  The resin film in the semiconductor device described in Patent Document 4 has an opening in the element electrode arrangement region, and the end of the opening is from the center of the element electrode compared to the opening end of the low elastic modulus layer. Since they are located at substantially the same position or far from each other, wiring is directly formed on the passivation film around the element electrodes.

  As described above, when the wiring is directly formed on the passivation film, the passivation film is an inorganic film and is difficult to form thickly. Therefore, the capacitance between the wiring and the package wiring is large. turn into.

  In this case, when the operation of the semiconductor device becomes faster in the future, malfunction may occur due to the capacitance between the wiring of the semiconductor device and the package wiring.

  Moreover, in the said conventional semiconductor device, it has the shape where the edge part of the semiconductor element and the edge part of the low elastic modulus layer and the soldering resist corresponded in the outer edge part. Therefore, when this semiconductor device is manufactured at the wafer level, the resin film and the semiconductor element having greatly different hardnesses are simultaneously cut when the wafer is finally diced and cut into individual semiconductor devices from the wafer. Become. Then, the vicinity of the interface between the resin film and the semiconductor element may be damaged, and the semiconductor element may be cracked or the interface may be peeled off.

  An object of the present invention is to solve the above-described problems, and to realize a semiconductor device and a mounting structure of the semiconductor device that can be manufactured at a wafer level with high reliability and excellent electrical characteristics.

In order to achieve the above object, the semiconductor device of the present invention is basically configured as follows.
(1) A semiconductor element, a conductive land for electrical connection between the semiconductor element and the outside, a surface protective film having an opening on the land and formed on the outermost surface, and the land A semiconductor device having at least an external terminal bonded to a printed circuit board having at least a conductive land for bonding an external terminal and a surface protective film having an opening on the land via the external terminal. In the connected semiconductor device mounting structure, on the semiconductor device side, the opening of the surface protection film is formed inside the end of the land, and in the printed circuit board, the land is formed of the surface protection film. The diameter of the land on the printed circuit board side is smaller than the diameter of the opening of the surface protective film on the semiconductor device side, which is formed inside the end of the opening.

In the semiconductor device of the present invention, the passivation film is an inorganic film such as SiN or SiO ₂ formed to protect the semiconductor element and has a thickness of 1 μm at most.

  The stress relaxation layer is formed using a low elastic resin material having a longitudinal elastic modulus of about 2000 MPa or less and a thickness of about 40 μm or more. This stress relaxation layer can absorb the distortion caused by the difference in thermal expansion between the semiconductor element and the printed circuit board when the semiconductor device is mounted on the printed circuit board, reducing the distortion generated in the external terminals and increasing the reliability. Can be realized.

  The stress relaxation layer is formed by applying to a portion other than the element electrode using a printing method. Since the opening is already formed at the stage of application, there is no need for a step of removing the opening, so that the above-described problem that it is difficult to process a warped wafer does not occur.

  Moreover, the edge part of the opening part of the apply | coated stress relaxation layer flows, and becomes a gentle slope shape. By forming the edge part into a slope, it is easy to form wiring at the step even if the stress relaxation layer is thick, and stress concentration on the wiring formed at the step part is reduced. High nature.

  On the other hand, the portion where the end portion flows and becomes inclined has a relatively large distance, so that it is difficult to control the size of the opening with high accuracy. In order to surely open the element electrode, it is necessary to form the opening end of the stress relaxation layer at a position sufficiently away from the element electrode.

  At this time, since the distance between the wiring and the surface of the semiconductor element is small in the portion where the stress relaxation layer near the element electrode is not formed and in the portion near the base of the slope of the stress layer relaxation layer, the wiring in this portion is static. There is concern about an increase in electric capacity.

  Therefore, in the present invention, an insulating film interposed between the stress relaxation layer and the passivation film is formed, and this insulating film is interposed between the wiring and the surface of the semiconductor element even in the vicinity of the element electrode, thereby reducing the wiring capacitance. The semiconductor device with excellent electrical characteristics is realized.

  The thickness of the insulating film may be adjusted according to the electrical characteristic level required for the semiconductor device, and is about 3 to 20 μm. On the element electrode, the opening of the insulating film is formed inside the opening of the passivation film.

  As a result, the wiring drawn from the element electrode rises immediately on the insulating film without passing through the passivation film, which is advantageous in terms of electrical characteristics. In addition, if the opening of the passivation film is on the inside, the end of the passivation film protrudes from the end of the insulating film, so stress concentration may occur in the wiring at this part, and there is a concern about disconnection. is there. Further, since it is necessary to form an opening on a fine element electrode, a highly accurate processing method such as photolithography is used for the opening of the insulating film.

  The insulating film in the semiconductor device of the present invention is interposed between the wiring near the element electrode and the surface of the semiconductor element, and is formed to reduce the capacitance of the wiring.

  The semiconductor device of the present invention can be manufactured at the wafer level, and can be manufactured, for example, by the following process.

  A passivation film is formed on the wafer surface on which a large number of semiconductor elements are formed, and the element electrodes are opened. Further, a photosensitive resin material to be an insulating film is first applied on the entire surface of the wafer by spin coating, and an opening is formed on the device electrode using photolithography.

  Next, a resin material to be a stress relaxation layer is applied to the entire surface of the wafer by printing. The screen mask used at the time of printing has a pattern for masking the element electrode formation region, and an opening is formed in the element electrode formation region simultaneously with printing. It is allowed to stand until the end of the stress relaxation layer flows to form a slope, and then dried.

  Next, lands on the stress relaxation layer and wirings extending from the element electrodes to the lands are collectively formed on the entire surface of the wafer using a thin film process. A metal seed film is formed on the entire surface of the wafer by sputtering, a photoresist is applied thereon by spin coating, a wiring and land pattern is opened by photolithography, the resist pattern is used as a guide, and the wiring and land are formed by electroplating. When the photoresist is peeled off and the metal seed film is removed by etching, the electroplated portion remains and wiring and lands are formed.

  Next, a photosensitive resin material to be a surface protective film is formed on the entire surface of the wafer by spin coating or printing, and an opening is formed on the land by photolithography. Next, the solder ball is mounted on the opening on the land using a mask, melted by reflow, and bonded to the land. Finally, dicing is performed to cut out each semiconductor device.

  Thus, when the semiconductor device of the present invention is formed by a wafer process, it is necessary to finally cut the wafer by a dicer and separate it into individual semiconductor devices, but a line to be cut by a cutter (referred to as a scribe line). If a resin film such as an insulating film, a stress relaxation layer, or a surface protective film is present on the top, the resin film and the semiconductor element having greatly different hardnesses are simultaneously cut. Then, the interface between the resin film and the semiconductor element may be peeled off, or damage such as a crack may occur in the semiconductor element near the interface may occur.

  Therefore, in the semiconductor device of the present invention, preferably, the end portions of the insulating film, the stress relaxation layer, and the surface protective film are formed at the end portions of the semiconductor device so as to be inside the end portions of the semiconductor elements. By doing so, the resin film does not exist in the scribe area, and damage during dicing can be reduced.

  In the semiconductor device of the present invention, the main surface of the semiconductor element is covered with a thick stress relaxation layer, which may cause malfunction of the semiconductor device. It is a semiconductor device that can block incoming light and has high reliability with respect to α rays and light.

  However, since there is no stress relaxation layer in the vicinity of the element electrode formation region, intrusion of α rays and light from this portion becomes a problem. In the semiconductor device of the present invention, since the insulating film is formed in the element electrode formation region, the α gland and light can be blocked to some extent by the insulating film.

  Further, when the thickness of the insulating film is insufficient, preferably, the surface protective film is formed thicker on the element electrode formation region than on the flat portion of the stress relaxation layer. And the surface protective film are combined to ensure the thickness necessary to block α rays and light.

  According to the present invention, it is possible to realize a mounting structure of a semiconductor device that has high reliability and excellent electrical characteristics and can be manufactured at a wafer level.

  That is, the present invention relates to a structure of a small semiconductor device that can be manufactured in a wafer state, and a low-elasticity and thick stress relaxation layer is interposed between a semiconductor element, a wiring, and a land. Improves the reliability of external terminals by absorbing strain due to the difference in thermal expansion between the semiconductor element and the printed circuit board during temperature cycling, and reduces the capacitance between the wiring and the internal wiring of the semiconductor element to improve electrical performance Can be improved.

  Further, even in the vicinity of the element electrode where the stress relaxation layer is not formed, an insulating film is interposed between the wiring and the semiconductor element, so that the capacitance of this portion is considered to be reduced.

  Further, in the mounting structure in which the semiconductor device of the present invention is mounted on the printed circuit board, the land on the printed circuit board side protrudes into the external terminal, and the reliability of the external terminal is reduced by reducing the diameter of the land. Can be further improved, and the pitch of the external terminals can be reduced.

Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings.
A semiconductor device according to a first embodiment of the present invention will be described with reference to FIGS. FIG. 1 is a cross-sectional view showing the first embodiment, and FIG. 2 is a plan view showing a state in which the external terminals and the surface protective film are partially removed in the first embodiment.

  The semiconductor device 14 according to the first embodiment of the present invention includes a semiconductor element 1, an element electrode 2 formed on the surface of the semiconductor element 1, and an opening formed on the element electrode 2 formed on the surface of the semiconductor element 1. A passivation film 3, an insulating film 4 formed on the passivation film 3 so that the surface of the device electrode 2 is exposed, and a stress relaxation layer 5 formed on the insulating film 4 so that the device electrode 2 is exposed. The conductive land 6 formed on the stress relaxation layer 5, the conductive wiring 7 connecting the element electrode 2 and the land 6, and the top surface of the semiconductor device 14 are formed on the land 6. And a conductive external terminal 9 joined to the land 6.

  The ends of the openings formed in the passivation film 3, the insulating film 4, and the stress relaxation layer 5 are close to the insulating film 4, the passivation film 3, and the stress relaxation layer 5 in this order at a distance from the center of the element electrode 2. Formed to be.

  The semiconductor element 1 includes a device structure such as a capacitor and a large number of wiring layers and insulating layers that connect them, and has an element electrode 2 on the surface for electrical connection with the outside. The device electrode 2 is covered with a thin inorganic passivation film 3 having an opening.

  The first embodiment of the present invention shows an example in which the device electrodes 2 are arranged in a line at the center of the semiconductor device 1.

  In the semiconductor device of the present invention, the lands 6 for connection to the external terminals 9 are formed on the stress relaxation layer 5, and the stress relaxation layer between the semiconductor elements 1 is directly below all the external terminals 9. 5 intervenes. The stress relaxation layer 5 is made of a material having a small elastic modulus and is formed thick, whereby the semiconductor device 1 when the semiconductor device of the first embodiment of the present invention is mounted on a printed circuit board and used. The thermal strain caused by the difference in thermal expansion from the printed circuit board can be absorbed by the deformation of the stress relaxation layer 5, and the life of the external terminal 9 against the temperature cycle can be improved.

  Moreover, the opening part edge part of the stress relaxation layer 5 is formed in the gentle slope shape. Therefore, compared to the case where the end portion is vertical, it is easy to form a wiring on the step of the thick stress relaxation layer 5, and the stress concentration on the wiring formed on the step portion can be reduced. high.

  In order to form an opening in the thick stress relieving layer 5 and make the end of the opening have a slope, in the semiconductor device of the present invention, the stress relieving layer is formed using a printing method. By forming a pattern that masks the formation area of the element electrode 2 on the screen mask used at the time of printing, an opening is formed at the same time as printing, and the end flows after printing and naturally forms a slope. become.

  When the semiconductor device of the present invention is manufactured at the wafer level, for example, when a method is used in which the stress relaxation layer is formed flat on the entire surface of the wafer and then the opening is removed by photolithography or the like, the wafer is formed at the stage of flat formation. It is difficult to perform removal processing with high accuracy. In addition, it is difficult to form the end in a gentle slope shape.

  Therefore, by using the printing method, since the opening is formed simultaneously with the application of the material, the above-described problem of the warp of the wafer is eliminated, and the inclined surface can be efficiently formed. Further, since the removal process can be omitted, the cost can be reduced.

The insulating film 4 is made of an insulating resin material and is formed for the purpose of interposing between the wiring 7 and the surface of the semiconductor element 1 and reducing the capacitance between them.
In a semiconductor device made by stacking a thin film on a semiconductor element like the semiconductor device of the present invention, the proximity between the wiring of the semiconductor device and the wiring inside the semiconductor element increases the capacitance between the two, There is a concern that the noise generated on the wire will increase, causing the device to malfunction.

  In the semiconductor device of the present invention, most of the wiring 7 has the thick stress relaxation layer 5 interposed between the semiconductor element 1 and the capacitance of this portion can be reduced. However, since the stress relaxation layer 5 is formed by the printing method as described above, the portion where the end portion flows and becomes inclined is relatively large, and it is difficult to control the position of the end portion with high accuracy. In order to reliably open the electrode 2, the end portion of the stress relaxation layer 5 is formed at a position sufficiently away from the element electrode 2.

  For this reason, the distance between the wiring 7 and the semiconductor element 1 becomes small at the portion near the element electrode 2 where the stress relaxation layer 5 is not formed and the portion near the bottom of the slope of the stress relaxation layer 5. There is concern about the increase.

  Therefore, by forming the insulating film 4 so as to be interposed between the wiring 7 and the semiconductor element 1 in the vicinity of the element electrode 2, the wiring capacity of this portion is reduced and a semiconductor device having excellent electrical characteristics is realized. can do.

  The opening of the insulating film 4 is formed inside the opening of the passivation film 3. As a result, the wiring drawn out from the element electrode immediately rises on the insulating film 4 without passing through the passivation film 3, which is advantageous in terms of electrical characteristics. Further, when the opening of the passivation film 3 is set to the inside, the end of the passivation film 3 has a shape protruding from the end of the insulating film 4. It is to be done.

  As the insulating film 4 is thicker, the effect of reducing the capacitance is higher. However, it is necessary to process an opening on the fine element electrode 2 and, for example, a high-precision processing method such as photolithography is used. It is not formed as thick as the relaxation layer 5. What is necessary is just to adjust thickness between 3-20 micrometers according to the level of the electrical property requested | required of a semiconductor device, for example.

Here, when alpha rays generated from the external terminal or light entering from the external environment reach the semiconductor element, it may cause malfunction of the device. In the semiconductor device of the present invention, α-rays and light can be sufficiently shielded by the thick stress relaxation layer 5.
In the vicinity of the device electrode 2, the stress relaxation layer 5 is not present or is slanted and thin. However, in this portion, the insulating film 4 is formed, and α-rays and light are formed with a thickness combined with the surface protective film 8. Shield.

  Here, in the step of forming the surface protective film 8, if a method of applying a material by spin coating or printing is employed, a larger amount of material is present in the opening near the element electrode 2 than in the flat portion of the stress relaxation layer 5. By flowing in, the thickness of the surface protective film 8 becomes thicker than on the flat portion of the stress relaxation layer 5, and the thickness of the resin film near the element electrode 2 can be compensated.

  As described above, a semiconductor device having a high shielding effect against α rays and light can be realized.

  In the semiconductor device of the present invention, the manufacturing process up to the formation of the external terminal 9 can be performed at the wafer level, thereby reducing the cost of the manufacturing process.

  When using a manufacturing process at the wafer level, it is necessary to form the external terminals 9 and then cut the wafer. The semiconductor element 1 may be composed mainly of Si or a compound semiconductor such as GaAs or InP as a material, but when cutting such a semiconductor element, on the scribe line to be cut, If resin films such as the insulating film 4, the stress relaxation layer 5, and the surface protective film 8 exist and are cut simultaneously with the hard semiconductor element 1, damage at the time of cutting occurs at the end, and the end of the semiconductor element 1 is generated. There is a possibility that a crack may occur or peeling occurs between the semiconductor element 1 and the resin film. Therefore, preferably, the insulating film 4, the stress relaxation layer 5, and the surface protective film 8 are formed inside the end portion of the semiconductor element 1 at the end portion of the semiconductor device, and these resin films exist on the scribe line. Do not.

  The inventors of the present application actually made a prototype to confirm that the semiconductor device having the structure of the first embodiment can be manufactured in a wafer state and has high reliability.

The manufacturing process of the prototype semiconductor device is as follows.
After a photosensitive resin material is applied by spin coating on a Si wafer on which a large number of semiconductor elements are formed, the openings on the element electrodes 2 and the resin on the scribe lines are removed by photolithography to insulate A film 4 was formed.

  Next, the stress relaxation layer 5 was applied by printing using a screen mask that masks the vicinity of the device electrode 2 and on the scribe line, left to stand for a while, and then dried to form a shape having a slope at the end.

  Next, a metal seed film is formed on the front surface by sputtering of Cr and Cu, a photosensitive plating resist is applied thereon by spin coating, and the resist of the pattern portion of the wiring 7 and land 6 is removed by photolithography. The wiring 7 and the land 6 are formed by electroplating of Cu and Ni, the plating resist is peeled off, and the metal seed film other than the pattern portion of the wiring 7 and the land 6 is further removed by etching. And land 6 was formed.

Next, a photosensitive resin material was applied by spin coating to form a surface protective film, and the openings on the lands 6 and the resin on the scribe lines were removed.
Next, a flux was applied to the opening on the land 6, and a ball-shaped solder material was placed thereon as the external terminal 9. The solder material was melted by heating in a reflow furnace and joined to the land 6.

  Finally, the dicing machine cut the wafer scribe line to obtain individual semiconductor devices.

  Note that the manufacturing process and the material of the constituent members are not limited to those described above, and the purpose of forming each constituent member can be achieved, and different materials and processes can be selected as long as the shape can be formed. There is also.

  For example, a wafer on which a semiconductor element is formed is not limited to Si, and a Si-based compound such as SiGa or a compound semiconductor such as GaAs or InP may be used.

  For the device electrode 2, the first land 6, and the first wiring 7, a material such as copper (Cu), aluminum (Al), or chromium (Cr) is used alone or in an alloy state using a plurality of materials. In some cases, the surface is plated with nickel (Ni), gold (Au), or the like.

  Examples of the material of the insulating film 4, the stress relaxation layer 5, and the surface protective film 8 include polyimide resin, polyimide amide resin, polyether imide resin, polyether amide imide resin, acrylic modified epoxy resin, epoxy resin blended with rubber, and silicone. There are resins.

  For the external terminal 9, for example, a solder material such as Sn—Pb, Sn—Ag—Cu, or Sn—Ag—Cu—Bi is used.

FIG. 3 is a cross-sectional view of the semiconductor device according to the first embodiment of the present invention mounted on a printed circuit board.
In FIG. 3, the printed circuit board 10 has a land 11 for joining the external terminal 9, and a surface protective film 13 is formed on the outermost surface, and the surface protective film 13 has an opening on the land 11. Between the lands 11 is wired inside the printed circuit board 10 by the conductive wiring 12 (most of the drawing is omitted in FIG. 3).

  The inventors of the present application examined the relationship between the temperature cycle life of the external terminal 9 and the thickness and elastic modulus of the stress relaxation layer 5 using simulation by a finite element method prior to the trial evaluation.

  The result is shown in the graph of FIG. The horizontal axis in FIG. 4 indicates the thickness of the stress relaxation layer 5, and the maximum value of the equivalent plastic strain range (vertical axis) generated in the external terminal 9 when the thickness of the stress relaxation layer 5 and the longitudinal elastic modulus are changed. Shows changes.

  As can be seen from FIG. 4, as the elastic modulus of the stress relaxation layer 5 is reduced and the thickness is increased, the strain generated in the external terminal 9 is reduced and the life is increased. However, the specifications of the stress relaxation layer 5 necessary for obtaining a certain reliability level vary depending on the size and material of the semiconductor element 1, the size and material of the external terminal 9, the linear expansion coefficient of the printed circuit board 10, and the like. come.

  As the size of the semiconductor element 1 increases, as the difference in the linear expansion coefficient between the semiconductor element 1 and the printed circuit board 10 increases, and as the size of the external terminal 9 decreases, the stress relaxation layer 5 increases in thickness, or It is desirable to reduce the elastic modulus.

The inventors of the present application mounted a prototype semiconductor device on a test substrate and conducted a temperature cycle test to evaluate the reliability of the semiconductor device of the present invention. The size of the semiconductor element is about 10 mm square, the size of the solder ball as an external terminal is about 400 μm in diameter, the substrate is a general-purpose FR-4 substrate, and the linear expansion coefficient is about 15 × 10 ⁻⁶ / ° C.

  As a result of performing a temperature cycle test at −55 to 125 ° C., the longitudinal elastic modulus at room temperature (25 ° C.) is about 2000 MPa, the thickness at the flat portion is about 75 μm, and the longitudinal elastic modulus is about 900 MPa and thick. When the length is about 40 μm, the life of the external terminal is about 1000 times.

  Further, in the specification having a longitudinal elastic modulus of about 900 MPa and a thickness of about 70 μm, the life was about 2500 times. Furthermore, in the specification in which the stress relaxation layer 5 was not formed, the life was about 350 times.

  From these results, it was found that the formation of the stress relaxation layer 5 has an effect of improving the life of the external terminal 9, and it was found that the semiconductor device of the present invention has high reliability. Further, in order to obtain a life of 1000 times or more, a thickness of about 40 μm or more is required in the flat portion of the stress relaxation layer 5.

In the semiconductor device of the present invention in which the wiring 7 and the land 6 are formed on the flexible stress relaxation layer 5, the wiring 7 and the land 6 are deformed by the stress relaxation layer 5 as the stress relaxation layer 5 becomes less elastic. However, in the above-described prototype specifications, the wiring 7 and the land 6 are not disconnected, and the semiconductor device of the present invention allows the wiring 7 and the land 6 to be broken. It was confirmed that reliability could be secured.
In addition, the board | substrate which mounted the prototype is a cheap thing generally used.

  In the semiconductor device of the present invention, the pitch is widened by pulling out the wiring 7 from the element electrode 2 with a narrow pitch, so that a substrate with a narrow pitch is not required, and the stress relaxation layer 5 absorbs thermal strain. In order to improve the life of the external terminal 9, a low thermal expansion substrate or underfill after the substrate mounting is not required, that is, even if mounting by only solder reflow using a general inexpensive substrate, It is characterized by high reliability.

  FIG. 5 is a sectional view of a mounting structure in which a semiconductor device according to a second embodiment of the present invention is mounted on a substrate.

  The difference between the structure of the second embodiment and the structure of the example shown in FIG. 3 is that the diameter of the opening formed in the surface protective film 13 is larger than the diameter of the land 11 on the printed circuit board 10 side. In the state in which the external terminal 9 is joined to the land 11, the land 11 has a shape protruding into the external terminal 9.

  FIG. 6 is a plan view showing the relationship between the land 11 and the surface protective film 13. 6A is a plane on the semiconductor device 14 side, and FIG. 6B is a plane on the printed circuit board 10 side. As shown in FIG. 6, the wiring 7 and the wiring 12 are usually thickened in the vicinity of the connecting portion in order to reinforce the connecting portion with the land 6 and the land 11. Here, the land indicates a circular portion.

  As shown in FIG. 6A, on the semiconductor device 14 side, the opening 8a of the surface protective film 8 is formed on the land 6 inward of the end of the land 6, and the opening of the surface protective film 8 is formed. The diameter 8b is smaller than the diameter 6b of the land 6.

  On the other hand, as shown in FIG. 6B, on the printed circuit board 10 side, the land 11 is formed inside the end of the opening 13a of the surface protection film 13, and the diameter 11b of the land 11 is the surface protection. The diameter of the opening of the film 13 is smaller than 13b.

  The destruction of the external terminal 9 due to the temperature cycle occurs in the vicinity of the connection portion with the land 6 or the land 11 where distortion is concentrated inside the external terminal 9. When the land 11 protrudes into the external terminal 9 on the printed circuit board 10 side as in the second embodiment shown in FIG. 5, the rigidity in the vicinity of the connecting portion is the same as that of the land 6 on the semiconductor device 14 side. It is relatively higher than the vicinity of the connecting portion.

  If the rigidity balance in the vicinity of the connection portion between the semiconductor device 14 side and the printed circuit board 10 side is poor, strain is concentrated on one side and the life until destruction is reduced, so that the rigidity on both sides can be balanced. desirable.

  Therefore, the diameter 11b of the land 11 on the printed circuit board 10 side is made smaller than the diameter 8b of the opening of the surface protective film 8 on the semiconductor device 14 side, and the rigidity of both connecting portions is balanced.

  With the above configuration, the life of the external terminal 9 is improved as compared with the structure in which the land does not protrude into the external terminal 9 on both the semiconductor device 14 side and the printed circuit board 10 side as shown in FIG.

  According to the experiments by the inventors of the present application, the life of the external terminal 9 in the temperature cycle test of the prototype improved by about 10% in a plurality of specifications.

  Further, in the configuration according to the second embodiment of the present invention, the diameter 11b of the land 11 on the substrate 10 side can be reduced as compared with the configuration in the example of FIG. The number of wires 12 passing between adjacent lands 13 can be increased, or if the number of wires is the same, the land interval can be narrowed and the pitch can be narrowed.

  In the semiconductor device of the present invention, since a thin film wiring formation process that is an extension of the wafer process is used for wiring formation, it is possible to narrow the pitch by fine processing, but in order to cope with it on the printed circuit board 10 side, The problem arises that an expensive substrate must be used. The configuration of the present invention is characterized in that the pitch can be narrowed even with an inexpensive substrate having a limit for fine processing.

  FIG. 7 is a plan view showing a semiconductor device according to a third embodiment of the present invention. The basic structure and material are the same as those in the first embodiment, and the difference between the third embodiment and the first embodiment is the planar structure of the wiring shown in FIG. In the example, in order to clearly show the difference from the first embodiment, the outermost surface protective film 8 and the external terminal 9 shown in FIG. 2 are omitted.

  The feature of the third embodiment of the present invention is that the thickness of the power supply line 18 or the ground line 16 drawn from the power supply pad 17 or the ground pad 15 provided on the semiconductor element 1 is drawn from the signal pad 19. The signal wiring 20 is significantly thicker than the signal wiring 20 and the occupied area occupied by both wiring regions is significantly increased even when compared with the example of FIG.

  The main purpose of this thickening is not only to reduce the power supply and ground wiring resistance, but also to ensure that at least one of both wirings is in close proximity to each signal wiring 20. Thereby, there is an effect that various electromagnetic noises such as simultaneous switching noise generated when a high frequency signal of several hundred MHz or more flows through the signal line can be reduced.

  FIG. 8 is a plan view showing a semiconductor device according to the fourth embodiment of the present invention. The basic structure and material are the same as those in the first embodiment. The difference from the first embodiment is that the device electrode 2 is arranged in the center of the semiconductor device in the first embodiment shown in FIG. In contrast, in the fourth embodiment, the element electrode 2 is disposed in the peripheral portion of the semiconductor element.

  The structure of the first embodiment is suitable for a memory system product having a few tens of external terminals 9 and relatively few. On the other hand, the structure of the fourth embodiment of the present invention is the number of external terminals 9. Is suitable for hundreds of microcomputers and logic LSI products.

  Also in the fourth embodiment of the present invention, the positional relationship between the openings of the passivation film 3, the insulating film 4, and the stress relaxation layer 5 in the vicinity of the device electrode 2 is the same as in the case of the first embodiment. Further, the stress relaxation layer 5 is formed so as to have a sloped periphery, and is formed at a position separated so that the end of the slope does not cover the device electrode 2.

  The opening of the insulating film 4 is formed inside the opening of the passivation film 3 so that the wiring 7 drawn out from the element electrode 2 immediately rises on the insulating film 4.

  Also in the fourth embodiment of the present invention, the dicing damage can be reduced by forming the end portion of the resin layer inside the end portion of the semiconductor element 1 as in the case of the first embodiment. . Further, by forming the surface protective film 8 thick around the element electrode 2, it is possible to realize a semiconductor device excellent in shielding α rays and light.

  Further, when mounting on the printed circuit board 10, the relationship between the land and the surface protective film is configured as in the second embodiment, thereby improving the reliability of the external terminal 9 and narrowing the external terminal 9. It can be pitched.

Furthermore, the reliability against electromagnetic noise can be improved by thickening the power supply wiring and the ground wiring as in the third embodiment.
FIG. 9 is a plan view showing a semiconductor device according to the fifth embodiment of the present invention. In the fifth embodiment, as in the fourth embodiment, the element electrode 2 is arranged in the peripheral portion of the semiconductor element. However, the fifth embodiment is different from the fourth embodiment in that it is opposed to the peripheral four sides. The element electrode 2 is arranged on two sides. Other parts are the same as those in the fourth embodiment and the fifth embodiment.

  As described above, in the first, fourth, and fifth embodiments of the present invention, the structures of the element electrodes 2 are different from each other. However, in the semiconductor device of the present invention, the arrangement of the element electrodes 2 is The present invention is not limited to the first, fourth, and fifth embodiments.

  Even in arrangements other than those described above, the insulating film 4 is configured to be interposed between the wiring 7 and the passivation 3 in the vicinity of the element electrode 2 as described in the description of the first embodiment. Also, the effects of the present invention can be obtained.

  A plurality of semiconductor devices of the present invention may be mounted on a printed circuit board. For example, by mounting a plurality of memory products to which the structure of the semiconductor device of the present invention is applied, a memory module having a larger capacity is formed, or a plurality of semiconductor devices having different functions such as a memory and a microcomputer are mounted. Thus, a module having a more complicated function can be realized.

  As an example, FIG. 10 shows a plan view of a semiconductor device mounting structure according to a sixth embodiment of the present invention. This is an example in which eight memory products of the same type are mounted on a printed circuit board, and a memory module having a capacity eight times that of a single memory is realized.

  As described above, in a mounting structure in which a plurality of semiconductor devices of the present invention are mounted, each semiconductor device has a stress relaxation layer inside, and therefore, the reliability of the external terminal with respect to the temperature cycle is high. Therefore, it is not necessary to reinforce the external terminals by sealing the space between the semiconductor device and the printed circuit board with an underfill resin.

  When underfill mounting is used, if the underfilled semiconductor device is defective, it cannot be replaced (repaired), and in addition to the mounted substrate, other good chips mounted before that are wasted. There is a fear.

  On the other hand, when the module is constituted by the semiconductor device of the present invention, the semiconductor device can be repaired, and thus there is no problem as described above.

1 is a schematic cross-sectional view showing a semiconductor device according to a first embodiment of the present invention. 1 is a schematic plan view of a semiconductor device according to a first embodiment of the present invention. It is a schematic sectional drawing which shows the mounting structure which mounted the semiconductor device of the 1st Embodiment of this invention in the printed circuit board. It is a graph which shows the relationship between the longitudinal elastic modulus and thickness of a stress relaxation layer, and the distortion which generate | occur | produces in an external terminal. It is a schematic sectional drawing which shows the board | substrate mounting structure of the semiconductor device which is the 2nd Embodiment of this invention. In the 2nd Embodiment of this invention, it is a top view which shows the relationship between a land and the opening part of a surface protective film. It is a top view which shows the semiconductor device which is the 3rd Embodiment of this invention. It is a top view which shows the semiconductor device which is the 4th Embodiment of this invention. It is a top view which shows the semiconductor device which is the 5th Embodiment of this invention. It is a top view which shows the board | substrate mounting structure of the semiconductor device which is the 6th Embodiment of this invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Semiconductor element 2 Element electrode of semiconductor element 3 Passivation film 4 Insulating film 5 Stress relaxation layer 6 Land 6b Land diameter 7 Wiring 8 Surface protective film 8a Surface protective film opening 8b Surface protective film opening diameter 9 External terminal DESCRIPTION OF SYMBOLS 10 Printed circuit board 11 Land 11b Land diameter 12 Wiring 13 Surface protection film 13a Surface protection film opening 13b Surface protection film opening diameter 14 Semiconductor device 15 Ground pad 16 Ground wiring 17 Power supply pad 18 Power supply wiring 19 Signal pad 20 Signal wiring

Claims (1)

A semiconductor element, a conductive land for electrical connection between the semiconductor element and the outside, a surface protective film having an opening on the land and formed on the outermost surface, and bonded to the land A semiconductor device having at least an external terminal connected to a printed circuit board having at least a conductive land for joining an external terminal and a surface protective film having an opening on the land via the external terminal In the mounting structure of
On the semiconductor device side, the opening portion of the surface protective film is formed inside the end portion of the land, and in the printed circuit board, the land is formed inside the opening end portion of the surface protective film. A semiconductor device mounting structure characterized in that the diameter of the land on the printed circuit board side is smaller than the diameter of the opening of the surface protective film on the semiconductor device side.

Images