JP2002118184A - Operating method of nonvolatile semiconductor memory device - Google Patents

Abstract

(57) [Summary] A p-channel type memory transistor is provided.
Stored information is reliably read while minimizing deterioration of the insulating film due to hole injection. A channel formation region made of an n-type semiconductor;
two source / drain regions S / D made of a p-type semiconductor and sandwiching the channel formation region, the gate insulating film 10 and the gate electrode G on the channel formation region, and discrete in the plane facing the channel formation region and in the film thickness direction In a non-volatile semiconductor memory device having charge storage means (carrier trap formed centering on the nitride film 12) formed in the gate insulating film 10 after being formed, the generated channel is generated by accelerating the electric field in the formed channel. Hot holes are injected into the charge storage means to perform writing, generate hot electrons due to the interband tunnel current on the source / drain region S / D side, and transfer the hot electrons to the charge storage means in which the holes are held. Erasing is performed by injecting into the distribution region.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a charge storage means (for example, a MONOS type or MNOS type) which is discretized planarly in a gate insulating film between a channel forming region of a memory transistor and a gate electrode. A charge trap in the nitride film, a charge trap near the interface between the top insulating film and the nitride film, or a small-diameter conductor, etc., and electrically injects and accumulates charges into the charge accumulating means; The present invention relates to an operation method of a nonvolatile semiconductor memory device whose basic operation is extraction.

[0002]

2. Description of the Related Art In a nonvolatile semiconductor memory, an FG in which charge storage means (floating gate) for holding charges is continuous in a plane is used.
(Floating Gate) type and charge storage means (carrier trap etc.) are discretized in a plane. For example, MONOS (Met
al-Oxide-Nitride-Oxide Semiconductor). As a memory cell array system, DIN
OR (Divided bit line NOR), a source line separated, or a common VG (V
There are various types such as NOR type and NAND type including ertual ground).

For example, in Japanese Patent Application Laid-Open No. 9-8153,
DIN having p-channel FG type memory transistor
In the OR type memory cell, the surface of the drain region is depleted to form inter-band tunneling (BTBT; Band-To-Band).
BBHE (Band-To-Ban) that injects hot electrons generated using Tunneling into a floating gate.
d tunneling induced hot electron) A writing method is disclosed (prior art 1). In the erasing in the prior art 1, electrons are drawn out to the entire channel by FN tunneling.

In addition, for example, “Extended Abstract of t
he 1999 International Conferenceon Solid State Dev
Ices and Materials, Tokyo, 1999, pp. 522-523 ”, paying attention to the fact that electric charges can be injected into a part of discrete traps of a MONOS type memory transistor by the CHE injection method, A technique has been reported in which two bits can be recorded per memory cell by independently writing binary information on the memory side (Prior Art 2). Bit information is written by CHE injection, and at the time of reading, a predetermined voltage is applied between the source and the drain in the direction opposite to the writing, so-called "reverse read" method. In addition, in the erase operation, band-to-band tunneling (BT) is performed on the source side or the drain side. The hot holes generated by BT) are injected into a part of the discrete trap in which electrons are held, and this technique has made it possible to shorten the writing time and greatly reduce the bit cost.

Further, this 2-bit / cell storage technique is called p
The technology applied to the channel type MONOS transistor is
For example, “Guide-lines on Flash Memory Cell Selecti
on, '98 SSDM Hiroshima, P138-P139, Yoshikawa "(prior art 3).

[0006]

However, in the above-mentioned prior art 2, since hot holes generated by BTBT are injected at the time of erasing, there is a concern that the quality of the bottom insulating film of the ONO film may be deteriorated at the time of the hole injection. Is done.

Further, when information is stored by BTBT in a p-channel type memory transistor as in prior art 1, or 2 bits / cell information is stored in a p-channel type memory transistor as in prior art 3. In such a case, if electrons are locally injected into one or both of the source side and the drain side of the p-channel type memory transistor, there is a problem that the reading cannot be performed for the following reason.

In the prior arts 1 and 3, in the n-type impurity region (channel forming region) between the source impurity region and the drain impurity region, an end portion above which electrons are accumulated may be of a depletion type. The end of the depletion-type channel formation region is in an on state in which current flows when no bias is applied. At the time of reading, a drain voltage is applied between the source and the drain such that this end side is a source impurity region and the other is a drain impurity region.

When reading "1" storage in which electrons are stored in the source impurity region side, when the gate voltage is changed from 0 V to the negative side, the source side in the channel formation region where electrons are stored is already turned on. Therefore, the memory transistor is turned on only after the inversion layer is formed in the center of the channel formation region where electrons are not held above. On the other hand, in the case of “0” storage in which no electrons are stored on the source side according to the information to be read, the memory transistor is turned on according to the threshold voltage of the entire channel formation region. However, in the case of "1" storage, since the source side is turned on without bias, a threshold voltage difference cannot be obtained from that of "0" storage.

In the two-bit / cell storage of the prior art 3, the other storage information is read out by applying a drain voltage so that the source impurity region and the drain impurity region are reversed. A sufficient threshold voltage difference cannot be obtained between "0" storage and "1" storage. As described above, in the case where information is stored by locally accumulating electrons in the p-channel type memory transistor, it is impossible to read out the stored information on one side and reliably read out 2 bits / cell.

An object of the present invention is to provide a p-channel type memory transistor which basically operates by accumulating electric charges in a charge accumulating means such as a carrier trap or the like which is discretely planarized such as a MONOS type. It is an object of the present invention to provide a method of operating a nonvolatile semiconductor memory device capable of reliably reading stored information while minimizing film quality deterioration.

[0012]

According to the present invention, there is provided a method of operating a nonvolatile semiconductor memory device, comprising: a channel forming region formed of an n-type semiconductor; and a source / drain region formed of a p-type semiconductor and sandwiching the channel forming region. A gate insulating film provided on the channel forming region; a gate electrode provided on the gate insulating film; and a gate insulating film which is discretized in a plane facing the channel forming region and in a film thickness direction. A method of operating a nonvolatile semiconductor memory device having a charge storage means formed in a film, comprising: forming a channel in the channel formation region; and accelerating an electric field in the channel to generate hot holes. To generate hot electrons due to the interband tunnel current on the source / drain region side. By injecting Tron to the charge storage means holes are held erasing.

At the time of writing, preferably, a hot hole is injected into a part of the distribution region of the charge storage means in the gate insulating film on the drain side in accordance with information to be stored. In the case of 2-bit / cell storage, preferably, the voltage is applied twice between the source and the drain, and the distribution of the charge storage means in the gate insulating film is performed in accordance with the information to be stored. Hot holes are independently injected at one end and the other end with a central region into which hot holes are not injected.

On the other hand, if the channel length is shortened, hot holes are injected into almost the entire distribution region of the charge storage means, so that 1 bit / cell storage is performed. In this case, the above 2
The length of the channel forming region between the two source / drain regions is equal to or less than the length at which the hot holes are injected into substantially the entire distribution region of the charge storage means facing the channel forming region during the writing. At the time of this 1-bit / cell storage writing, hot holes are injected into the charge storage means from the entire surface of the channel formation region using FN tunneling. Alternatively, writing can be performed using a so-called substrate hot hole. In this case, the nonvolatile semiconductor memory device further has an n-well made of an n-type semiconductor and a p-well made of a p-type semiconductor and having the channel formation region and the two source / drain regions formed therein. Sometimes the n-well and the p
A forward bias voltage is applied to the pn junction between the wells to inject hot holes, which are minority carriers, into the n-wells. The hot holes are accelerated by an electric field between the n-well and the p-type channel formation region, and Inject into the storage means. At the time of erasing, it is preferable to inject hot electrons caused by the interband tunnel current from both of the two source / drain regions into the charge storage means.
If hot electrons can be injected from almost one side to almost the entire distribution region of the charge storage means, the erasing may be performed by that method.

In the present invention, a writing method for injecting channel hot holes from the source side is also possible. In this case, the gate electrode has a memory gate electrode on the storage region of the gate insulating film into which hot holes are injected at the time of writing, and a control gate electrode on another region of the gate insulating film into which hot holes are not injected. And controlling the voltage applied to the memory gate electrode and the control gate electrode during writing to inject hot holes into the storage area from the source side.

The gate insulating film structure according to the present invention includes:
In addition to the so-called MONOS type, MNOS type and nanocrystalline type, a film using a high dielectric material other than a nitride film such as Ta ₂ O ₃ as a film having a charge storage function, or a film having a charge storage function is formed as a channel. There is one provided directly on a semiconductor serving as a region. In the case of the MONOS type and the MNOS type, the gate insulating film includes a bottom insulating film over the channel formation region and a nitride film or an oxynitride film over the bottom insulating film. In the case of the nanocrystal type, the gate insulating film includes a bottom insulating film on the channel formation region and a small-diameter conductor formed on the bottom insulating film and insulated from each other as the charge storage means. When a material other than a nitride film is used as the film having the charge storage function, the gate insulating film has a first insulating film having a band gap larger than a semiconductor material forming the channel formation region;
And a second insulating film having a smaller band gap than the first insulating film and including a trap as the charge storage means therein. When a film having a charge storage function is directly attached on the channel formation region, the gate insulating film is formed on the channel formation region, and includes a charge holding film including a trap as the charge storage means therein; And an insulating film on the holding film.

In such an operation method of the nonvolatile semiconductor memory device, since a hot hole is injected into the charge storage means in the gate insulating film to perform writing, even if the charge storage region is local. , The portion of the channel forming region thereunder is not depleted. Therefore, the threshold voltages of “1” storage and “0” storage are higher than the thresholds of the channel formation region other than the charge accumulation region, and reading is easy. Also, in the case of 2-bit / cell storage, binary information is reliably read by two readings with the voltage application directions of the source and the drain reversed. In the writing in the present invention, hot hole injection is used. However, since the so-called channel hot hole injection, hot hole injection by FN tunneling of the entire channel, or substrate hot hole injection, the energy of holes is small. Therefore, in the writing in the present invention, the film quality of the bottom insulating film does not deteriorate as much as the hot hole injection caused by the interband tunnel current.

[0018]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, an embodiment of the present invention will be described with reference to an MO.
An example in which the present invention is applied to a memory cell including a NOS type memory transistor will be described with reference to the drawings.
FIG. 1 is a sectional view showing a basic structure of a memory transistor. This memory transistor has an n-type semiconductor substrate or an n-type semiconductor layer (for example, n-well,
n-type SOI layer). Hereinafter, this n
The type semiconductor is simply referred to as a substrate SUB. Two source / drain regions S / D to which a p-type impurity is added are formed separately from each other in a surface region in the substrate SUB. The substrate surface region between the two source / drain regions S / D becomes a channel formation region of the memory transistor.

The gate insulating film 10 is formed on the channel formation region.
Is formed, and a gate electrode G is formed on the gate insulating film 10. The gate electrode G is made of doped polysilicon (doped pol) by introducing metal and n-type impurities at a high concentration.
y-Si) or a laminated film of doped poly-Si and refractory metal silicide.

The gate insulating film 10 is composed of a bottom insulating film 11, a nitride film 12, and a top insulating film 13 in order from the lower layer. The bottom insulating film 11 is formed, for example, by forming a silicon oxide film, and nitriding the silicon oxide film as necessary.
The thickness of the bottom insulating film 11 is, for example, 1 nm to 10 n.
m.

The nitride film 12 has a thickness of, for example, 2-3 nm to 1 nm.
It is made of a film of silicon nitride SiN _x (x> 0) or silicon oxynitride SiO _x N _y (x, y> 0) of about 0 nm. This nitride film 12
Is manufactured by, for example, low pressure CVD (LP-CVD), and the film contains many carrier traps. The nitride film 12 has a Frenkel pool type (FP type) electric conduction characteristic. Note that, in the present invention, instead of the nitride film 12, another insulating film having a charge storage trap, for example, Ta ₂ O ₃
You can choose the membrane. The conditions for the bottom insulating film 11 and the nitride film 12 (or another insulating film) are as follows: the bottom insulating film 11 has a larger band gap than the substrate SUB;
The nitride film 12 (or another insulating film) has a smaller band gap than the bottom insulating film 11 and has a charge storage capability.

The top insulating film 13 needs to form deep carrier traps near the interface with the nitride film 12 at a high density, and is therefore formed by, for example, thermally oxidizing the nitride film after film formation. The top insulating film 13 is made of HTO (High Temperatu
It may be a SiO ₂ film formed by a re-chemical vapor deposition (Oxide) method. When the top insulating film 13 is formed by CVD, this trap is formed by heat treatment. The thickness of the top insulating film 13 is required to be at least 3.0 nm, preferably at least 3.5 nm, in order to effectively prevent injection of holes from the gate electrode G and to prevent a reduction in the number of times data can be rewritten. It is.

In manufacturing a memory transistor having such a configuration, first, an element isolation insulating layer and the like are formed on the prepared substrate SUB as necessary, and then ion implantation for adjusting the threshold voltage is performed as necessary. And so on.

Next, a gate insulating film 10 is formed on the semiconductor substrate SUB. Specifically, for example, a silicon oxide film (bottom insulating film 1) is formed by a short-time high-temperature heat treatment method (RTO method).
Form 1). Also, if necessary, the surface or the entire surface of the silicon oxide film is thermally nitrided. Next, the bottom insulating film 11
A silicon nitride film or a silicon oxynitride film (nitride film 12) is deposited thereon by LP-CVD so as to be thicker than the final film thickness.
In the formation of the nitride film 12, for example, monosilane (S
iH ₄ ), dichlorosilane (SiCl ₂ H ₂ ), trichlorosilane (SiCl ₃ H), tetrachlorosilane (S
A CVD method using a gas containing Si such as iCl ₄ ) and a gas containing nitrogen atoms (and a gas containing oxygen atoms) such as N ₂ or NH ₃ as raw materials is used. The surface of the formed silicon nitride film is oxidized by a thermal oxidation method to form, for example, a 3.5-nm-thick silicon oxide film (top insulating film 13). Thereby, a deep carrier trap having a trap level (energy difference from the conduction band of the nitride film) of about 2.0 eV or less is formed at a density of about 1 × 10 ¹⁸ to 1 × 10 ¹⁹ / cm ² . A thermal silicon oxide film (top insulating film 13) is formed at 1.62 nm with respect to the nitride film 12 having a thickness of 1 nm. At this ratio, the thickness of the underlying nitride film is reduced, and the nitride film 12 has a desired final film thickness.

A laminated film of a conductive film serving as the gate electrode G and an offset insulating layer (not shown) is laminated, and this laminated film is processed at once by the same pattern. Using this gate electrode pattern as a mask, p-type impurity regions are ion-implanted to form source / drain regions S / D. The source
The drain region S / D is formed by ion implantation using the gate electrode G as a mask and ion implantation using the sidewall formed on the side surface of the gate electrode G as a mask.
It may be structured. Thereafter, although not shown, the memory transistor is completed through various steps such as formation of an interlayer insulating film, formation of a contact hole, and formation of a source / drain electrode.

FIG. 2 shows a write operation of the memory transistor according to the first embodiment, and FIG. 3 shows an erase operation. Also,
FIG. 4 shows a list of bias voltage application conditions during writing and erasing. At the time of writing, the substrate SUB and various wells are held at 0 V, a source voltage Vs of 0 V is applied to one of the two source / drain regions S / D, and a drain voltage Vd of -3 V to -5 V is applied to the other, A gate voltage Vg of −5 V to −10 V is applied to the gate electrode G.
Thus, an inversion layer (channel Ch) is formed on the surface of the channel formation region, and holes are supplied from the source in the channel Ch and accelerated by the drain voltage. This hole receives energy from the accelerating electric field and becomes a hot hole near the drain end. A part of the hot hole exceeds the energy barrier of the bottom insulating film 11, is attracted by the electric field of the gate electrode G, and is injected into the carrier trap distributed around the nitride film 12.

In this channel hot hole (CHH) injection, since the generation of high energy charges (hot holes) is biased toward the drain side, the distribution area of the charge storage means (carrier trap) centered on the nitride film 12 is reduced. Hot holes are injected into the part. Therefore, writing at 2 bits / cell is possible. In this case, the above-described writing is performed again by exchanging the source / drain region S / D to which the drain voltage Vd and the source voltage Vs are applied. As a result, 2-bit information can be independently written at both ends of the carrier trap distribution region. When hot holes are injected into both ends of the carrier trap distribution region, the region between them remains as a region into which hot holes are not injected. By adjusting the amount of injected charge with respect to the effective gate length, if the length of the intermediate region where hot holes are not injected is made sufficiently long, even if the stored information interferes with each other or the stored charge slightly diffuses at high temperature No blurring of stored information occurs.

For reading, a so-called reverse read method is used. For example, the source / drain region S / D on the side where the bit to be read is stored has a source of 0 V
Is applied, −1.5 V is applied to the other source / drain region as a drain, and −2 V is applied to the gate electrode G. When reading the other bit, the above-described voltages are applied while the source and the drain are switched. In any case, when the bit to be read is "1" and the threshold voltage is high, the memory transistor is not turned on. When the bit to be read is "0" and the threshold voltage is low, the memory transistor is turned on. As a result, the drain voltage changes.
This change in drain voltage is amplified by, for example, a sense amplifier, and the voltage after the amplification is used to store “1”,
Determine “0”.

For erasing, BBHE implantation is used. As shown in FIG. 4, the substrate SUB and various wells are held at 0 V, and a negative voltage of -3 V to -5 V (a drain voltage Vd in FIG. ) Is applied to open the source / drain region S / D on the bit side not to be erased, and the voltage (source voltage Vs in the figure) is brought into a floating state. Further, a positive gate voltage Vg of 0 V to 5 V is applied to the gate electrode G. As a result, the surface of the p-type impurity region forming the source / drain region S / D to which the negative voltage Vd is applied is in a deep depletion state, causing avalanche breakdown, and the energy band on the surface of the p-type impurity region is sharply bent. Become. At this time, electrons tunnel from the valence band to the conduction band due to the interband tunnel effect, flow toward the p-type impurity region,
As a result, electrons are generated. The generated electrons slightly drift toward the center of the channel forming region, where the electric field is accelerated, and a part of the electrons is turned into hot electrons. This p
High-energy charges (hot electrons) generated at the end of the type impurity region are efficiently injected with little loss of kinetic energy while maintaining their momentum (direction and magnitude), and are injected into the carrier trap as charge storage means at high speed. Is done. When erasing the other bit, a negative voltage Vd is applied to the source / drain region S / D on the erase side and the other bit is left open, thereby achieving erasure by hot electron injection. When a negative voltage Vd is applied to both the two source / drain regions S / D, two bits can be erased simultaneously.

In the first embodiment, writing is performed by injecting holes into the p-type memory transistor. Therefore, after writing, the threshold voltage at the end of the channel forming region on the side holding holes is higher than that during erasing. I do. That is, the end of the channel formation region on the side holding the hole is not depleted, and the threshold voltage is higher than the threshold voltage of the channel formation region on the center side not holding the hole. As a result, at the time of reading, the central channel formation region can be turned on first, and then the end of the channel formation region on the side holding holes is turned on, and finally a channel is formed. The gate voltage at the time of forming this channel varies greatly depending on the presence or absence of holes, and the threshold voltage difference (window width) between writing and erasing increases. As described above, the method of operating the nonvolatile memory according to the first embodiment solves the problem that reading cannot be performed by the conventional method of writing by injecting electrons into the p-type memory transistor. There is an advantage that bit conversion is easy.

In the BBHH method in which hot holes generated due to an interband tunnel current are injected (erasing in the prior art 2), carriers are accelerated by a high electric field generated in a short depletion layer between a substrate and a drain. High energy hot holes are generated. On the other hand, in the first embodiment, CHH injection is used for writing, and hot holes are generated even in a relatively weak accelerating electric field having a long charge acceleration distance. Not. Therefore, the CHH injection method is BBHH
Damage to the bottom insulating film 11 can be reduced as compared with the method. Therefore, there is an advantage that the charge retention characteristics and the retention characteristics are excellent and the reliability is high.

In the above description, the side with the higher threshold voltage is set to the writing state, and the side with the lower threshold voltage is set to the erasing state, but the definition may be reversed.

Second Embodiment In the second embodiment, the effective portion of the gate electrode G, that is, the length in the channel direction (effective gate length) corresponding to the distance between the source and the drain is 0.1 μm or less, for example, 80 nm.
９０90 nm. Other basic transistor configurations are the same as those in FIG. 1, and the manufacturing method is also common to the first embodiment.

The operation of single bit / cell storage will be described below in response to the shortened gate length. FIG. 5 shows a write operation of the memory transistor according to the second embodiment, and FIG. 6 shows an erase operation. FIG. 7 shows a list of bias voltage application conditions during writing and erasing. At the time of writing, both the substrate SUB, various wells, and the two source / drain regions S / D are held at 0 V, and a gate voltage Vg of −5 V to −10 V is applied to the gate electrode G. As a result, holes are injected from the entire surface of the channel formation region into the carrier trap distributed around the nitride film 12 by FN tunneling.

In the hot hole injection using the FN tunneling on the entire surface of the channel, holes are easily injected almost all over the distribution region of the carrier trap, and as a result, the threshold voltage is greatly increased.

In reading, the source / drain region S /
0V is applied to one (source) of D and the other (drain)
, And −2 V is applied to the gate electrode G. When holes are injected and the threshold voltage is high, the memory transistor does not turn on. When holes are not injected and the threshold voltage is low, the memory transistor turns on and the drain voltage changes. The change in the drain voltage is amplified by, for example, a sense amplifier, and “1” or “0” of the storage bit is determined based on the amplified voltage.

For erasing, BBHE implantation is used. When holes are injected substantially all over the carrier trap distribution region, it is desirable to perform BBHE injection from both of the two source / drain regions S / D as shown in FIG. That is, the substrate SUB and various wells are held at 0 V, and the two source / drain regions S / D are -3V to -V.
A negative voltage Vd of 5 V is applied, and 0 V to 5 V is applied to the gate electrode G.
Is applied. Thereby, on the same principle as in the first embodiment, the electrons due to the band-to-band tunnel effect become hot electrons and are injected into the carrier trap as the charge storage means. The gate length is short,
If erasing is possible by BBHE injection from one side, one of the source / drain regions S / D may be opened and the voltage thereof may be in a floating state.

FIG. 8 shows another writing method according to the second embodiment. In this writing, a so-called substrate hot hole is used. In order to generate a substrate hot hole, a pn junction deep in the substrate is required. In this nonvolatile memory, a p-type impurity is added to the
W is formed, an n-type impurity is added to a part of the p-well PW to form an n-well NW, and a memory transistor is formed in the n-well NW. Another configuration is shown in FIG.
This is the same as in FIG. In a state where the channel forming region in the n-well NW is depleted by the substrate bias and a predetermined negative voltage is applied to the gate electrode G, the two wells PW, N
Forward bias the pn junction between W. As a result, holes are supplied to the depleted channel forming region, and the holes are electric field accelerated toward the gate electrode to become hot holes, which are injected into carrier traps distributed around the nitride film 12. As a result, hot holes are easily injected into almost the entire distribution region of the carrier trap, and the threshold voltage of the memory transistor is greatly increased.

In the second embodiment, storage of 2 bits / cell is not possible, but since hole injection writing is used for a p-channel transistor, the channel formation region does not become depleted, and the threshold voltage is reduced. The window width can be made sufficiently large. Therefore, there is an advantage that reading is easier than in the conventional method of writing by injecting electrons into the p-type memory transistor. In addition, since the substrate hot hole injection is used for writing, the BBHH method of injecting a hot hole generated due to an inter-band tunnel current (erasing of prior art 2)
As compared with, damage to the bottom insulating film 11 can be reduced. Therefore, there is an advantage that the charge retention characteristics and the retention characteristics are excellent and the reliability is high.

In the above description, the side with the higher threshold voltage is the writing state, and the side with the lower threshold voltage is the erasing state. However, the opposite definition may be used.

Third Embodiment In the third embodiment, writing is performed using CHH injection from the source side. FIG. 9 shows a state at the time of writing to the memory transistor according to the third embodiment.

This memory transistor has a channel forming region portion on the drain side and a source / drain region S / D.
1, a gate insulating film 10 having a three-layer structure composed of a bottom insulating film 11, a nitride film 12, and a top insulating film 13 is formed as in FIG. A single-layer insulating film 14 having no charge storage capability is formed on the upper part of the substrate. This single-layer insulating film 14 can be made of the same material and the same thickness as the bottom insulating film 11, but is preferably formed of a different film in order to adjust the dominance of the gate electrode G over the channel. Although the gate electrode G is shared in FIG. 9, a control gate electrode is provided on the source side, and a memory gate electrode which is insulated and separated from the control gate electrode is formed on the gate insulating film 10 having charge storage capability. May be provided. In either configuration, a control transistor that mainly controls the channel and a memory transistor that controls hot hole injection have a memory cell structure in which they are connected in series on an equivalent circuit.

This memory transistor is basically written by CHH injection similar to the first embodiment.
However, in the third embodiment, the conductance of the channel is arbitrarily adjusted by changing the material and thickness of the single-layer insulating film 14 or by changing the voltage applied to each gate of the control transistor and the memory transistor. it can. As a result, a high potential gradient is generated near the boundary between the control transistor and the memory transistor, and hot holes can be injected into the carrier traps distributed around the nitride film 12 with higher efficiency. Therefore, the writing speed is improved. When the gates of the control transistor and the memory transistor are separated from each other, it is possible to change the hot hole injection position in the nitride film 12 by controlling the voltage applied to each gate electrode and the gate length.

Reading and erasing are performed in the same manner as in the first and second embodiments.

Also in the third embodiment, the same advantages as those of the first and second embodiments, that is, since the hole injection writing is performed, the threshold voltage window width is large and reading is easy, and the third embodiment has the same advantages as the first embodiment. Since CHH implantation is used, there is an advantage that damage to the bottom insulating film is reduced.

In the present invention, the structure of the memory transistor is not limited to the MONOS type. For example, in FIG.
The top insulating film 13 may be omitted, and the thickness of the nitride film 12 may be increased, so that a so-called MNOS type may be used. Further, a film having a charge storage capability, for example, a silicon nitride film, a silicon oxynitride film, Ta ₂ O
₃ may be in direct contact with a semiconductor serving as a channel forming region, and a film having the same function as the top insulating film 13 in FIG. 1, for example, a gate insulating film structure formed with a thermal silicon oxide film may be used. Further, a conductive material such as polysilicon having a diameter of several nm is dispersed and formed on the bottom insulating film 11,
This may be buried in a silicon oxide film and used as a discretized charge storage means, that is, a so-called nano-crystal type, or polysilicon may be processed and separated by a fine lithography technique using an electron beam. It can also be embedded in a silicon oxide film and used as a discretized charge storage means.

[0047]

According to the method of operating a nonvolatile semiconductor memory device according to the present invention, it is possible to reliably read out stored information from a p-channel type memory transistor while minimizing deterioration of the insulating film due to hole injection. Became possible.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view showing a basic structure of a MONOS type memory transistor according to an embodiment.

FIG. 2 is a diagram illustrating a state of writing in a memory transistor according to the first embodiment.

FIG. 3 is a diagram showing a state when erasing a memory transistor according to the first embodiment;

FIG. 4 is a table showing a bias voltage application condition at the time of writing and erasing of the memory transistor according to the first embodiment.

FIG. 5 is a diagram illustrating a write operation of a memory transistor according to a second embodiment.

FIG. 6 is a diagram illustrating a state of erasing a memory transistor according to a second embodiment.

FIG. 7 is a table showing a bias voltage application condition during writing and erasing of a memory transistor according to a second embodiment.

FIG. 8 is a diagram illustrating another writing method of the memory transistor according to the second embodiment.

FIG. 9 is a diagram showing a state of writing into a memory transistor according to a third embodiment.

[Explanation of symbols]

10 gate insulating film, 11 bottom insulating film, 12 nitride film, 13 top insulating film, 14 single-layer insulating film, SUB
... substrate, PW ... p well, NW ... n well, S / D ... source / drain region, G ... gate electrode, Vs ... source voltage, Vd ... drain voltage, Vg ... gate voltage.

 ──────────────────────────────────────────────────続 き Continued on front page F-term (reference) BE07 BF03

Claims (12)

[Claims] 1. A channel forming region made of an n-type semiconductor, two source / drain regions made of a p-type semiconductor and sandwiching the channel forming region, a gate insulating film provided on the channel forming region, and the gate A nonvolatile semiconductor memory device comprising: a gate electrode provided on an insulating film; and charge storage means formed in the gate insulating film in a plane opposed to the channel forming region and in the film thickness direction. An operation method, wherein a channel is formed in the channel formation region, hot holes generated by accelerating an electric field in the channel are injected into the charge storage means to perform writing, and a band-to-band tunnel is formed in the source / drain region. Hot electrons generated by the current are generated, and the hot electrons are injected into the charge storage means holding holes to extinguish them. Method of operating a nonvolatile semiconductor memory device that performs. 2. In writing, according to information to be stored,
2. A hot hole is injected into a part of the distribution region of the charge storage means in the gate insulating film on a drain side.
The operation method of the nonvolatile semiconductor memory device described in the above. 3. The method according to claim 2, wherein the writing is performed twice with the voltage application direction between the source and the drain reversed.
3. The non-volatile semiconductor memory device according to claim 2, wherein hot holes are independently injected into one end and the other end of the gate insulating film with respect to a central region of the distribution region of the charge storage means where the hot hole is not injected. How it works. 4. The hot hole is injected into substantially the entire distribution region of the charge storage means facing the channel formation region during the writing when the length of the channel formation region between the two source / drain regions is set. The method according to claim 1, wherein the length is less than or equal to the length. 5. The operating method of a nonvolatile semiconductor memory device according to claim 4, wherein at the time of writing, hot holes are injected into said charge storage means from the entire surface of said channel formation region using FN tunneling. 6. The non-volatile semiconductor memory device according to claim 1, wherein the n-well comprises an n-type semiconductor;
And a p-well in which two source / drain regions are formed. During writing, a bias voltage is applied to a pn junction between the n-well and the p-well to generate a hot hole, and the hot hole is charged with the electric charge. 5. The method according to claim 4, wherein the liquid is injected into the storage means.
The operation method of the nonvolatile semiconductor memory device described in the above. 7. An erase operation wherein hot electrons resulting from the interband tunnel current are injected into the charge storage means from both of the two source / drain regions.
The operation method of the nonvolatile semiconductor memory device described in the above. 8. A memory gate electrode on a storage region of the gate insulating film into which hot holes are injected at the time of writing, and a control gate on another region of the gate insulating film into which hot holes are not injected. 3. The non-volatile semiconductor memory device according to claim 2, further comprising an electrode, wherein a hot hole is injected from a source side into the storage region by controlling a voltage applied to the memory gate electrode and the control gate electrode during writing. How it works. 9. The method of operating a nonvolatile semiconductor memory device according to claim 1, wherein said gate insulating film includes a bottom insulating film on said channel formation region, and a nitride film or an oxynitride film on said bottom insulating film. . 10. The gate insulating film includes a bottom insulating film on the channel formation region, and a small-diameter conductor formed on the bottom insulating film and insulated from each other as the charge storage means. Operating method of the non-volatile semiconductor memory device. 11. The first insulating film having a band gap larger than a semiconductor material forming the channel formation region, the gate insulating film being formed on the first insulating film, wherein the first insulating film is formed on the first insulating film. And a second insulating film having a smaller band gap than the film and including a trap as the charge storage means therein.
The operation method of the nonvolatile semiconductor memory device described in the above. 12. A charge holding film formed on the channel formation region, having a larger band gap than a semiconductor material forming the channel formation region, and including a trap as the charge storage means therein. The nonvolatile semiconductor memory device according to claim 1, further comprising: an insulating film on the charge holding film.