JP2005228763A - Memory element and manufacturing method thereof - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a memory element in which a manufacturing cost can be reduced markedly, without the need for using expensive materials, read-out of data is non-destructive, and a cell area can be made small, and which can cope to future scalings over a long period. <P>SOLUTION: A layer structure is obtained, by sequentially laminating a charge barrier layer 2, a charge transfer layer 3, and a gate electrode 4 on a semiconductor layer 1. The charge barrier layer 2 has defect density lower than the defect density in the charge moving layer 3 and has a barrier larger than that of the charge transfer layer 3. The charge in the charge transfer layer 3 is moved, by applying a voltage between the gate electrode 4 and the semiconductor layer 1. Charging of polarity opposite to that of the voltage applied to the gate electrode 4 is stored to the side of the gate electrode 4 in the charge transfer layer 3, and the charge of the same polarity as the voltage applied to the gate electrode 4 is stored on the side of the semiconductor layer 1 in the charge transfer layer 3, thereby changing the threshold of a MIS transistor. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a MOS (metal-oxide-semiconductor) type or MIS (metal-insulator-semiconductor) type memory element and a method for manufacturing the same.

  The memory element of the present invention is different in operation principle from a conventionally proposed memory element. As far as the present inventors know, there is no prior art of a memory element based on the same operation principle as the memory element of the present invention.

Therefore, first, a charge storage memory element having a structure similar to that of the memory element of the present invention will be described. The charge storage memory element has a film configuration shown in FIG. 18 and includes at least a semiconductor layer 100, a first charge barrier layer 101, a charge storage layer 102, a second charge barrier layer 103, a gate electrode 104, a source 105, And a drain 106. Currently, a floating gate type charge storage memory element using polysilicon for the charge storage layer 102 is in practical use, and the first and second barrier layers 101 and 103 are SiO ₂ films. Polysilicon is made conductive to form a floating gate. A voltage is applied between the semiconductor layer 100 and the gate electrode 104, a charge is injected from the semiconductor layer 100 to the gate electrode 104 through the first barrier layer 101, and the charge is stored in the charge storage layer 102. Information is stored by changing the threshold.

  This type of storage element retains the charge stored in the charge storage layer 102 for 10 years or more in order to store information for 10 years or more. Therefore, the first and second barrier layers 101 and 103 need to be excellent in electrical insulation, and should not be conductive to a weak electric field. Injecting or extracting charges into the charge storage layer 102 (that is, writing or erasing information) increases the voltage applied between the semiconductor layer 100 and the gate electrode 104 and causes the Fowler to flow through the first barrier layer 101 by a strong electric field. -It is carried out by a Nordic (Fowler-Nordheim) type (FN type) tunneling current or other conduction mechanism appearing under a strong electric field. At this time, the second barrier layer 103 is thicker than the first barrier layer 101 so that no current flows through the second barrier layer 103.

Reading of information is performed depending on whether or not a current flows when a voltage is applied to the gate electrode 104 of the MOS transistor whose threshold value has changed due to charge accumulation and a voltage is applied between the source and drain. This read operation is almost the same as that of a normal MOS transistor. However, since the charge barrier layer and the charge storage layer are thick, it is necessary to apply a high gate voltage. Further, the floating gate type accumulates charges in conductive polysilicon, and the charge retention depends on the insulating performance of the first barrier layer 101. Therefore, in the floating gate type, it is difficult to make the first barrier layer 101 thin ( _{7 to 8} nm with a SiO ₂ film), and therefore, a low voltage for writing / erasing (currently 10 to 20 V) is also a limit. Has reached. Therefore, an example using polyacetylene (see, for example, Patent Document 1) or the like has been proposed in order to accumulate a large amount of charge in the floating gate.

In addition to the floating gate type, the charge storage type memory includes an insulating film trap type that traps charges at localized levels where defects are generated. In the insulating film trap type, a SiN film or an Al ₂ O ₃ film is used for the charge storage layer 102, and these include a MONOS (metal oxide nitride oxide sillicon) type, an NROM (multi-bit type) type, or a SONOS type. There are types such as (silicon oxide nitride oxide sillcon) type (for example, see Non-Patent Document 1). The insulating trap type has been energetically researched and developed for future capacity expansion. In the insulating film trap type, electric charges are trapped at localized levels created by defects in the insulating film. Therefore, even if the first barrier layer 101 is locally conductive due to defects or the like, the local area near the defects is The charges trapped at the level only escape, not all the charges in the charge storage layer 102 escape, and the insulating requirements of the first barrier layer 101 are relaxed compared to the floating gate type. . Therefore, in the charge trap type, the first barrier layer 101 can be made thin enough to allow carriers to tunnel, and the voltage for writing, reading, and erasing information can be lowered.

  However, there is a limit to the insulating film trap type. That is, in the insulating film trap type, it is necessary to trap charges in the deep localized levels of the insulating film and suppress conduction between the traps, so that the trap space density cannot be increased. The distance between traps is considered to be 5 nm or more. Therefore, in order to trap the amount of charge necessary to change the threshold value of the transistor, a relatively large volume is required for the insulating film. Therefore, there is a limit to miniaturization of elements, and there is a limit to lowering the voltage.

  Next, DRAM (dynamic random access memory) will be described. A DRAM is generally a 1T1C type in which one transistor and one capacitor are used as one cell. Information is written by storing charge in the capacitor through the channel of the transistor. A transistor is a switch, and information is stored by storing electric charge in a capacitor. Since the charge stored in the capacitor leaks mainly through the semiconductor layer of the transistor (the pn junction between the source / drain and the substrate), it disappears in a relatively short time. Therefore, information is detected and rewritten frequently (on the order of 100 msec) to maintain information storage. In recent miniaturized cells, a 5-10 μm deep trench (deep trench) is dug in a silicon substrate, an oxide film is grown on the surface of the trench, the trench is then filled with polysilicon, and the silicon substrate and the polysilicon are formed. Is used as a capacitor.

Recently, in order to promote further miniaturization, a cylindrical protrusion or fin is formed on the wiring to increase the area, and an insulating film and an electrode are formed on the surface to form a capacitor. In future prediction (for example, see Non-Patent Document 2), an insulating film having a high dielectric constant is used, and an MIM (metal insulator metal) capacitor is formed on the wiring to secure the capacitance of the fine element. It can be said that the capacity of the DRAM is determined by how much the capacitor can be miniaturized. According to ITRS, the dielectric constant of the insulating film of the MIM capacitor in the DRAM is required to exceed 100 in the near future, and in the future, a value exceeding 1000 is required. As a material for realizing such a high dielectric constant, a material having a perovskite crystal structure is considered. Further, expensive metals such as Pt, Ru, and Ir that promote crystallization of perovskite crystals are required for the lower and upper electrodes. The electrode has a multilayer film structure that shares functions with expensive materials, and the number of manufacturing steps is remarkably increased, so an increase in cost is inevitable.
JP-A-5-152576 Nikkei Microdevice, June 2003, pages 85-90 ITRS: International Technology Roadmap for Semiconductors, <URL> http://www.itrs.net/

  The object of the present invention is based on an operating principle different from that of the memory element, and it is not necessary to use an expensive material, so that the manufacturing cost can be drastically reduced, data reading is non-destructive, the cell area can be reduced, and the future It is an object of the present invention to provide a memory element and a method for manufacturing the same that can cope with the scaling of the device for a long time.

  A memory element according to a first aspect of the present invention has a MIS transistor structure made of a metal, an insulating film, and a semiconductor, and the insulating film functions as a charge transfer layer, and retains charges in the charge transfer layer. In addition, an electric field in the charge transfer layer caused by a voltage applied between the metal and the semiconductor moves the charge in the charge transfer layer, and a charge having a polarity opposite to the voltage applied to the metal moves in the charge transfer. A charge of the same polarity as the voltage applied to the metal is accumulated on the metal side in the layer on the semiconductor side in the charge transfer layer, thereby changing a threshold value of the MIS transistor. To do.

  According to a second aspect of the present invention, there is provided a memory element having a MIS type transistor structure comprising a metal, an insulating film, and a semiconductor, the insulating film having at least a charge transfer layer and a charge barrier layer, and a defect in the charge barrier layer. The density is less than the defect density in the charge transfer layer, and the charge barrier layer has a larger barrier to charge transfer than the charge transfer layer, the charge barrier layer is in contact with the semiconductor, and the charge transfer A layer is in contact with the metal, and a charge in the charge transfer layer is moved by an electric field generated by a voltage applied between the metal and the semiconductor, and a charge having a polarity opposite to the voltage applied to the metal A charge having the same polarity as the voltage applied to the metal is accumulated on the semiconductor side in the charge transfer layer, thereby changing a threshold value of the MIS transistor. And butterflies.

  According to a third aspect of the present invention, there is provided a memory element having a MIS transistor structure made of a metal, an insulating film, and a semiconductor, the insulating film having at least a charge transfer layer and a charge barrier layer, and a defect in the charge barrier layer. The density is less than the defect density in the charge transfer layer, and the charge barrier layer has a larger barrier to charge transfer than the charge transfer layer, the charge barrier layer is in contact with the metal, and the charge transfer A layer is in contact with the semiconductor, and the charge in the charge transfer layer is moved by an electric field generated by a voltage applied between the metal and the semiconductor, and a charge having a polarity opposite to the voltage applied to the metal A charge having the same polarity as the voltage applied to the metal is accumulated on the semiconductor side in the charge transfer layer, thereby changing a threshold value of the MIS transistor. And butterflies.

  According to a fourth aspect of the present invention, there is provided a memory element having a MIS transistor structure comprising a metal, an insulating film, and a semiconductor, wherein the insulating film includes at least a charge transfer layer and the charge transfer layer. A defect density of the first and second charge barrier layers is less than a defect density in the charge transfer layer, and the first and second charge barrier layers are resistant to charge transfer. The first charge barrier layer is in contact with the semiconductor, the second charge barrier layer is in contact with the metal, and a voltage is applied between the metal and the semiconductor. The charge in the charge transfer layer is moved in such a manner that the charge having the opposite polarity to the voltage applied to the metal has the same polarity as the voltage applied to the metal on the metal side in the charge transfer layer. Accumulate on the semiconductor side in the charge transfer layer. Characterized in that changing the threshold value of the MIS transistor by.

  According to a fifth aspect of the present invention, in the memory element according to any one of the first to fourth aspects, the charge transfer layer has a localized level created by a defect and holds a charge at the localized level. And the voltage applied between the metal and the semiconductor is moved between the localized levels by an electric field created in the charge transfer layer, and the charge having the opposite polarity to the voltage applied to the metal is The charge transfer layer accumulates on the electrode side, and charges having the same polarity as the voltage applied to the metal accumulate on the semiconductor side in the charge transfer layer.

  According to a sixth aspect of the present invention, in the memory element according to any one of the first to fourth aspects, the charge transfer layer includes a charge retention layer and a third charge barrier layer, and the charge retention layer includes: The voltage applied between the metal and the semiconductor has a structure in which the defect density is made larger than the defect density of the third charge barrier layer, the charge holding layer and the third charge barrier layer are alternately stacked. Is characterized in that the electric charge generated in the charge transfer layer moves between the charge storage layers by an electric field generated in the charge transfer layer.

  According to a seventh aspect of the present invention, in the memory element according to any one of the first to fourth aspects, the charge transfer layer includes a plurality of microconductors provided in an insulator, and the microconductor In addition, the charge is held between the metal and the semiconductor, and the charge is moved between the minute conductors by an electric field generated in the charge transfer layer by a voltage applied between the metal and the semiconductor.

  According to an eighth aspect of the present invention, in the memory element according to any one of the first to fourth aspects, the charge transfer layer is insulated in a form in which the first layer made of an insulator is separated from the microconductor. It has a structure in which second layers provided in the body are alternately stacked.

  The invention according to claim 9 is the memory element according to any one of claims 1 to 6, wherein the charge transfer layer or the charge retention layer is a metal nitride, a metal oxynitride, or a stoichiometric. It consists of any one of the metal oxides which shifted | deviated in composition.

  According to a tenth aspect of the present invention, in the memory element according to any one of the second to fourth aspects, the charge barrier layer is a metal oxynitride or a metal oxide having a stoichiometric composition. It consists of one.

  According to an eleventh aspect of the present invention, in the memory element according to the seventh or eighth aspect, the insulator in the charge transfer layer is made of a metal oxide, and the microconductor is made of a metal.

  A twelfth aspect of the present invention is the method of manufacturing a memory element according to any one of the first to fifth aspects, wherein the charge transfer layer is a metal oxide, and includes an electron cyclotron resonance plasma generating means, a rare earth element, Refraction of the metal oxide deposited by sputtering, using sputtering means having at least gas and oxygen gas supply means, a metal target, and power application means to the target. The charge transfer layer is formed as a supply amount whose refractive index is different from that of a metal oxide having a stoichiometric composition.

  A thirteenth aspect of the present invention is the method of manufacturing a memory element according to any one of the first to fifth aspects, wherein the charge transfer layer is a metal nitride, an electron cyclotron resonance plasma generating means, Using the sputtering means having at least a gas and nitrogen gas supply means, a metal target, and a power application means for the target, supplying the rare gas and the nitrogen gas and sputtering the charge transfer layer It is characterized by forming.

  The invention according to claim 14 is the method of manufacturing a memory element according to any one of claims 1 to 5, wherein the charge transfer layer is a metal oxynitride, and an electron cyclotron resonance plasma generating means; Using a sputtering means having at least a rare gas, oxygen gas and nitrogen gas supply means, a metal target, and a power application means to the target, the rare gas, the oxygen gas and the nitrogen gas are simultaneously supplied. The charge transfer layer is formed by sputtering.

  The invention according to claim 15 is the method of manufacturing a memory element according to any one of claims 2 to 5, wherein the charge transfer layer and the charge barrier layer are a metal oxide, and an electron cyclotron resonance plasma. A sputtering unit having at least a generating unit, a rare gas and oxygen gas supply unit, a metal target, and a power application unit to the target is used to supply the rare gas and supply amount of the oxygen gas. The charge barrier layer is formed as a first supply amount in which the refractive index of the metal oxide deposited by sputtering becomes the refractive index of the stoichiometric metal oxide, and the supply amount of the oxygen gas is sputtered. As the second supply amount, the refractive index of the metal oxide deposited by the above method becomes a refractive index shifted from the refractive index of the stoichiometric metal oxide. And forming a moving layer.

  The invention according to claim 16 is the method of manufacturing a memory element according to any one of claims 2 to 5, wherein the charge transfer layer is a metal nitride, and the charge barrier layer is a metal oxide. A sputtering means having at least an electron cyclotron resonance plasma generation means, a rare gas, oxygen gas and nitrogen gas supply means, a metal target, and a power application means to the target; and the rare gas and the The charge barrier layer is formed by supplying oxygen gas and sputtering, and the charge transfer layer is formed by supplying and sputtering the rare gas and nitrogen gas.

  The invention according to claim 17 is the method of manufacturing a memory element according to claim 6, wherein the charge retention layer and the third charge barrier layer in the charge transfer layer are metal oxides, and an electron cyclotron. A sputtering means having at least a resonance plasma generating means, a rare gas and oxygen gas supply means, a metal target, and a power application means to the target is used, and the supply amount of the oxygen gas is deposited by sputtering. The third charge barrier layer is formed as a first supply amount in which the refractive index of the metal oxide becomes the refractive index of a metal oxide having a stoichiometric composition, and the supply amount of the oxygen gas is deposited by sputtering. The charge retention layer is formed as a second supply amount in which the refractive index of the metal oxide has a refractive index deviated from the refractive index of the stoichiometric metal oxide. The features.

  The invention according to claim 18 is the method of manufacturing a memory element according to claim 6, wherein the charge retention layer in the charge transfer layer is a metal nitride, and the third charge barrier layer is a metal oxide. A sputtering means having at least an electron cyclotron resonance plasma generating means, a rare gas, oxygen gas and nitrogen gas supply means, a metal target, and a power application means to the target, and the rare gas And the oxygen gas is supplied and sputtered to form the third charge barrier layer, and the rare gas and the nitrogen gas are supplied to form the charge retention layer.

  The invention according to claim 19 is the method of manufacturing a memory element according to claim 6, wherein the charge retention layer in the charge transfer layer is a metal oxynitride, and the third charge barrier layer is a metal. A sputtering means which is an oxide and has at least an electron cyclotron resonance plasma generation means, a rare gas, oxygen gas and nitrogen gas supply means, a metal target, and a power application means to the target; The third charge barrier layer is formed by sputtering by supplying a gas and the oxygen gas, and then applying an electron cyclotron resonance plasma of the rare gas and the nitrogen gas without applying power to the target. The charge retention layer is formed on the surface of the third charge barrier layer by irradiating the surface of the third charge barrier layer.

The invention according to claim 20 is the method for manufacturing the memory element according to claim 2 or 4, wherein the charge barrier layer is SiO ₂ , the semiconductor is silicon, and the SiO ₂ is used as a rare gas. It is formed by irradiating the surface of the silicon with electron cyclotron resonance plasma of oxygen gas.

  The invention according to claim 21 is the method of manufacturing the memory element according to claim 7 or 8, wherein the microconductor is formed by depositing a metal film on the surface of the heated insulator. And

  The present invention is a storage element that operates on a principle different from that of a conventional memory, and uses a charge that is held and moved in a portion of a gate insulating film of a MIS transistor, so there is no need to use an expensive material, Memory manufacturing costs can be significantly reduced. Further, while the existing DRAM is composed of 1 TIC, the memory element of the present invention can obtain the function of DRAM with only 1T. Reading data from 1TIC DRAM is destructive reading, and rewriting is performed immediately after reading. However, since the memory of the present invention is nondestructive to read data, this point is also superior to 1TIC DRAM. ing. In addition, since the EOT of the gate insulating film can be reduced, the cell area can be reduced, and future scaling can be supported for a long time.

  Examples of the present invention will be described below.

  FIG. 1 shows a cross-sectional view of the basic configuration of the memory element of Example 1. A charge barrier layer 2, a charge transfer layer 3, and a gate electrode 4 are sequentially formed on the semiconductor layer 1, and a source 5 and a drain 6 are formed at both ends. FIG. 2 is a diagram for explaining the operation principle of the first embodiment, and shows a case where the semiconductor layer 1 is p-type and a positive voltage is applied to the gate electrode 4. The charge barrier layer 2 and the charge transfer layer 3 function as a gate insulating film of the MIS transistor. When a positive voltage is applied to the gate electrode 4, an inversion layer, that is, an electron which is a minority carrier, is induced on the surface of the semiconductor layer 1, and a part of the electron penetrates the charge barrier layer 2 and is injected into the charge transfer layer 3. Some of the electrons injected into the charge transfer layer 3 are trapped in the localized level. If the charges at the localized level of the charge transfer layer 3 can be moved by an electric field, the electrons are moved by the electric field. It moves to the gate electrode 4 side, and part of it moves out to the gate electrode 4. A part of the positive charge of the gate electrode 4 is injected into the charge transfer layer 3, moves toward the charge barrier layer 2 by an electric field, and is trapped at a localized level. By such a series of charge transfer, more positive charges are trapped on the semiconductor layer 1 side of the charge transfer layer 3 and more negative charges are trapped on the gate electrode 4 side.

  In the first embodiment, since no charge barrier layer is used on the gate electrode 4 side, positive charge injection / migration from the gate electrode 4 is more dominant, and a lot of positive charge is accumulated on the charge barrier layer 2 side. Will be. While these charges are held, the threshold value of the MIS transistor is lowered. That is, the transistor is turned on when the positive voltage applied to the gate electrode 4 is lower. If the amount of charge to be held is increased to some extent, the transistor can be turned on even when the gate voltage is 0V. This state corresponds to storage of information “1”. Needless to say, in order to store the information “0”, the side of the semiconductor 1 should be positive with respect to the gate electrode 4. The charge transfer and the movement of carriers in the semiconductor will be described in more detail in Experimental Example 1 described later.

  The charge transfer layer 3 needs to have a defect with an appropriate space density for trapping the charge and for moving the charge by a weak electric field. The defect creates a localized level in the band gap of the insulating film. In the case of a sparse defect density with almost no overlapping of the wave functions of the charges trapped in the localized levels, the carriers can be moved by localized excitation by thermal excitation in order for the charges to move easily in a weak electric field. Therefore, when the carrier is an electron, the depth of the localized level from the bottom of the conduction band must be extremely shallow. When there are overlapping wave functions when the localized level is deep, so-called trap-assisted tunnel conduction can move between the localized levels, so the charge movement depends on the search for the localized level and the degree of overlap. The ease is determined. Usually, a defect formed by a compound having a stoichiometric composition is considered to have a deep localized level. Therefore, it is considered that a method of causing charge tunneling by controlling the spatial density of defects is suitable. The distance at which the trapped charge wave functions overlap is considered to be about 5 nm or less, and shortening the distance corresponds to operating at a low voltage. Therefore, the memory element of the present invention is a fine element. Adaptable. The depth of the level where charges are trapped and the resistance value of the film due to charge transfer can be obtained experimentally, and the optimum electrical characteristics of the charge transfer layer 3 can be obtained.

  The charge barrier layer 2 and the charge transfer layer 3 must also function as a gate insulating film of the MIS transistor. Therefore, the threshold value should not fluctuate greatly over the long term or the electrical characteristics of the charge transfer layer 3 should not deteriorate. Generally, when a strong electric field is applied to an insulating film, the deterioration of the insulating film is fast, but with a weak electric field, the deterioration is slow. Since the charge transfer memory element of the present invention operates with a weak electric field (low gate voltage), it can be expected that the deterioration is slow.

Since the charge barrier layer 2 is an insulating film in contact with the semiconductor layer 1, it is limited to an insulating film that provides good MIS transistor characteristics. A typical material is a SiO ₂ film formed by thermal oxidation, but it may be a high dielectric constant (high-k) gate insulating film which has been actively developed in recent years. A SiO ₂ film, SiO _x N _y film, Al ₂ O ₃ film, AlO _x N _y film, HfO ₂ film, HfO _x N _y film, etc. formed by ECR sputtering are also suitable. A SiO ₂ film grown by irradiating a silicon substrate with an ECR plasma flow of Ar and O ₂ gas is also suitable. A method for forming these films will be described later. An example of actual measurement of the characteristics of the MIS diode having this film configuration will be described later.

The charge barrier layer 2 does not need to be formed thick because it is not for holding charges for a long period of time unlike the charge storage type storage element. When the charge barrier layer 2 is thickened, it is necessary to increase the gate voltage for moving charges, and the change in threshold value due to charge movement is reduced. Therefore, it is preferable that the charge barrier layer 2 has a minimum thickness. When a high-k film is used for the charge barrier layer 2, the thickness thereof will be discussed in terms of an equivalent oxide thickness (EOT). EOT is
EOT = {(dielectric constant of SiO ₂ film) ÷ (dielectric constant of high-k film)} × (dielectric constant of high-k film)
Is defined. When the high-k film is used, a larger charge transfer suppression effect can be obtained with the same EOT than the SiO ₂ film. Further, by using the thinner EOT charge barrier layer 2, the gate voltage of the transistor can be lowered.

The charge transfer layer 3 includes a Si compound SiO _x film (0 <x <2), a SiN film, and a SiO _x N _y film, an Al compound AlO _x film (0 <x <1.5), an AlN film, And AlO _x N _y film, HfO _x film of Hf compound (0 <x <2), HfN film, and HfO _x N _y film are suitable. A method for forming these films will be described later.

<Experimental example 1>
This experimental example 1 shows an experimental example in which the memory operation by the MIS diode manufactured with the same film configuration as that of the first example was confirmed. FIG. 3 is a diagram showing a schematic cross-sectional structure of the manufactured MIS diode. 51 is a semiconductor layer, 52 is a charge barrier layer, 53 is a charge transfer layer, and 54 is a gate electrode. A p-type silicon substrate having a resistivity of 3 to 5 Ωcm and a plane orientation of (100) was used for the semiconductor layer 5l. An Al ₂ O ₃ film was used for the charge barrier layer 52. Since the charge barrier layer 52 is an insulating film in contact with the semiconductor layer 51, the charge blocking layer 52 is limited to an insulating film that provides good MIS transistor characteristics. A typical material is a SiO ₂ film formed by thermal oxidation, but a high-k gate insulating film which has been actively developed in recent years may be used.

The Al ₂ O ₃ film of Experimental Example 1 is one of the high-k materials, but is a film formed by a reactive sputtering method using electron cyclotron resonance (ECR) plasma. The deposition method and basic MIS diode characteristics of the Al ₂ O ₃ film are described in, for example, the literature (Y. Jin, K. Saito, M. Shimada and T. Ono, “Using electron cyclotron resonance sputtering in the deposition of ultrathin A1. ₂ 0 ₃ gate dilectrics ", Journal of Vacuum Science & Technology B21, 942 (2003).), And Japanese Patent Application No. 2001-270029.

In Experimental Example 1, an Al ₂ O ₃ film having a thickness of 1.5 nm was deposited by metal mode deposition (deposition conditions with a reduced O ₂ flow rate) using an Al target and Ar / O ₂ gas by ECR sputtering. Subsequently, an Ar / O ₂ gas ECR plasma was irradiated onto the Al ₂ O ₃ film for 30 seconds. The outline of the deposition of the Al ₂ O ₃ film and the ECR plasma irradiation conditions is as follows.
Al ₂ O ₃ film deposition conditions;
Ar flow rate: 20 sccm, O ₂ flow rate: 5.5 sccm, microwave (2.45 GHz) power: 500 W, high frequency (13.56 MHz) power: 500 W, target: Al, no substrate heating.
ECR plasma irradiation conditions;
Ar flow rate: 20 sccm, O ₂ flow rate: 8 sccm, microwave power: 500 W, irradiation time: 20 sec.

By repeating these steps, an Al ₂ O ₃ film having a thickness of 4.5 nm was deposited to form the charge barrier layer 52. ECR plasma irradiation is considered to have an effect of reducing defects due to insufficient oxidation during film deposition at the Al ₂ O ₃ film and at the Al ₂ O ₃ / Si interface, and has been confirmed to have an effect of improving MOS characteristics. Application No. 2001-270029). Even if the ECR plasma irradiation is applied to the first 1.5 nm Al ₂ O ₃ film, the MIS interface characteristics are greatly improved. The Al ₂ O ₃ film on the silicon substrate thus formed is aged in a high vacuum, in this example 1, in a vacuum of 1 to 2 × 10 ⁻⁴ Pa at about 550 ° C. for about 3 minutes. Annealed.

Next, the gas for ECR sputtering was switched between Ar and N ₂ , and an AlN film was deposited in an amount of 6 to 12 nm with an Al target to form a charge transfer layer 53. The AlN film deposition conditions are as follows:
Ar flow rate: 20 sccm, N ₂ flow rate: 6 sccm, microwave power: 500 W, high frequency power: 500 W, no substrate heating.
It is. On top of that, Al was deposited by vacuum evaporation to form a gate electrode. Al was vacuum-deposited on the back surface of the silicon wafer to form a back electrode.

  The electrical characteristics of the MIS diode produced as described above were evaluated by high-frequency CV measurement. The characteristics are shown in FIG. In FIG. 4, the vertical axis represents the capacitance (pF) measured with a minute alternating current of 1 MHz, and the horizontal axis represents the DC bias voltage (V). In this measurement, the DC bias is swept from −2V to −3V, and subsequently turned back from −3V to + 2V. The bias sweep rate is 0.5 V / s. The measured capacitance was larger at the turnback than at the first bias sweep, resulting in a large hysteresis. The hysteresis width in the half capacity of the maximum capacity was about 0.6V.

  There are two types of hysteresis caused by such a reciprocal sweep of bias. That is, the case where the capacity of the forward path of the bias sweep is larger than the capacity of the return path (trap type) and vice versa (drift type). The trap type hysteresis is generated by trapping charges in the insulating film. On the other hand, the drift type is caused by the trapped charge moving in the insulating film.

  Hereinafter, the cause of hysteresis will be described in more detail. Hysteresis can be understood by a simple electromagnetic law of repulsion of similar charges and attraction of different charges and three states of semiconductors (accumulation, depletion, and inversion). First, the trap type hysteresis when a p-type semiconductor is used will be described. When a large positive bias is first applied to the gate electrode, an inversion layer is generated in the p-type semiconductor, and electrons which are minority carriers are induced at the insulating film / semiconductor interface. A depletion layer is formed under the inversion layer. The electrons in the inversion layer are injected into the insulating film by a strong electric field, and are captured by the localized levels created by the defects. As the bias voltage advances to the minus side, the semiconductor takes a depletion state from an inversion state, further moves to an accumulation state, induces holes that are majority carriers, and the entire semiconductor enters a p-type conduction conduction state.

  In the inversion or depletion state, the total capacitance is the capacitance of the serial connection of the insulating film capacitance and the depletion layer capacitance, so it is a small capacitance governed by the small capacitance of the depletion layer, but in the accumulation state Since the semiconductor becomes a conductor, the large capacitance inherent in the insulating film appears in the entire capacitance. At this time, if electrons are trapped in the insulating film, holes are induced in the semiconductor with a bias on the positive side due to the attractive force of the electrons and holes. When the bias approaches the negative maximum value, some of the electrons trapped in the insulating film escape from the insulating film to the semiconductor by a strong electric field, and holes induced in the semiconductor enter the insulating film by a strong electric field. And some of them neutralize the electrons. Therefore, in the return path of the bias sweep, due to the repulsion of the holes, the accumulation state is shifted to the depletion state with a more negative bias voltage, and thus trap-type hysteresis appears.

  Next, consider a case where holes are injected from the gate electrode into the charge transfer layer when a positive voltage is applied to the gate electrode. When holes accumulate in the charge transfer layer, the hysteresis has the opposite polarity to the above case, and the hysteresis in the same direction as the drift type appears. In the memory element of Example 1, since no charge barrier layer is provided between the gate electrode and the charge transfer layer, this type of charge injection is likely to occur. However, the fact that the memory element of the present invention does not operate with mere charge trapping characteristics will be clarified by experimental results to be described later.

  Next, drift type hysteresis when a p-type semiconductor is used will be described. When the charge injected into the insulating film is moved by the electric field during the bias sweep process, the direction of hysteresis is reversed. First, in the forward path of the bias sweep (positive bias), electrons injected into the insulating film are attracted by an electric field and move in the insulating film to the electrode side. It is considered that some of the moved electrons escape to the electrode. At this time, it is considered that a hole of a reverse charge is induced on the semiconductor side of the insulating film because a part of the hole is injected and moved from the gate electrode and balances with electrons of the inversion layer in the semiconductor. On the gate electrode side, it is considered that more negative charges are accumulated in a form balanced with the positive voltage of the gate electrode. If this state is maintained until the transition from depletion to accumulation, the bias voltage from depletion to accumulation is shifted to the minus side due to repulsion of holes.

  In the return path of the bias sweep, negative charges are accumulated on the semiconductor side due to the negative potential of the gate electrode. If this state is maintained until the time from the semiconductor accumulation to the depletion, the bias voltage from the accumulation to the depletion is shifted to the plus side due to the suction of electrons and holes. Such movement of the charge causes hysteresis in the direction opposite to the trap type. The memory element of the present invention utilizes this drift type hysteresis. The CV characteristic of FIG. 4 shows that this drift type hysteresis occurs.

  In order to obtain a large drift type hysteresis, the relationship between the film thicknesses of the charge barrier layer 52 and the charge transfer layer 53 is important. The larger hysteresis width is obtained when the charge transfer layer 53 is thicker than the charge barrier layer 52. The influence of the electric field repulsion / attraction force and the voltage applied to the gate electrode 54 on the carriers in the semiconductor is considered. I can understand. This is because the smaller the electric field from the gate electrode 54 and the shorter the distance between charges in the insulating film / semiconductor, the greater the influence of charges in the insulating film. In this experimental example 1, AlN films of 6 nm and 12 nm were used as the charge transfer layer 53. However, for the same maximum bias voltage, larger hysteresis was obtained at 12 nm as expected. This is evidence that charges having the opposite polarity to the charges in the vicinity of the semiconductor surface are accumulated on the semiconductor side of the charge transfer layer 53, and it can be seen that this is different from a simple charge trap type.

  Drift-type hysteresis is caused by charge injection from the gate electrode, charge retention, and charge transfer. However, when the bias sweep was delayed to about 0.2 V / s, the hysteresis width was reduced. This indicates that the charge retention is on the order of several seconds to several tens of seconds. This charge retention time is sufficient for a DRAM that performs refresh to retain stored information.

Next, characteristics that the charge barrier layer 52 and the charge transfer layer 53 should have will be described. The charge barrier layer 52 is in contact with the semiconductor layer 51, and it is necessary not to impair the characteristics of the MIS transistor. A typical film that can be used is a SiO ₂ film formed by a thermal oxidation method at a temperature of 800 ° C. or higher, but a high-k gate insulating film that has been actively researched and developed recently is also possible. .

In this Experimental Example 1, an A1 ₂ O ₃ film with few defects deposited by ECR sputtering was used. In order to further reduce the defect density, Ar / O ₂ gas ECR plasma was irradiated. Further, defects can be reduced by performing heat treatment at about 400 ° C. in an atmosphere of nitrogen gas or hydrogen gas excluding oxygen gas and moisture or in a high vacuum. This low-temperature heat treatment can reduce the density of so-called slow traps that do not appear in CV measurement at 1 MHz but appear in CV measurement at a low frequency of about 1 kHz. It is considered that the Al ₂ O ₃ film thus formed can be used as a charge barrier layer of the charge transfer memory element of the present invention.

<Experimental example 2>
As the charge barrier layer 52 in contact with the silicon substrate, use of a SiO ₂ film formed by oxidizing the silicon substrate with ECR plasma can be proposed. Hereinafter, the formation method will be described. A silicon substrate having a p-type, (100) plane orientation, and 1 to ₂ Ωcm was washed with an H ₂ SO ₄ / H ₂ O ₂ mixed solution and dilute hydrofluoric acid to make the silicon substrate surface hydrophobic by hydrogen termination. The substrate was loaded into an ECR plasma irradiation apparatus (in this experiment 2, an ECR plasma sputtering apparatus was used instead), and the substrate was not heated and irradiated with ECR plasma of Ar and O ₂ gas. ECR plasma irradiation was performed under the following conditions.
Ar flow rate: 20 sccm, O ₂ flow rate: 8 sccm, microwave power: 500 W.
By this treatment, a SiO ₂ film grows on the silicon substrate surface. FIG. 5 shows the relationship between the thickness of the SiO ₂ film measured with an ellipsometer and the ECR plasma irradiation time. The thickness of the grown SiO ₂ film has a power relationship with the irradiation time.

Next, the SiO ₂ film on the silicon substrate thus formed was heated at 400 ° C. to 800 ° C. for about 3 minutes at 1-2 × 10 ⁻⁴ Pa in high vacuum, and post-annealed. Next, Al was deposited thereon by vacuum evaporation to form a gate electrode. Al was also vacuum deposited on the back surface of the Si wafer to form a back electrode.

The electrical characteristics of the MIS diode produced as described above were evaluated by high-frequency CV measurement. FIG. 6 shows CV characteristics of a sample subjected to ECR plasma oxidation for 30 minutes. In FIG. 6, the vertical axis represents the capacitance (F / cm ² ) measured with 1 MHz minute alternating current, and the horizontal axis represents the DC bias voltage (V) swept in the order of +1, −3, and +1 V. Under any of the post-annealing conditions in the figure, the hysteresis width was 70 mV or less, and in particular, those subjected to post-annealing at 600 ° C. were 25 mV or less, indicating good MIS diode characteristics with few traps. It was found that the flat band potential indicated by the CV curve (in the vicinity of the rise of the curve in this condition) is in the vicinity of the expected value of about 0.8 to 0.9 V, and the fixed charge in the SiO ₂ film is also small. Therefore, it has been found that the ECR plasma oxidation method can provide a good charge barrier layer. When an SiO ₂ film is formed by plasma oxidation using an ECR sputtering apparatus, there is also an advantage that the charge transfer layer can be deposited as it is by ECR sputtering without breaking the vacuum.

  A schematic cross-sectional view of the memory element of Example 2 is shown in FIG. In FIG. 7, the same parts as those in FIG. In Example 2, the charge barrier layer 2 of Example 1 is removed. As the charge barrier layer 7 in Example 2, it is necessary to ensure good MIS characteristics, and therefore an insulating film with a low defect density is suitable.

  When a voltage is applied to the gate electrode 4, the charge in the charge transfer layer 7 moves as described in Embodiment 1, and the threshold value of the transistor is changed. In the second embodiment, at the same time, charges are injected from the semiconductor layer 1 or the gate electrode 4 into the charge transfer layer 7 by the tunnel effect and trapped. A part of the injected charge is associated with the charge moving through the charge transfer layer 7 and disappears. Since the moving direction of the threshold of the MIS transistor due to the trapped charge is opposite to the moving direction due to the charge movement, a storage element by charge movement can be obtained if the effect of the charge movement is better. Such an element is a case where the thickness of the charge transfer layer 7 is sufficiently thick compared to the distance of charge (approximately 3 nm or less) that can be moved by the tunnel effect in a weak electric field. In order to obtain a sufficient change in threshold value due to charge transfer, the charge transfer layer 7 is considered to have a thickness of 15 nm or more. When the charge transfer layer 7 is thickened, the gate voltage for driving the transistor must be increased. It is therefore desirable to keep the thickness to a minimum that satisfies the device requirements.

Since the memory element of Example 2 has a very simple configuration, it has a promising element structure for reducing the manufacturing cost of the element. The charge transfer layer 7 includes a Si compound SiO _x film (0 <x <2), a SiN film, and a SiO _x N _y film, an Al compound AlO _x film (0 <x <1.5), an AlN film, And AlO _x N _y film, HfO _x film of Hf compound (0 <x <2), HfN film, and HfO _x N _y film are suitable. A method for forming these films will be described later.

  A schematic cross-sectional view of the memory element of Example 3 is shown in FIG. In FIG. 8, the same parts as those in FIG. In the third embodiment, a charge barrier layer 9 is provided between the charge transfer layer 8 and the gate electrode 4. The charge barrier layer 9 suppresses charge injection from the gate electrode 4 so that charge injection mainly occurs from the semiconductor layer 1. By appropriately selecting the thickness and defect density of the charge transfer layer 8, charges having the opposite polarity to the charge of the semiconductor layer 1 can be accumulated on the semiconductor layer side of the charge transfer layer 5. The same material as that used for the charge barrier layer 2 of Example 1 is suitable for the charge barrier layer 9. As in the above example, the gate voltage of the transistor can be lowered as EOT is reduced.

  A schematic cross-sectional view of the memory element of Example 4 is shown in FIG. In FIG. 9, the same parts as those in FIG. In Example 4, the first charge barrier layer 11 was provided between the semiconductor layer 1 and the charge transfer layer 10, and the second charge barrier layer 12 was provided between the charge transfer layer 10 and the gate electrode 4. Is. The charge barrier layers 11 and 12 suppress the injection of charges into the charge transfer layer 10 due to the tunnel. It is not preferred that the charge barrier layers 11 and 12 be thick enough to completely confine the charge in the charge transfer layer 10. In such a case, charge trapping characteristics appear, and the expected drift characteristics cannot be obtained. Further, in the long term, the total charge in the charge transfer layer 10 increases or decreases, and the threshold value changes. When the charge barrier layers 11 and 12 are made of the same material, one or both of them are thinned so that a part of the charge in the charge transfer layer 10 is released. Thereby, the long-term change of the threshold can be prevented. Even when different materials are used, charge extraction is considered. As in the above example, the gate voltage of the transistor can be lowered as EOT is reduced.

  A schematic cross-sectional view of a memory element of Example 5 is shown in FIG. 10, parts that are the same as those in FIG. 1 are given the same reference numerals, and descriptions thereof are omitted. Example 5 has a charge transfer layer 15 made of a laminated film of a charge retention layer 13 and a charge barrier layer 14. By making the defect density of the charge retention layer 13 higher than that of the charge barrier layer 14, more charges are trapped in the charge retention layer 13. A metal nitride may be used for the charge retention layer 13, and a metal oxide may be used for the charge barrier layer 14. Alternatively, the charge retention layer 13 and the charge barrier layer 14 may be metal oxynitrides, and the contents of oxygen and nitrogen may be changed. That is, the charge retention layer 13 increases the nitrogen content, and the charge barrier layer 14 increases the oxygen content. In Example 5, the defect density of the charge retention layer 13 can be made larger than that of the charge transfer layer of the other examples. The charge transfer barrier depends on the material and thickness of the charge barrier layer 14. A memory element that operates at a low voltage can be obtained by thinning the charge barrier layer 14 to lower the charge transfer barrier. By appropriately adjusting the thickness of the layer in contact with the semiconductor layer 1 or the gate electrode 4 in the charge barrier layer 14, charge injection due to the tunnel can be suppressed. It should be noted that the charge transfer layers 3, 7, 8, and 10 of the first to fourth embodiments can be replaced with the charge transfer layer 15 of the fifth embodiment.

  A schematic cross-sectional view of the memory element of Example 6 is shown in FIG. In FIG. 11, the same parts as those in FIG. Example 6 has a charge transfer layer 18 in which a microconductor 16 is present in an insulator 17. The electric charges trapped in the microconductor 16 are moved to the semiconductor layer 1 side or the gate electrode 4 side by an electric field. In the case of electrons, charges are trapped in the conduction band of the microconductor 16 (although the mass of the microconductor is so small that the band levels are not continuous). Since the insulator 17 between the microconductors 16 serves as a barrier for charge transfer, the distance between the microconductors 16 and the electrical characteristics of the insulator 17 determine the size of the barrier. When the distance between the minute conductors 16 is set to a distance of several nanometers or less, the wave functions of electrons in the conduction band of the minute conductors 16 overlap each other, and the state can be moved by the tunnel. Accordingly, the charges trapped in the microconductors 16 can move between the microconductors 16 relatively easily by the electric field. The microconductor 16 in this embodiment corresponds to the defect in the above embodiment. The difference between them is that more charges than defects can be stored in one microconductor 16. A method for forming the minute conductor 16 will be described later. It should be noted that the charge transfer layers 3, 7, 8, and 10 of the first to fourth embodiments can be replaced with the charge transfer layer 18 of the sixth embodiment.

  A schematic cross-sectional view of the memory element of Example 7 is shown in FIG. In FIG. 12, the same parts as those in FIG. Example 7 has the charge transfer layer 21 in which the microconductor 19 exists in the insulator 20 in a layered manner over a plurality of layers. That is, the charge transfer layer 21 has a structure in which first layers made of an insulator and second layers provided in the insulator are alternately stacked in such a manner that the microconductors 19 are separated from each other. Similar to the sixth embodiment, the electric charges trapped in the minute conductor 19 are moved to the semiconductor layer 1 side or the gate electrode 4 side by an electric field. In the sixth embodiment, the microconductors 16 are randomly distributed in the insulator 17, whereas the microconductor 19 of the seventh embodiment is formed in a layered form. A method for forming the minute conductor 19 in a layered manner will be described later. In addition, the charge transfer layers 3, 7, 8, and 10 in the first to fourth embodiments can be replaced with the charge transfer layer 21 in the seventh embodiment.

Example 8 shows a method for forming a charge transfer layer made of a metal oxide. In Example 8, a metal oxide having a stoichiometric composition is formed using ECR sputtering. As the metal element, Al, Si, Ti, Y, Zr, La series, Hf, and Ta are suitable. By using these metal targets and depositing a metal oxide in a metal mode of ECR sputtering using Ar and O ₂ gas, a charge transfer layer can be formed. As an example, the film formation characteristics of an AlO _x film when Al is used as a target are shown in FIG. In FIG. 13, the horizontal axis represents the O ₂ flow rate (sccm), the left vertical axis represents the deposition rate (nm / min), and the right vertical axis represents the refractive index. The film forming conditions are as follows.
Ar flow rate: 20 sccm, microwave (2.45 GHz) power: 500 W, high frequency (13.56 MHz) power: 500 W, no substrate heating.
In FIG. 13, the region where the O ₂ flow rate is low and the deposition rate is high and the refractive index does not change so much is the metal mode region, and the region where the O ₂ flow rate is further reduced and the refractive index is greatly changed For convenience, the strong metal mode region and the region having a large O ₂ flow rate and a low deposition rate are referred to as an oxide mode region. The metal mode region has a high sputtering rate because the target surface is not oxidized much. When the O ₂ flow rate is increased, the target surface is oxidized and approaches the sputtering rate of A1 ₂ O ₃ , so that the deposition rate is greatly reduced. In general, the sputtering rate of a metal oxide tends to be smaller than the sputtering rate of a metal. Therefore, when a metal that forms a hard and stable oxide is used as a target, the film formation characteristics similar to those in FIG. It is done. Actually, Al, Si, Ti, Zr, Hf, and Ta are confirmed.

In the case of the ECR sputtering method, since the film formed in the metal mode region is oxidized by the ECR plasma of oxygen irradiated on the substrate surface, the refractive index measured by an ellipsometer shows almost the same value as that of the oxide mode. This indicates that a high-quality metal oxide film can be formed even in the metal mode. However, when the O ₂ flow rate is further reduced to the strong metal mode, the refractive index is remarkably increased and a large change in the film quality appears. The film deposited in that region is considered to be oxygen deficient (metal rich). Therefore, there are many defects in the film. FIG. 13 shows that the density of the defects can be controlled by changing the O ₂ flow rate. In this manner, a charge transfer layer made of a metal oxide having a stoichiometric composition can be formed.

  In order to form the charge barrier layer, the charge retention layer, and the charge transfer layer in the second to fifth embodiments (FIGS. 7 to 10) according to the difference in the stoichiometric composition of the metal oxide, A metal mode region film whose refractive index is almost the same as that of the oxide mode may be applied, and a strong metal mode region film whose refractive index changes may be applied to the charge retention layer or the charge transfer layer.

Example 9 shows a method for forming a charge transfer layer made of a metal nitride. In Example 9, metal nitride is formed using a metal target, Ar, and N ₂ gas using ECR sputtering. As the metal element, Al, Si, Ti, Y, Zr, La series, Hf, and Ta are suitable. As an example, FIG. 14 shows film formation characteristics of an AlN film when Al is used as a target. In FIG. 14, the horizontal axis represents the N ₂ flow rate (sccm), the left vertical axis represents the deposition rate (nm / min), and the right vertical axis represents the refractive index. The film forming conditions are as follows.
Ar flow rate: 20 sccm, microwave (2.45 GHz) power: 500 W, high frequency (13.56 MHz) power: 500 W, no substrate heating.
Metal nitrides tend not to form a clear boundary between metal mode and oxide mode in ECR sputtering. When the N ₂ gas flow rate is decreased, conductivity is generated in the deposited film, and the illustrated region becomes a metallic film (resistor). As shown in Experimental Example 1 described above, the AlN film is suitable for the charge transfer layer. Changes in deposition rate and refractive index with respect to the N ₂ gas flow rate are the same for other metal nitrides, and nitrides of the above elements are also considered suitable for the charge transfer layer.

Example 10 shows a method for forming a charge transfer layer made of a metal oxynitride. In Example 10, a metal oxynitride is formed using an ECR sputtering method using a metal target, Ar, O ₂ , and N ₂ gas. As the metal element, Al, Si, Ti, Y, Zr, La series, Hf, and Ta are suitable. Since metal oxynitrides have a property that they do not crystallize even at high temperatures, they are suitable for forming a source / drain region by self-aligned ion implantation and performing high-temperature activation heat treatment. For ECR sputtering, since the seldom enter N elements also in the film by adding a small amount of N ₂ gas to the mixed gas of Ar and O _2, a small amount of O ₂ gas to the mixed gas of Ar and N ₂ gas To lacquer. The composition of N and O in the film can be changed depending on the amount of O ₂ gas added.

In Example 11, when forming the charge retention layer 13 and the charge barrier layer 14 in Example 5 (FIG. 10), a metal oxide deposited on the charge barrier layer 14 by ECR sputtering is used, and the charge retention layer 13 is formed of a metal. A method for forming an oxide surface by ECR plasma nitriding will be described. As the metal oxide, a film formed in the metal mode region described in Example 8 (FIG. 13) is used. Subsequently, the gas of the ECR sputtering apparatus is switched from O ₂ to N ₂ to generate ECR plasma of Ar and N ₂ and irradiate the metal oxide surface. The ECR plasma irradiation conditions are, for example,
Ar flow rate: 20 sccm, N ₂ flow rate: 4 to 10 sccm, microwave (2.45 GHz) power: 500 W, no substrate heating, irradiation time: 30 to 120 sec.
And By this plasma irradiation, the surface of the metal oxide is nitrided to a depth of about 1.5 nm and becomes an oxynitride. If the metal oxide is formed thicker than 1.5 nm, a laminated structure of metal oxide and metal oxynitride can be formed. By repeating this, the structure of the multilayer charge transfer layer 15 of Example 5 is obtained.

  Example 12 shows an example of a method for forming the charge transfer layers 18 and 21 having the microconductors 16 and 19 of Examples 6 and 7 (FIGS. 11 and 12). It can be formed using an ECR sputtering apparatus having two metal targets 30 and 31 as shown in FIG. In FIG. 15, 32 and 33 are ECR plasma sources, 34 is a substrate holder, 35 is a substrate, and 36 is a heater. The substrate 35 is rotated to make the film thickness uniform. This type of ECR sputtering apparatus has already been commercialized (for example, NTT AFTY). The metal mentioned in Examples 8 and 9 for forming the insulating film is used for the metal target 30. The metal target 31 is made of a metal such as Pt or Au that is not easily oxidized or nitrided.

In order to form the charge transfer layer 18 of Example 6 (FIG. 11), the substrate 35 is heated to an appropriate temperature by the heater 36, and the target 30 is sputtered by Ar, O ₂ gas, and N ₂ gas. At the same time as depositing a metal oxide on 35, the target 31 is sputtered to deposit Pt or Au. Pt or Au deposited on the metal oxide migrates on the surface due to heat and coalesces and gradually increases. The migration rate of small particles is large, but the migration rate of large grown particles is slow. At the same time, since the insulating film is deposited, the particles that have grown large are covered with the insulating film. The size of the grains can be controlled by the temperature, the deposition rate of Pt and Au, and the deposition rate of the insulating film.

  In order to form the charge transfer layer 21 in Example 7 (FIG. 12), metal oxide deposition and Pt or Au deposition may be performed alternately.

  Example 13 shows a case where the charge transfer layer 21 of Example 7 (FIG. 12) is formed by an ECR sputtering apparatus having one target. After depositing the metal oxide, the metal is deposited on the oxide surface by sputtering a metal target only with Ar gas on the heated substrate. The deposited metal particles migrate on the oxide surface to form grains. A multilayer structure is obtained by repeating sputtering of oxide and metal.

  In the fourteenth embodiment, an example of a cell configuration in the case where the memory element of the present invention is used as a memory and its driving circuit will be described. The memory element of the present invention stores information by utilizing a change in the threshold value of one transistor, and can take the configuration of a one-transistor type memory cell 41 as shown in FIG. 42 is a bit line control circuit, 43 is a word line control circuit, and 44 is a sense circuit. In writing data, a write voltage is applied between the bit lines (BL1, BL2) and the word line (WL). For example, in an element using a p-type semiconductor inversion layer as a channel, the word line write voltage is positive with respect to the bit line. For example, 0V is applied to the bit lines (BL1, BL2), and + 3V is applied to the word line (WL). By this writing, a positive charge is induced on the semiconductor layer side of the charge transfer layer, and a negative charge is induced on the gate electrode side. As a result, the threshold value of the transistor moves in the negative direction as shown in FIG. 17, and the transistor is turned on even at a low gate voltage. This state is a state in which information “1” is written. Data is read by applying a read voltage to the word line (appropriate voltage considering the threshold offset voltage, and need not be applied if the offset is adjusted to 0 V), and the sense circuit 44 connected to the bit line operates the transistor. Read on / off of. When writing “0” data, the voltage of the bit line is increased with respect to the word line. For example, 0V is applied to the word line (WL), and + 3V is applied to the bit lines (BL1, BL2). The threshold value of the transistor moves in the opposite direction to the previous case, and is turned off at a low gate voltage.

  Unlike the flash memory, this memory element does not need to erase information at a high voltage all at once, and can be stored by random access. However, the threshold value of the transistor depends on the charge held in the charge transfer layer, and the charge holding time is predicted to be several seconds to several hundred seconds. Therefore, this memory is a kind of DRAM, and it is necessary to periodically refresh data. The refresh is performed by reading the data within the data holding time, reading it, and writing the same data, as in the case of the 1TIC DRAM using the existing capacitor. The existing DRAM refreshes at a cycle of several hundreds of milliseconds, but this memory has a high possibility of extending to a cycle of several seconds. The reason why the charge escape of the 1TIC type DRAM is fast is mainly due to the escape from the pn junction of the semiconductor, but in this memory, the escape from the semiconductor does not occur.

  Unlike the flash memory, this memory does not require the charge to be confined in the insulating film for a long period of time, so that the thickness of the charge barrier layer and the charge transfer layer can be reduced. It is also possible to reduce the EOT by using a high-k material having a high dielectric constant. Therefore, when the insulating film is thinned, an electric field applied to the insulating film is increased even at a low voltage, so that the writing and reading voltages can be reduced. The use of a high-k material can scale the size of the MOS transistor and miniaturize the device, so that this memory is considered to be able to cope with future scaling for a long time.

It is a schematic sectional drawing of the memory element which shows Example 1 of this invention. 2 is an explanatory diagram of an operation principle of Embodiment 1. FIG. It is a schematic sectional drawing of the MIS diode created in Experimental example 1 of this invention. It is a CV characteristic figure of the MIS diode created in Experimental example 1 of the present invention. A film forming characteristic diagram of the SiO ₂ film grown by ECR plasma irradiation. It is a MOS diode characteristic view of a SiO ₂ film grown by ECR plasma irradiation. It is a schematic sectional drawing of the memory element which shows Example 2 of this invention. It is a schematic sectional drawing of the memory element which shows Example 3 of this invention. It is a schematic sectional drawing of the memory element which shows Example 4 of this invention. It is a schematic sectional drawing of the memory element which shows Example 5 of this invention. It is a schematic sectional drawing of the memory element which shows Example 6 of this invention. It is a schematic sectional drawing of the memory element which shows Example 7 of this invention. A film forming characteristic diagram of the Al ₂ O ₃ film by ECR sputtering. It is a film-forming characteristic figure of an AlN film by ECR sputtering method. It is a schematic sectional drawing of the ECR sputtering apparatus with two ECR sources. 1 is a basic circuit diagram of a charge transfer memory according to the present invention. It is explanatory drawing which shows the threshold value shift of the charge transfer type storage element of this invention. It is a schematic sectional drawing which shows the conventional charge storage memory element (flash memory).

Explanation of symbols

1: Semiconductor layer 2: Charge barrier layer 3: Charge transfer layer 4: Gate electrode 5: Source 6: Drain 7: Charge barrier layer 8: Charge transfer layer 9: Charge barrier layer 10: Charge transfer layer 11: First charge Barrier layer 12: Second charge barrier layer 13: Charge holding layer 14: Charge barrier layer 15: Charge transfer layer 16: Microconductor 17: Insulator 18: Charge transfer layer 19: Microconductor 20: Insulator 21: Charge transfer layer 30, 31: Metal target 32, 33: ECR plasma source 34: Substrate holder 35: Substrate 36: Heater 41: Memory cell 42: Bit line control circuit 43: Word line control circuit 44: Sense circuit 51: Semiconductor Layer 52: Charge barrier layer 53: Charge transfer layer 54: Gate electrode

Claims (21)

MIS type transistor structure consisting of metal, insulating film and semiconductor,
The insulating film functions as a charge transfer layer, holds charges in the charge transfer layer, and the charges are generated by an electric field in the charge transfer layer due to a voltage applied between the metal and the semiconductor. Move through the moving bed,
Charges having the opposite polarity to the voltage applied to the metal accumulate on the metal side in the charge transfer layer, and charges of the same polarity as the voltage applied to the metal accumulate on the semiconductor side in the charge transfer layer. By changing the threshold value of the MIS transistor, a memory element is provided. MIS type transistor structure consisting of metal, insulating film and semiconductor,
The insulating film has at least a charge transfer layer and a charge barrier layer, the defect density of the charge barrier layer is less than the defect density in the charge transfer layer, and the charge barrier layer Having a larger barrier than the charge transfer layer, the charge barrier layer in contact with the semiconductor, the charge transfer layer in contact with the metal,
A charge in the charge transfer layer is moved by an electric field generated by a voltage applied between the metal and the semiconductor, and a charge having a polarity opposite to the voltage applied to the metal is present on the metal side in the charge transfer layer. The memory element is characterized in that a charge having the same polarity as the voltage applied to the metal is accumulated on the semiconductor side in the charge transfer layer, thereby changing a threshold value of the MIS transistor. MIS type transistor structure consisting of metal, insulating film and semiconductor,
The insulating film has at least a charge transfer layer and a charge barrier layer, the defect density of the charge barrier layer is less than the defect density in the charge transfer layer, and the charge barrier layer Having a larger barrier than the charge transfer layer, wherein the charge barrier layer is in contact with the metal, the charge transfer layer is in contact with the semiconductor,
A charge in the charge transfer layer is moved by an electric field generated by a voltage applied between the metal and the semiconductor, and a charge having a polarity opposite to the voltage applied to the metal is present on the metal side in the charge transfer layer. The memory element is characterized in that a charge having the same polarity as the voltage applied to the metal is accumulated on the semiconductor side in the charge transfer layer, thereby changing a threshold value of the MIS transistor. MIS type transistor structure consisting of metal, insulating film and semiconductor,
The insulating film has at least a charge transfer layer and first and second charge barrier layers sandwiching the charge transfer layer, and the defect density of the first and second charge barrier layers is in the charge transfer layer. Less than the defect density, and the first and second charge barrier layers have a larger barrier to charge transfer than the charge transfer layer; the first charge barrier layer is in contact with the semiconductor; Two charge barrier layers contact the metal;
By applying a voltage between the metal and the semiconductor, the charge in the charge transfer layer is moved, and a charge having a polarity opposite to the voltage applied to the metal is present on the metal side in the charge transfer layer. A memory element, wherein a threshold voltage of the MIS transistor is changed by accumulating charges having the same polarity as the voltage applied to a metal on the semiconductor side in the charge transfer layer. The memory element according to any one of claims 1 to 4,
The charge transfer layer has a localized level created by a defect, holds a charge at the localized level, and a voltage applied between the metal and the semiconductor is generated by an electric field generated in the charge transfer layer. Move between the localized levels,
Charges having the opposite polarity to the voltage applied to the metal accumulate on the electrode side in the charge transfer layer, and charges of the same polarity as the voltage applied to the metal accumulate on the semiconductor side in the charge transfer layer. A memory element. The memory element according to any one of claims 1 to 4,
The charge transfer layer includes a charge retention layer and a third charge barrier layer, the defect density of the charge retention layer is made larger than the defect density of the third charge barrier layer, and the charge retention layer and the first charge barrier layer 3 charge barrier layers alternately stacked,
A memory element, wherein a charge applied to the charge holding layer moves between the charge holding layers by an electric field generated in the charge transfer layer by a voltage applied between the metal and the semiconductor. The memory element according to any one of claims 1 to 4,
The charge transfer layer includes a plurality of microconductors provided in an insulator, holds charges in the microconductor, and a voltage applied between the metal and the semiconductor is generated in the charge transfer layer. A memory element, wherein the electric charge moves between the minute conductors by an electric field. The memory element according to any one of claims 1 to 4,
The memory is characterized in that the charge transfer layer has a structure in which first layers made of an insulator and second layers provided in the insulator are alternately stacked so that the microconductors are separated from each other. element. The memory element according to any one of claims 1 to 6,
The memory element, wherein the charge transfer layer or the charge retention layer is made of any one of a metal nitride, a metal oxynitride, or a metal oxide having a stoichiometric composition. The memory element according to any one of claims 2 to 4,
The memory device according to claim 1, wherein the charge barrier layer is made of one of a metal oxynitride and a metal oxide having a stoichiometric composition. The memory element according to claim 7 or 8,
The memory element according to claim 1, wherein the insulator in the charge transfer layer is made of a metal oxide, and the minute conductor is made of a metal. A method for manufacturing a memory element according to any one of claims 1 to 5,
The charge transfer layer is a metal oxide;
Using sputtering means having at least electron cyclotron resonance plasma generation means, rare gas and oxygen gas supply means, a target made of metal, and power application means to the target,
The charge transfer layer is formed by setting the supply amount of the oxygen gas to a supply amount in which the refractive index of the metal oxide deposited by sputtering is different from the refractive index of the stoichiometric metal oxide. A method for manufacturing a memory element. A method for manufacturing a memory element according to any one of claims 1 to 5,
The charge transfer layer is a metal nitride;
Using sputtering means having at least electron cyclotron resonance plasma generation means, rare gas and nitrogen gas supply means, a target made of metal, and power application means to the target,
A method of manufacturing a memory element, wherein the charge transfer layer is formed by sputtering with supplying the rare gas and the nitrogen gas. A method for manufacturing a memory element according to any one of claims 1 to 5,
The charge transfer layer is a metal oxynitride;
Using sputtering means having at least electron cyclotron resonance plasma generation means, supply means for rare gas, oxygen gas and nitrogen gas, a target made of metal, and power application means to the target,
A method for manufacturing a memory element, wherein the charge transfer layer is formed by simultaneously supplying the rare gas, the oxygen gas, and the nitrogen gas and performing sputtering. A method for manufacturing a memory element according to any one of claims 2 to 5,
The charge transfer layer and the charge barrier layer are metal oxides;
Using sputtering means having at least electron cyclotron resonance plasma generation means, rare gas and oxygen gas supply means, a target made of metal, and power application means to the target,
While supplying the rare gas,
Forming the charge barrier layer as a first supply amount in which the refractive index of the metal oxide deposited by sputtering is the refractive index of the stoichiometric metal oxide;
The charge transfer layer is used as a second supply amount in which the refractive index of the metal oxide deposited by sputtering is different from the refractive index of the stoichiometric metal oxide. A method for manufacturing a memory element, comprising: forming a memory element. A method for manufacturing a memory element according to any one of claims 2 to 5,
The charge transfer layer is a metal nitride, and the charge barrier layer is a metal oxide;
Using sputtering means having at least electron cyclotron resonance plasma generation means, supply means for rare gas, oxygen gas and nitrogen gas, a target made of metal, and power application means to the target,
The charge barrier layer is formed by supplying and sputtering the rare gas and the oxygen gas, and the charge transfer layer is formed by supplying and sputtering the rare gas and the nitrogen gas. A method for manufacturing a memory element. A method of manufacturing a memory element according to claim 6,
The charge retention layer and the third charge barrier layer in the charge transfer layer are metal oxides;
Using sputtering means having at least electron cyclotron resonance plasma generation means, rare gas and oxygen gas supply means, a target made of metal, and power application means to the target,
The third charge barrier layer is formed as a first supply amount in which the refractive index of the metal oxide deposited by sputtering is the refractive index of the stoichiometric metal oxide. ,
The charge retention layer is used as a second supply amount in which the refractive index of the metal oxide deposited by sputtering is different from the refractive index of the stoichiometric metal oxide. A method for manufacturing a memory element, comprising: forming a memory element. A method of manufacturing a memory element according to claim 6,
The charge retention layer in the charge transfer layer is a metal nitride, and the third charge barrier layer is a metal oxide;
Using sputtering means having at least electron cyclotron resonance plasma generation means, supply means for rare gas, oxygen gas and nitrogen gas, a target made of metal, and power application means to the target,
The third charge barrier layer is formed by supplying and sputtering the rare gas and the oxygen gas, and the charge retention layer is formed by supplying the rare gas and the nitrogen gas. A method for manufacturing a memory element. A method of manufacturing a memory element according to claim 6,
The charge retention layer in the charge transfer layer is a metal oxynitride, the third charge barrier layer is a metal oxide,
Using sputtering means having at least electron cyclotron resonance plasma generation means, supply means for rare gas, oxygen gas and nitrogen gas, a target made of metal, and power application means to the target,
The third charge barrier layer is formed by sputtering by supplying the rare gas and the oxygen gas, and then, an electric cyclotron resonance plasma of the rare gas and the nitrogen gas without applying power to the target. Irradiating the surface of the third charge barrier layer to form the charge retention layer on the surface of the third charge barrier layer. A method of manufacturing a memory element according to claim 2 or 4,
The charge barrier layer is SiO ₂ and the semiconductor is silicon;
A method for manufacturing a memory element, characterized in that the SiO ₂ is formed by irradiating the silicon surface with an electron cyclotron resonance plasma of a rare gas and an oxygen gas. A method of manufacturing a memory element according to claim 7 or 8,
The method for manufacturing a memory element, wherein the minute conductor is formed by depositing a metal film on the surface of the heated insulator.

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