JP2002019876A - Tray for semiconductor chip - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a tray for semiconductor chips, which prevents damages of semiconductor chips during transport and which flexibly and easily copes with variation in the sizes of chips. SOLUTION: The tray has a tray main body 1 and a chip storing frame 3. The tray main body 1 holds the chip storing frame 3 in a replaceable manner. Further, the tray main body 1 has protrusions 4 which receive corner parts 3a of the chip storing frame 3 to determine the positioning of the chip storing frame 3 on the tray main body 1.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor chip tray used for storing or transporting semiconductor chips.

[0002]

2. Description of the Related Art Conventionally, as shown in FIG. 5, a semiconductor chip tray used for storing and transporting semiconductor chips has a chip housing frame 1b made of a hard resin integrally formed on a substrate 1a made of a hard resin. The chip housing frame 1b is provided with a recess 2 for receiving a semiconductor chip.

When a semiconductor chip is stored or transported, the semiconductor chip is loaded into the recess 2 of the chip housing frame 1b and mounted on a semiconductor chip tray.

[0004]

However, in the semiconductor chip tray shown in FIG. 5, since the semiconductor chips are stored in the concave portion 2 of the hard resin, the semiconductor chip collides with the inner wall of the concave portion 2 due to vibration during transportation. There is a problem that it is lost.

A recess 2 for accommodating a semiconductor chip.
Since the internal dimensions of the semiconductor chip are determined at the time of resin processing of the tray, when the dimensions of the semiconductor chips to be stored are changed, it is necessary to prepare a resin tray in accordance with the size of the semiconductor chip each time.

In order to cope with a change in the size of the semiconductor chip, as shown in FIG. 6, the inner wall of the concave portion 2 is stepped in steps, and supporting portions 2a and 2b having different sizes are provided for each step. It is possible to cope with the problem by selecting a support portion 2a or 2b suitable for the size of the semiconductor chip and supporting the semiconductor chip on the selected support portion 2a or 2b.

However, according to the method shown in FIG. 6, the size is limited only to the number of steps of the supporting portion provided, and it is impossible to sufficiently cope with the full size of the semiconductor chip, and it is not always effective. It is not a simple means.

Further, since the support portions 2a and 2b are provided in a plurality of stages in the depth direction of the hole 2, a wasteful space is consumed in the space in the depth direction of the hole necessary for accommodating one semiconductor chip. As a result, there is a problem that the dimensions of the semiconductor chip tray are expanded, and storage, transportation and the like are hindered.

An object of the present invention is to provide a semiconductor chip tray which can prevent damage to semiconductor chips during transportation and can flexibly and easily cope with a change in chip size.

[0010]

To achieve the above object, a semiconductor chip tray according to the present invention is a semiconductor chip tray having a tray body and a chip storage frame,
The tray body holds the chip storage frame in a replaceable manner, and the chip storage frame is provided with a hole for storing a semiconductor chip, and a buffering action is provided on a side surface of the hole facing the semiconductor chip. It is a thing.

The tray main body has a convex portion, and the convex portion receives a corner of the chip storage frame and positions the chip storage frame on the tray main body.

Further, the convex portion receives a diagonal corner of the chip storage frame and fixes the semiconductor chip on the tray body.

The projections support the stacked tray bodies to secure a space for accommodating semiconductor chips between the tray bodies.

In addition, the apparatus has an upper tray, and the upper tray fixes the chip storage frame to the tray body.

The upper tray is detachably attached to the tray body.

Further, the tray main body and the chip storage frame are provided with antistatic measures.

[0017]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of the present invention will be described below with reference to the drawings.

(Embodiment 1) FIG. 1 is an exploded perspective view showing a semiconductor chip tray according to Embodiment 1 of the present invention, FIG. 2 is a perspective view showing an assembled state, and FIG. FIG.

The semiconductor chip tray according to the present invention shown in FIG. 1 has a tray body 1 and a chip storage frame 3.

The tray body 1 includes the chip storage frame 3.
The tray body 1 shown in FIG. 1 is formed by processing a hard resin into a flat plate shape.

Further, the tray body 1 has a convex portion 4 for receiving the corner 3a of the chip storage frame 3 to position the chip storage frame 3 on the tray body 1.

The protrusion 4 shown in FIG. 1 has a structure in which two side walls 4a are crossed at an angle formed by the corners 3a and 3b of the chip housing frame 3, and are raised. Part 3
a, 3b to receive the chip storage frame 3 on the tray body 1.
The projections 4 shown in FIG. 1 are provided in pairs on the diagonal line of the rectangular tray main body 1, and the corner portions 3 a and 3 b on the diagonal line of the chip storage frame 3.
And the chip storage frame 3 is fixed on the tray body 1.

The chip housing frame 3 is provided with a hole 3c for housing a semiconductor chip (not shown), and a side surface 3d of the hole 3c facing the semiconductor chip has a buffering action.

The chip housing frame 3 shown in FIG. 1 is made of a flexible resin sheet, and has a buffering effect on the side surface 3d of the hole 3c facing the semiconductor chip.

By providing a buffering effect on the side surface 3d of the hole 3c of the chip housing frame 3 facing the semiconductor chip, the semiconductor chip is prevented from being damaged when the semiconductor chip comes into contact with the chip housing frame 3. Has become. Further, by using a flexible resin for the chip housing frame 3, processing for providing the hole 3 c in the chip housing frame 3 is facilitated.

There is a problem if the hole 3c is too large or too small for the semiconductor chip. If it is too large, not only does the number of stored semiconductor chips decrease, but also the movement of the semiconductor chip in the hole 3c due to the vibration of the tray increases the impact of collision between the semiconductor chip and the hole 3c, increasing the probability of chip breakage. It is because it becomes. On the other hand, if it is too small, it becomes difficult to handle the semiconductor chip. Therefore, it is desirable to open the hole 3c so as to have a gap of about +1 mm to +2 mm between the semiconductor chip to be stored and the side wall 3d of the hole 3c.

It is desirable that the sheet-shaped chip housing frame 3 be thicker than the semiconductor chip (200 μm to 300 μm). However, if it is too thick, handling becomes difficult, so about 1 mm is appropriate. In this case, since the sheet subjected to general-purpose electrostatic processing is thin, it is difficult to configure the chip storage frame 3 with only one sheet. Therefore, it is desirable to form a chip storage frame 3 having a sufficient thickness for a semiconductor chip by stacking several electrostatic sheets.

The chip housing frame 3 may be made of a cushion material made of a foamed material for which antistatic measures are taken instead of the sheet. In this case, it is possible to improve the point that the sheet is too soft and difficult to handle. However, it is preferable that the foamed material used here does not generate waste of the foamed material even when used for a long time. This is to prevent foreign matter from attaching to the semiconductor chip.

As shown in FIG. 3, the projection 4 rises upward from the tray main body 1 and is located inside the four corners of the tray main body 1, supports the stacked tray main bodies 1, and interposes between the tray main bodies 1, 1. A space S for accommodating semiconductor chips is secured.

The lower surface 1d of the tray main body 1 is formed in a concave shape, and when the convex portion 4 of another tray main body 1 to be stacked is received at the corner of the concave lower surface 1d, the upper and lower tray main bodies 1 Is not shifted.

The tray body 1 and the chip storage frame 3 are provided with anti-static measures. By applying antistatic measures to the tray body 1 and chip storage frame 3,
The semiconductor chip is prevented from being destroyed by static electricity.

In FIG. 1, a chip storage frame 3 having a hole 3c corresponding to the size of a semiconductor chip (not shown) is selected, and the chip storage frame 3 is set on the tray body 1.

In this case, the corners 3a, 3
b is applied to the convex portion 4 to position the chip storage frame 3 on the tray body 1.

Further, diagonal corners 3 of the chip housing frame 3
The chips a and 3b are received in the protrusions 4 located on the diagonal lines, and the chip storage frame 3 is fixed to the tray body 1.

Thereafter, semiconductor chips (not shown) are put into the chip storage frame 3, mounted on the tray body 1, and the semiconductor chips are stored and transported in this state.

In the conventional example shown in FIG. 5, the semiconductor chips are housed in a tray made of only a hard resin, so that the semiconductor chips come into contact with the tray during transportation, and the corners of the semiconductor chips are damaged. Silicon chips generated by the defect may vibrate in the tray together with the semiconductor chips, and the silicon chips may secondarily damage the semiconductor chips.

However, according to the semiconductor chip tray of the present invention shown in FIG. 1, since the buffering action is given to the side wall 3d of the hole 3c facing the semiconductor chip of the chip housing frame 3, the semiconductor chip is being transported. Even when the semiconductor chip comes into contact with the tray due to vibration, it is possible to prevent corner portions of the semiconductor chip from being lost, and to prevent secondary damage due to silicon chips.

Further, in the conventional semiconductor chip tray, it is necessary to prepare a mold for each chip size when forming the resin tray according to the chip size. However, according to the present invention shown in FIG. Hole 3 corresponding to the size
In order to cope with the change in the size of the semiconductor chip by replacing the chip storage frame 3 having the hole c with the chip storage frame 3 having the hole 3c corresponding to the size, the chip storage frame 3 having the size corresponding to the size is changed for each chip size. Only the preparation is required, and the entire tray is not changed, so that the cost can be reduced economically. Further, the height of the hole 3c with respect to the semiconductor chip (the height of the concave portion in the conventional example) can be maintained at an appropriate height for the chip size.

Further, since the tray main body 1 and the chip storage frame 3 are configured separately, it is easy to recognize the partition when the trays are stacked one on top of the other, and it is also possible to prevent the semiconductor chips from being broken due to the curvature of the tray main body 1. Can be. In addition, spread a thin sheet without holes on the tray body 1,
It is possible to lay a sheet as a chip storage frame 3 having a hole 3c on the sheet.

(Embodiment 2) FIG. 4 is an exploded perspective view showing a semiconductor chip tray according to Embodiment 2 of the present invention.

The present invention shown in FIG. 4 is different from the combination of the tray body 1 and the chip storage frame 3 shown in FIG.
have.

The upper tray 5 fixes the chip storage frame 3 to the tray body 1, and the upper tray 5 is detachably attached to the tray body 1.

The upper tray 5 shown in FIG. 4 has a frame shape in which an opening 5a for inserting a semiconductor chip into all the holes 3c of the chip housing frame 3 is provided on the upper surface, and the periphery thereof is hook-shaped. The chip-shaped frame portion 5b receives the upper edge peripheral portion 3e of the chip storage frame 3, and the insertion piece 5c is inserted into the insertion hole 1e of the tray body 1, and the hook-shaped frame portion 5b is bent. The upper edge peripheral portion 3e of the chip storage frame 3 is pressed down to the tray main body 1 side, so that the chip storage frame 3 is securely fixed to the tray main body 1.

Although the insertion piece 5c shown in FIG. 4 has a tongue shape,
This may be shaped like a key claw.

In the embodiment shown in FIG.
When the tray body 1 vibrates up and down, the chip storage frame 3 may be displaced on the tray body 1 when the means for fixing the chip body to the tray body 1 is only the protrusion 4.

Therefore, in the embodiment shown in FIG. 4, the insertion piece 5c of the upper tray 5 is inserted into the insertion hole 1e of the tray main body 1, and the upper tray 5 is fixed to the tray main body 1.

When the upper tray 5 is fixed to the tray main body 1, the upper edge peripheral portion 3e of the chip storage frame 3 is pressed down by the hook-shaped frame portion 5b of the upper tray 5 toward the tray main body 1, and the chip storage frame 3 is moved. The upper, lower, left and right positions are fixed to the tray body 1.

According to the embodiment shown in FIG. 4, the chip storage frame 3 can be fixed to the tray main body 1 more reliably than the structure in which the chip storage frame 3 is fixed to the tray main body 1 in FIG.
Defects in the semiconductor chip can be more reliably prevented.

[0049]

As described above, according to the present invention, it is possible to prevent a semiconductor chip from being damaged during transportation, and to flexibly and easily cope with a change in chip size.

[Brief description of the drawings]

FIG. 1 is an exploded perspective view showing a semiconductor chip tray according to Embodiment 1 of the present invention.

FIG. 2 is a perspective view showing an assembled state.

FIG. 3 is a vertical sectional view taken along line aa of FIG. 2;

FIG. 4 is an exploded perspective view showing a semiconductor chip tray according to Embodiment 2 of the present invention.

FIG. 5 is an exploded perspective view showing a semiconductor chip tray according to a conventional example.

FIG. 6 is a vertical sectional view taken along line bb of FIG. 5 showing a semiconductor chip tray according to a conventional example.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Tray main body 3 Chip storage frame 3a, 3b Corner of chip storage frame 3c Hole of chip storage frame 4 Convex part 5 Upper tray

Claims (7)

[Claims] 1. A semiconductor chip tray having a tray main body and a chip storage frame, wherein the tray main body holds the chip storage frame in a replaceable manner, and wherein the chip storage frame stores a semiconductor chip. A semiconductor chip tray, wherein a hole for accommodating the semiconductor chip is provided, and an inner wall of the hole facing the semiconductor chip has a buffering action. 2. The method according to claim 1, wherein the tray main body has a convex portion, and the convex portion receives a corner of the chip storage frame and positions the chip storage frame on the tray main body. The semiconductor chip tray according to claim 1. 3. The semiconductor chip according to claim 2, wherein the convex portion receives a diagonal corner of the chip storage frame and fixes the semiconductor chip on the tray body. 4. The semiconductor chip tray according to claim 2, wherein the projection supports the stacked tray bodies to secure a space for accommodating semiconductor chips between the tray bodies. . 5. The semiconductor chip tray according to claim 1, further comprising an upper tray, wherein the upper tray fixes a chip storage frame to the tray body. 6. The semiconductor chip tray according to claim 5, wherein the upper tray is detachably attached to the tray body. 7. The tray main body and the chip storage frame,
2. The semiconductor chip tray according to claim 1, wherein an antistatic measure is taken.