JP2002009255A - Non-volatile semiconductor storage device - Google Patents

Abstract

(57) [Summary] [PROBLEMS] A bias applied to a ferroelectric substance during data retention is lost due to a leak current, and stored data is destroyed in a short time. SOLUTION: When the ferroelectric substance 3 is dominated by N-type conduction, a P-channel FET is formed with the silicon substrate 8 as N-type, and when the ferroelectric substance is P-type conduction, the silicon substrate 8 is formed. Is formed as a P-type to form an N-channel FET.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a nonvolatile semiconductor memory device comprising a field effect transistor (FET) using a ferroelectric capacitor for controlling a gate potential.

[0002]

2. Description of the Related Art A conventional field effect transistor (FET) having a gate provided with a ferroelectric substance has, for example, a structure as shown in FIG. Here, reference numeral 43 denotes a ferroelectric made of a metal oxide such as zircon-lead titanate (PZT) or bismuth-strontium tantalate (SBT); 44, a silicon oxide film; 40, a gate electrode;
Is a source region, 46 is a drain region, 47 is a channel,
48 is a silicon substrate.

In this configuration, the ferroelectric 43 can be polarized upward or downward, and the depth of the surface potential of the silicon substrate under the gate of the ferroelectric FET is changed by two different states in accordance with the two polarization states. It can be set to either of the states. At this time, the surface potential of the silicon substrate under the gate is equal to the source potential of the ferroelectric FET.
Since the resistance between the drains is dominant, the resistance between the source and the drain takes one of two states of a high value and a low value depending on the direction of the polarization, and this state is maintained as long as the polarization of the ferroelectric 43 is maintained ( Is memorized). Therefore, the ferroelectric FET can be applied to a nonvolatile memory device.

A conventional technique for storing and reading out two different logic states in a ferroelectric FET having such a structure is, for example, a logic "1" when the ferroelectric material 43 is polarized downward and a logic "1" when the ferroelectric material 43 is polarized upward. Is made to correspond to logic "0". To make the polarization downward, the back surface of the silicon substrate 48 is set to the ground potential, and a strong positive voltage is applied to the gate electrode 40, and to make the polarization upward, a strong negative voltage is applied. After that, the voltage of the gate electrode 40 rapidly becomes the ground potential due to the junction leak of the transistor connected to the gate electrode 40. Therefore, the data after data writing is maintained with the gate electrode 40 and the silicon substrate 48 at the same potential.

The data holding state will be described with reference to an energy band diagram shown in FIG. For example, the silicon substrate 48 is P-type, and the source region 45 and the drain region 46 are N-type. In this configuration, a positive bias is applied to the gate electrode 40, data is written in a downward polarization (state of logic "1"), and the energy band diagram after the gate electrode 40 is grounded is shown in FIG. As shown in FIG. 5, a negatively ionized depletion layer spreads deeply into the silicon substrate 48, forming an N-type conduction channel 35.
The interface potential of the silicon substrate 48 falls below the ground potential. Here, 31 is the conduction band of the gate electrode, 32, 3
3, and 34 are ferroelectrics, silicon oxide films,
And the energy band of the silicon substrate. The arrow 30 shown in FIG. 5 indicates the direction of polarization of the ferroelectric, and the broken line indicates the Fermi level. On the other hand, after writing data with the polarization upward (the state of logic "0"), as shown in FIG. 5B, holes as P-type carriers accumulate at the interface of the silicon substrate 48, and Since no N-type conduction channel is formed in 48, the interface potential of the silicon substrate 48 becomes the ground potential.

As described above, since the interface potential of the silicon substrate 48 under the gate differs depending on the direction of polarization,
When a potential difference is applied between the source and the drain, the current flowing differs depending on the direction of polarization. That is, in the state of logic "1" where the interface potential of the silicon substrate 48 is lower than the ground potential, a low resistance (O
N state), a large current flows, and the state of logic "0" where the potential of the silicon substrate 48 is the ground potential is a high resistance (OFF state) between the source and the drain, and almost no current flows. By examining the current between the source and the drain in this manner, it is determined whether the ferroelectric FET is in the ON state or not.
It is possible to know whether it is in the FF state.

In reading the logic state of one ferroelectric FET as described above, it is not necessary to apply a bias to the gate electrode 40 only by applying a potential difference between the source and the drain. That is, the ON state of the ferroelectric FET is MO
This corresponds to the depletion state of the S transistor.

However, as shown in FIGS. 5A and 5B, after writing data, a positive or negative bias is always generated in the ferroelectric 43. The oxide film 44 and the silicon substrate 4
8 and the potential distribution is ON or O
The state of the FF is determined.

[0009]

However, the ferroelectric 43
Is similar to an insulator, but its specific resistance is at most 10 ¹⁵ Ω
It is about 5 m, so if its thickness is 100 nm, 15
The resistance per m ² is 10 ⁷ Ω.

As shown in FIG. 4, since the area of the ferroelectric 43 is substantially the same as the gate area of the ferroelectric FET, the area of the ferroelectric and the gate area are normalized to 15 m ^2, and Discuss the characteristics.

Referring to FIG. 4, a gate electrode 40 and a silicon-based
The state where the plate 48 is at the ground potential is represented by an equivalent circuit in FIG.
become that way. Here, as shown in FIG._OXIs Siri
Capacity of the oxidized film, C_FIs the capacitance of the ferroelectric, R_FIs ferroelectric
The internal resistance of the body. C_OXIs a standard MOS transistor
0.1 μF / 5 at most from the capacity of the silicon oxide film
m ^Two, C_FIs 1μF / 5m^TwoAnd these parallel capacities are almost
1μF / 5m^TwoBecomes R_FIs 10 according to the previous discussion.⁷Ω
5m^TwoTherefore, virtual floating in the equivalent circuit of FIG.
The potential of the play electrode 50 is the capacitance C_OXAnd C_FAnd the resistance R_FThrough
Exponentially decreases with time due to discharge
I do. The time constant is (C_OX+ C_F) × R_FSo 10 seconds
Can be calculated. In practice, traps in the gate and low voltage
Time constant is extended by deviation from ohmic conduction in the region
There is a tendency, but still at most 10^ThreeSeconds are the experimental limit
You.

This means that the conduction channel disappears when the bias applied to the ferroelectric 43 is about 10 ³ seconds.
The stored data will be destroyed in a short time.

In order to put a ferroelectric FET into practical use as a non-volatile memory, it is necessary to retain data for at least 10 years (ie, 10 ⁸ seconds). For this purpose, the specific resistance of the ferroelectric must be reduced. 10 ²⁰ Ω of at least 5 digits or more
・ Must be raised to about 5m. However,
There is no technical means to obtain such a ferroelectric material having a high specific resistance, and this has been one factor that hinders industrial practical use of ferroelectric FETs.

[0014]

SUMMARY OF THE INVENTION In order to solve the above problems, the present invention provides a source region and a drain region on a silicon substrate, a dielectric formed between them, and a dielectric formed directly on the dielectric. A field effect transistor (FET) comprising a ferroelectric and a gate electrode formed thereon, when the ferroelectric is dominated by N-type conduction, the silicon substrate is N-type and the source region is A P-channel FET is formed with the P-type drain region and the P-type. When the P-type conduction is dominant in the ferroelectric, the silicon substrate is P-type, and the source region and the drain region are N-type.
It is composed of a nonvolatile semiconductor memory device in which an N-channel FET is formed as a mold.

As a result, even if a bias is applied to the ferroelectric for data retention, a small number of carriers of charges have a forward polarity in the bias, so that no charge is lost due to leakage, and data is stored for a long time. A memory cell that can be held can be provided.

[0016]

FIG. 1 is a sectional view showing a nonvolatile semiconductor memory device according to an embodiment of the present invention.

As shown in FIG. 1, in the nonvolatile semiconductor memory device of the present invention, a source region 5 and a drain region 6 are provided on a silicon substrate 8 and a dielectric 4 formed between them is formed.
And a field effect transistor (FET) comprising a ferroelectric 3 formed directly thereon and a gate electrode 10 formed thereon, when the ferroelectric 3 is dominated by N-type conduction, a silicon substrate A P-channel FET is formed by setting the source region 5 and the drain region 6 to be P-type. When the P-type conduction is dominant in the ferroelectric substance 3, the silicon substrate 8 is set to P-type. In addition, an N-channel FET is formed with the drain region 6 being N-type. With this configuration, there is an effect that data can be held for a long time without causing loss of charge due to leakage.

(Embodiment 1) In a nonvolatile semiconductor device according to Embodiment 1 of the present invention, when the P-type conduction is dominant in the ferroelectric substance 3, the silicon substrate 8 is of P-type. Here, a data holding state of this nonvolatile semiconductor device is shown in an energy band diagram shown in FIG.

Here, 21 is the conduction band of the gate electrode, 2
Reference numerals 2, 23, and 24 are energy bands of the ferroelectric, the silicon oxide film, and the silicon substrate, respectively.
The arrow 20 shown in FIG. 2 indicates the direction of polarization of the ferroelectric, and the broken line indicates the Fermi level.

Here, paying attention to the carrier of the charge of the leakage current via the internal resistance of the ferroelectric 3 in FIG. 1, since the interface between the ferroelectric 3 and the silicon oxide film 4 is in direct contact with each other, The charges present at the interface are polarization charges. Therefore, there is no freely movable carrier at this interface.

Then, the gate electrode 10 is biased positively with respect to the P-type silicon substrate 8 to direct the polarization toward the substrate, and then the bias is reduced to zero, as shown in FIG.
Conduction channel 2 formed on the surface of a silicon substrate
Hold 5.

At this time, as is apparent from FIG.
A negative bias is applied to the ferroelectric 3 with respect to the silicon substrate 8. Two carriers are injected into the ferroelectric substance by this bias, ie, injection of holes from the silicon oxide film 4 side and injection of electrons from the gate electrode 10 side. However, there is no freely movable carrier near the interface between the dielectric 3 and the silicon oxide film 4 at this interface, so that the carrier is not injected by the former mechanism. Therefore, the carrier is injected only from the gate electrode 10 side.

However, according to the present invention, since the P-type silicon substrate uses the ferroelectric material 3 in which P-type conduction is dominant,
Electrons injected from the gate electrode 10 side cannot conduct through the ferroelectric 3. Electrons that cannot be conducted are localized at the interface between the gate electrode 10 and the ferroelectric 3, but this increases the interfacial potential of the ferroelectric 3 with respect to the electrons at an accelerating rate. Disappears.

As a result, since the injection of electrons from the gate electrode 10 side is also eliminated, the bias applied to the ferroelectric 3 is maintained for a long period of time, whereby the N-type conduction channel on the surface of the P-type silicon substrate 8 is also maintained. Is done.

In the above-described configuration, the gate electrode 10 is biased negatively with respect to the P-type silicon substrate 8 so that the polarization is directed toward the gate electrode.
The N formed on the surface of the P-type silicon substrate as shown in FIG.
Suppose that the conduction channel 25 is to be erased. At this time, the negative bias to the gate electrode 10 is adjusted sufficiently small so that the bias as shown in FIG. 5B is not applied to the ferroelectric 3, so that the energy band is almost as shown in FIG. The N-type conduction channel 25 which is in a thermal parallel state and disappears is maintained almost permanently while disappearing.

(Embodiment 2) In a nonvolatile semiconductor device according to Embodiment 2 of the present invention, when the N-type conduction is dominant in the ferroelectric 3, the silicon substrate 8 is made N-type. Here, the data holding state of this nonvolatile semiconductor device is shown in the energy band diagram shown in FIG.

Here, 21 is the conduction band of the gate electrode, 2
Reference numerals 2, 23, and 24 denote the ferroelectric, the silicon oxide film, and the energy band of the silicon substrate, 26 denotes the energy band of the N-type silicon substrate, and 27 denotes the depletion layer of the N-type silicon substrate. Similarly, the arrow 30 shown in FIG. 3 indicates the direction of polarization of the ferroelectric, and the broken line indicates the Fermi level.

In the nonvolatile semiconductor memory device according to the second embodiment, the gate electrode 10 is biased negatively with respect to the N-type silicon substrate 8 so that the polarization is directed toward the gate electrode 10, and then the bias is reduced to zero. The P-type conduction channel 27 formed on the surface of the N-type silicon substrate as shown in FIG.

At this time, as is apparent from FIG.
A positive bias is applied to the ferroelectric 3 with respect to the silicon substrate 8. The carrier of the charge is injected into the ferroelectric by this bias in two ways: the injection of electrons from the silicon oxide film 4 side and the injection of holes from the gate electrode 10 side. However, there is no carrier that can freely move around the interface between the dielectric 3 and the silicon oxide film 4, so that the carrier is not injected by the former mechanism. Therefore, carrier injection is only injection of holes from the gate electrode 10 side.

However, according to the present invention, since the N-type silicon substrate uses a ferroelectric material in which N-type conduction is dominant, holes injected from the gate electrode 10 side cannot conduct through the ferroelectric material 3. . The holes that cannot be conducted are localized at the interface between the gate electrode 10 and the ferroelectric 3, but this increases the interfacial potential of the ferroelectric 3 with respect to the holes at an accelerating rate. Will not be performed.

As a result, the injection of holes from the side of the gate electrode 10 is also eliminated, so that the bias applied to the ferroelectric 3 is maintained for a long time, whereby the P-type conduction channel 27 on the surface of the N-type silicon substrate 8 is maintained. Is also maintained.

In the above configuration, the gate electrode 10 is biased positively with respect to the N-type silicon substrate 8 to direct the polarization toward the silicon substrate 8, and then the bias is reduced to zero, as shown in FIG. Thus, the P-type conduction channel 27 formed on the surface of the P-type silicon substrate is erased. At this time,
Since the positive bias applied to the gate electrode 10 is adjusted to be sufficiently small so that no bias is generated in the ferroelectric 3, FIG.
As shown in (b), the energy band is substantially in a heat parallel state, and the disappeared P-type conduction channel is maintained almost permanently while disappearing.

For example, when the ferroelectric is SrBi ₂ (Ta, Nb) ₂ O ₉ where N-type conduction is dominant, it is better to form a P-channel FET using an N-type silicon substrate than to form a P-type FET. Data storage and retention time is longer than when an N-channel FET is formed using a substrate.

[0034]

As described above, according to the present invention, the conduction channel once formed on the surface of the silicon substrate is retained for a long time, and the state does not change until the operation of erasing the conduction channel is performed. Also, once the conduction channel is erased, its state is maintained almost permanently.

[Brief description of the drawings]

FIG. 1 is a sectional view of an element of a nonvolatile semiconductor device of the present invention.

FIG. 2A shows a state in which an N-type conduction channel is maintained when a P-type silicon substrate and a P-type conductive dominant ferroelectric are used in the nonvolatile semiconductor memory device according to the first embodiment of the present invention; (B) Energy band diagram showing a state in which the N-type conduction channel of the nonvolatile semiconductor memory device according to the first embodiment of the present invention is erased.

FIG. 3A shows a state in which a P-type conduction channel is maintained when an N-type silicon substrate and a N-type-dominated ferroelectric are used in the nonvolatile semiconductor memory device according to the second embodiment of the present invention; (B) Energy band diagram showing a state where the P-type conduction channel of the nonvolatile semiconductor memory device according to the second embodiment of the present invention is erased.

FIG. 4 is a cross-sectional view of a conventional FET having a metal-ferroelectric-insulator-silicon gate structure.

5A is an energy band diagram showing a state of maintaining an N-type conduction channel when a P-type silicon substrate and a ferroelectric of a conventional nonvolatile semiconductor memory device are used; FIG. 5B is a conventional nonvolatile semiconductor memory device; Band diagram showing a state in which the N-type conduction channel of FIG.

FIG. 6 is an equivalent circuit diagram of a channel holding state of an N-channel FET.

[Explanation of symbols]

 Reference Signs List 3 ferroelectric 4 silicon oxide film 5 source region 6 drain region 7 channel 8 silicon substrate 10 gate electrode 21 gate electrode conduction band 22 ferroelectric energy band 23 oxide film energy band 24 p-type silicon substrate energy band 25 N-type conduction channel 26 Energy band of N-type silicon substrate 27 P-type conduction channel

Claims (1)

[Claims] An electric field comprising a dielectric formed above a source region and a drain region on a silicon substrate, a ferroelectric formed directly thereon, and a gate electrode formed thereon. In an effect transistor (FET), when the ferroelectric material is dominated by N-type conduction, a P-channel FET is formed by setting the silicon substrate to N-type and the source and drain regions to P-type. When the P-type conduction is dominant in the dielectric, the silicon substrate is P-type, and the source region and the drain region are N-type.
A nonvolatile semiconductor memory device in which an N-channel FET is formed as a mold.