JP2002064096A - Semiconductor device and manufacturing method thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device with a nitride film which can lower electrical stress. SOLUTION: A gate nitride film 4 containing fluorine is formed on an N-type well layer 2 by a plasma CVD method in a gas atmosphere containing silicon tetrafluoride (SiF4) and ammonium (NH3). Thus, the dangling bond in the gate nitride film 4 is terminated by an Si-F combination to lower an interface level between the gate nitride film 4 and the N-type well layer 2. So, a semiconductor device of low electrical stress is manufactured.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device having a nitride film and a method of manufacturing the same. It is suitable.

[0002]

2. Description of the Related Art In order to improve the performance of a semiconductor integrated circuit device, high integration and high speed are required, and it is required to miniaturize a MOSFET which is a typical semiconductor element. I have. In response to this demand, the size in the thickness direction has been reduced along with the size reduction in the substrate surface. For example, the gate oxide film has been reduced to 2 nm or less, and the extension / source / drain junction has been reduced to 100 nm or less.

When the MOSFET is miniaturized, the influence of the direct tunnel current increases because the gate oxide film becomes thinner, and it is necessary to reduce the effect. For this reason, a method of increasing the physical film thickness without changing the capacitance of the insulating film by using a material having a larger relative dielectric constant than the oxide film has been studied.

A material having a higher relative dielectric constant than an oxide film is a nitride film. Normally, when a nitride film is formed by a plasma chemical vapor deposition (hereinafter, referred to as CVD) method, monosilane (SiH ₄ ) and nitrogen (N ₂ ) or SiH ₄ and ammonia (NH ₃ ) are used as atmosphere gases. Is often used,
When a film is formed by the JVD (Jet Vapor Deposition) method, SiH ₄ and N ₂ are used.

However, when these gases are used, a large amount of hydrogen remains in the nitride film, and the hydrogen in the nitride film (for example, a portion existing by Si—H bond or N—H bond) is trapped in charge. And a change in electrical stress due to release of hydrogen (deterioration of transistor characteristics due to an increase in interface states and an increase in charge traps).

As a measure for preventing this problem, it is conceivable to form a nitride film by a thermal CVD method in which residual hydrogen in the nitride film is reduced. The thermal CVD method is generally such NH ₃ dichlorosilane (SiC ₁₂ H ₂₎ introduced into the furnace, 700 ° C. ~
This is performed at about 800 ° C. in a reduced pressure atmosphere. However, since the film formation temperature is high, there is a concern that the interface level may increase due to the film stress of the nitride film itself, and the short channel effect may deteriorate due to impurity diffusion of the channel.

SUMMARY OF THE INVENTION In view of the foregoing, it is an object of the present invention to provide a semiconductor device having a nitride film capable of reducing electric stress and a method of manufacturing the same.

[0008]

Means for Solving the Problems To achieve the above object,
According to the first aspect of the present invention, silicon tetrafluoride (SiF
_Four) And ammonia (NH_Three) In a gas atmosphere containing
Silicon nitride film containing fluorine on body layer (2, 32)
Forming a (4, 34) film and forming an electrode on the silicon nitride film.
Forming the poles (5, 36).
Features.

As described above, by forming a silicon nitride film on a semiconductor layer in a gas atmosphere containing silicon tetrafluoride (SiF ₄ ) and ammonia (NH ₃ ), a dangling bond is formed by a Si—F bond. And the interface state at the interface between the silicon nitride film and the semiconductor layer can be reduced. Thus, a semiconductor device with low electric stress can be manufactured. In particular, it is preferable to apply to a miniaturized semiconductor device in which the thickness of the silicon nitride film is 5 nm or less.

The invention according to claim 2 relates to a method for manufacturing a semiconductor device such as a MOS transistor, and the inventions according to claims 3 and 4 relate to a method for manufacturing a semiconductor device such as a liquid crystal. By applying a silicon nitride film to a gate insulating film in a semiconductor device such as a MOS transistor or a liquid crystal and forming the silicon nitride film in the same step as in claim 1, the same effect as in claim 1 can be obtained. Can be.

Further, a silicon nitride film can be applied to the passivation film as described in claim 5, or a silicon nitride film can be applied to the interlayer insulating film as described in claim 6. In these cases, since the nitride film manufactured by the above process has high insulating properties, it is possible to obtain an effect of preventing a leak current.

Specifically, the silicon nitride film can be formed by a plasma enhanced chemical vapor deposition method.

The invention according to claim 8 is characterized in that a pulse modulated plasma is used as the plasma enhanced chemical vapor deposition method. When such pulse-modulated plasma is used, negative ions are formed instead of electrons, so that the energy hit by the ions is reduced, and damage to the silicon nitride film and the like can be reduced.

According to a ninth aspect of the present invention, in the step of forming the silicon nitride film, the gas flow ratio of ammonia to silicon tetrafluoride is set to 1.9 or more. With such a gas flow ratio, the amount of Si—N bonds in the silicon nitride film can be increased.

According to a tenth aspect of the present invention, in the step of forming the silicon nitride film, the gas flow ratio of ammonia to silicon tetrafluoride is set to 4.5 or less. With such a gas flow ratio,
The fluorine concentration in the silicon nitride film can be increased.

In the step of forming the silicon nitride film, if the gas flow ratio of ammonia to silicon tetrafluoride is about 2.5, the amount of Si—N bonds in the silicon nitride film can be increased and the fluorine concentration can be increased. Can be higher.

The same effect as described above can be obtained by using silicon tetrafluoride in which one of the elements constituting silicon tetrafluoride is an isotope thereof. Further, the same effect as described above can be obtained even if any one of the elements constituting ammonia uses ammonia composed of its isotope. Further, hydrogen (H ₂ ) or deuterium (D ₂ ) may be introduced into the gas atmosphere.

The invention according to claims 15 and 16 is characterized in that
A semiconductor substrate (1, 31) having a conductive semiconductor layer (2, 32); a gate nitride film (4, 34) formed on the semiconductor layer; and a metal electrode layer (4) formed on the gate nitride film. 5, 36), and the gate nitride film contains fluorine, and the fluorine concentration is 9% to 1 in atomic composition ratio.
It is characterized by 2%. in this way,
The fluorine concentration of the gate nitride film is set to 9% to 12 in atomic composition ratio.
%, A semiconductor device with low electric stress can be obtained. The invention according to claims 17 to 30 relates to a semiconductor device formed by the manufacturing method according to claims 1 to 14.

Note that the reference numerals in parentheses of the above means indicate the correspondence with specific means described in the embodiments described later.

[0020]

(First Embodiment) FIG. 1 shows a process for manufacturing a MOS diode according to an embodiment of the present invention. Hereinafter, based on this figure, the MOS in the present embodiment will be described.
A method for manufacturing a diode will be described.

[Step shown in FIG. 1A] First, (10
A CZ silicon substrate (semiconductor substrate) 1 having a 0) plane is prepared. Then, after forming an N-type well layer 2 as a semiconductor layer on the CZ silicon substrate 1, an element isolation region 3 is formed by a known method.

Subsequently, as a pretreatment for forming a gate insulating film, R
After performing the CA cleaning, the N is further increased with 0.5% hydrofluoric acid aqueous solution.
The natural oxide film formed on the mold well layer 2 is removed and washed with pure water.

[Step shown in FIG. 1B] Plasma CVD
Using a device, a gate nitride film 4 is formed on the surface of the N-type well layer 2.
Is formed. The plasma CVD apparatus forms a thin film by plasma discharge decomposition of a reactive gas under reduced pressure, and has a feature that, unlike the thermal CVD method, a CVD reaction is established at a relatively low temperature. FIG. 2 shows the plasma CV
A schematic configuration of an ECR-plasma CVD apparatus 10, which is an example of a D apparatus, is shown, and a specific manufacturing process of the gate nitride film 4 will be described with reference to FIG.

As shown in FIG. 2, ECR-plasma CV
The D apparatus 10 includes a chamber 11 in which the CZ silicon substrate 1 is accommodated. This chamber 11 is CZ
A large-diameter reaction chamber 11a in which the silicon substrate 1 is disposed, and a small-diameter plasma chamber 1 partially protruding from the reaction chamber 11a.
1b.

A quartz window 12 is provided at the tip of the plasma chamber 11b.
Further, a microwave supply source 13 for supplying a microwave is provided in the chamber 11, and the microwave is supplied into the chamber 11 through the quartz window 12. Further, a gas inlet 14 is provided at the tip of the plasma chamber 11 b, and ammonia (NH ₃ ) gas is introduced into the chamber 11 from the gas inlet 14. An electromagnet 15 and a permanent magnet 16 are provided on the outer periphery of the plasma chamber 11b so that a desired magnetic field can be formed in the chamber 11.

A gas ring 17 is provided in the reaction chamber 11a, and silicon tetrafluoride (S
iF ₄ ) gas is introduced into the chamber 11. Also,
The reaction chamber 11a is provided with an exhaust hole 18 so that the pressure inside the chamber 11 can be controlled by a pump or the like (not shown).

The CZ silicon substrate 1 is supported by a pedestal 19 in the reaction chamber 11a. The pedestal 19 is provided with a carbon heater 20 and the CZ silicon substrate 1
Can be heated from the back side. A single probe 21 extends to near the surface of the CZ silicon substrate 1 supported on the pedestal 19, and the single probe 21 can measure the electron density.

ECR-plasma CVD with such a configuration
Using the device 10, the internal pressure of the chamber 11 is 0.5P
a, temperature of 350 ° C., microwave power of 300 W, gas flow rate of 20 sccm for SiF _{4 and} 50 sccm for NH ₃
The gate nitride film 4 is formed under such film forming conditions as follows. In the present embodiment, for example, the gate nitride film 4 is formed so that the physical film thickness is about 4 nm. This is about 2.2 nm in terms of an oxide film.

At this time, when the electron density was measured with N ₂ gas, the electron density was about 1 × 10 ⁹ to 10 ¹² cm ^−3.
Met. Incidentally, in the case of the RF parallel plate type PECVD apparatus, since the electron density is usually 10 ⁸ , it can be said that the present embodiment is a high-density plasma as compared with this case.

[Step shown in FIG. 1C] Gate nitride film 4
Aluminum by evaporation to cover the surface of
A metal electrode layer 5 serving as an electrode is formed by depositing and patterning a thickness of about μm. Thus, a CZ silicon substrate 1 as a semiconductor substrate having an N-type well layer 2 as a semiconductor layer, a gate nitride film 4 formed on the N-type well layer 2, and a metal electrode formed on the gate nitride film As described later, the gate nitride film 4 has an atomic composition ratio of 9% to 12% and an Si—N bond amount of 2 to
The MOS diode of 2.5 is completed.

As described above, in the present embodiment, Si
The gate nitride film 4 is formed by high-density plasma CVD using F ₄ and NH ₃ .

As described above, the gate nitride film 4 was formed by plasma CVD using SiF ₄ and NH _3, and the plasma CVD using normal fluorine-free gas (SiH ₄ and NH ₃ ) was performed. For both cases, the amount of residual hydrogen in the film was examined by transmission Fourier transform infrared spectroscopy (FT-IR). The result is shown in FIG.

This figure shows the relationship between the wave number of infrared light (the reciprocal of the wavelength) and the density of coupling.
As can be seen from this figure, a case where a normal gas without fluorine addition is used and a case where SiF ₄ and NH ₃ are used as in this embodiment.
Is compared with the case where is used, the wave number is ~ 1200 cm ^-1
In the bending mode (shown as NH (B) in the figure), the stretchi with a wave number of ~ 3340 cm ^-1
In both the ng mode (shown as NH (S) in the figure), the NH bond is significantly reduced when SiF ₄ and NH ₃ are used. And the wave number is ~ 8
Si in an antisymmetric streching mode of 50 cm ^-1 (shown as Si-N (AS) in the figure)
As you can look at the -N bond, with respect to the Si-N bond, even with the SiF ₄ and NH _3, the case of using SiH ₄ and NH ₃ without fluoridation and Si- The number of N bonds hardly changes. That is,
By plasma CVD using SiF ₄ and NH ₃ , the number of N—H bonds can be reduced without reducing the number of Si—N bonds as compared with the case of using SiH ₄ and NH ₃ without addition of fluorine. You can.

This is because, by interposing fluorine in the gate nitride film 4 or at the interface between the gate nitride film 4 and the N-type well layer 2, the Si—H that terminates the dangling bond usually becomes Si—F It is considered to be replaced by

Then, the bond energy of Si—H is 3.3.
Since the binding energy of Si-F is as large as 5.8 eV with respect to eV, the barrier height against hole current is increased, so that the electric stress fluctuation is reduced and the reliability of the MOS diode can be improved. As a result of an experiment, it was found that the fluorine concentration in the gate nitride film 4 was 9% to 12% as an atomic composition ratio of the nitride film.

It is conceivable to add chlorine instead of fluorine. In this case, however, it is more preferable to add fluorine because the bonding energy of Si—Cl is 3.9 V, which is smaller than the bonding energy of Si—F. It can be said that it is more preferable.

When NH ₃ and SiF ₄ are used, N
Hydrogen in the H ₃ gas is extracted by fluorine in the SiF ₄ gas, and fluorine enters the interface between the gate nitride film 4 and the N-type well layer 2. This is considered to be because fluorine has a higher electronegativity than hydrogen, and thus it is easier to terminate dangling bonds than hydrogen.
Therefore, the interface state at the interface between the gate nitride film 4 and the N-type well layer 2 is reduced.

FIG. 4 shows the gate nitride film 4 and the N-type well layer 2.
FIG. 4 is a CV characteristic diagram in which an interface state at an interface with the semiconductor device and a charge trap in the gate nitride film 4 are examined. In this figure, (a) shows the CV characteristics in the present embodiment, and (b) shows the CV characteristics when fluorine is not added. As shown in this figure, the hysteresis characteristic of the present embodiment is improved as compared with the case where no fluorine is added, and in the case of the present embodiment, it appears when no fluorine is added. No hump (characteristic curve has a protruding shape) does not appear. This also indicates that the interface state at the interface between the gate nitride film 4 and the N-type well layer 2 is reduced.

As described above, by reducing the interface state at the interface between the gate nitride film 4 and the N-type well layer 2,
It is possible to improve the driving capability of the MOS diode and the saturation current.

Further, since the gate nitride film 4 in this embodiment has a refractive index and a Si—N bond amount equal to or higher than those formed without adding fluorine,
So-called "boron loss" in which impurities hardly diffuse and boron existing in the metal electrode layer 5 diffuses into the gate nitride film 4 during a heat treatment step performed after the formation of the gate nitride film 4.
Can be prevented.

The electron density in the ECR-plasma CVD apparatus 10 shown in this embodiment is
Has been found to be 1 × 10 ⁹ to 10 ¹² cm ⁻³ . By using such a high-density plasma, a high dissociation of gas can be expected, and it is possible to prevent the gate nitride film 4 from becoming porous (hollow) by fluorine. It becomes possible to suppress. On the other hand, when high-density plasma is used, there is a concern that the CZ silicon substrate 1 and the gate nitride film 4 themselves may be damaged by high electron temperature. However, in the present embodiment, pulse-modulated plasma is used, and negative fluorine ions are confined instead of electrons in the plasma, so that the electron temperature is lowered and the CZ silicon substrate 1 and the gate nitride film 4 The damage of itself is reduced. Therefore, the plasma C shown in the present embodiment is
According to the VD method, it is possible to lower the electron temperature while using high-density plasma.

Here, the gas flow rate is set to NH ₃ as described above.
The reason why is 50 sccm and SiF ₄ is 20 sccm will be described.

FIG. 5A shows the relationship between the flow rate of the gas and the flow rate of Si.
It shows the relationship between the -N bond amount and the fluorine concentration. Regarding the fluorine concentration, XPS (X-ray photoelectron spectro
scopy) from the F1s / Si2p / N1s ratio,
Regarding the amount of Si—N bond, FT-IR RAS (fourie
r transfoem infrared reflection absorptionspec
troscopy).

On the other hand, as described above, it has been confirmed that it is suitable when the concentration of fluorine is 9% to 12% in atomic composition ratio. Further, the amount of the Si—N bond was determined to be 2 to 2.
When it was 6, it was confirmed that it was suitable.

From these results, the gas flow ratio (NH ₃ /
When SiF ₄ ) is 1.9 or more, the amount of Si—N bond falls within the above range. Experiments have confirmed that the gas flow ratio falls within the above range at least when the gas flow ratio is 17 or less. When the gas flow rate ratio is 4.5 or less, the fluorine concentration falls within the above range. In experiments, it was confirmed that the above range was obtained at least when the gas flow rate ratio was 2.5 or more. In particular, when the gas flow ratio is 2.
5 (that is, NH ₃ / SiF ₄ = 50/20).
The N bond amount and the fluorine concentration are the most preferable values.

FIG. 5B is a JV characteristic diagram showing the relationship between the gas flow ratio and the insulating property of the formed gate nitride film 4. Here, in consideration of the thickness variation of the formed gate nitride film 4, each data is adjusted so as to show the insulating property when the gate nitride film 4 is formed with a thickness of 4 nm.

As can be seen from the results, NH ₃ / S
When iF ₄ = 50/20, the direct tunnel current is most suppressed. Here, the JV characteristic is shown only when the gas flow ratio is 2.5, but the gas flow ratio is 2.5 for all cases where the gas flow ratio is 1.7 to 5.
It is considered that good insulation can be obtained as in the case of

As shown in these results, by setting the gas flow rate ratio to 1.9 to 4.5, particularly 2.5, the Si—N bond amount and the fluorine concentration in the gate nitride film 4 can be reduced. A gate nitride film that can be in a desired range and that has good insulating properties can be obtained. For this reason, in the present embodiment, these effects are set to the gas flow rate ratio that can obtain the most.

(Second Embodiment) In the first embodiment, the case where the present invention is applied to a MOS diode has been described. In the present embodiment, a case where the present invention is applied to a salicide structure MOS transistor will be described. FIG. 6 shows a manufacturing process of the MOS transistor according to the present embodiment, and a manufacturing method of the MOS transistor will be described with reference to FIG.

[Step shown in FIG. 6A] First, (10
A CZ silicon substrate 31 having a 0) plane is prepared. Then, after forming the N-type well layer 32 on the CZ silicon substrate 31, an element isolation region 33 is formed by a known method.

Subsequently, as a pretreatment for forming a gate insulating film, R
After performing the CA cleaning, the N is further increased with 0.5% hydrofluoric acid aqueous solution.
The natural oxide film formed on the mold well layer 32 is removed and washed with pure water.

[Step shown in FIG. 6B] Using the ECR-plasma CVD apparatus 10 shown in FIG. 2 of the first embodiment, an N-type well layer is formed under the same film forming conditions as in the first embodiment. A gate nitride film 34 is formed on the surface of
m, or about 2.2 nm in terms of oxide film.

As a result, the dangling bond becomes Si-
The gate nitride film 34 terminated by F-coupling can be formed, and the interface state at the interface between the gate nitride film 34 and the N-type well layer 32 can be reduced.

[Step shown in FIG. 6C] Gate nitride film 3
Polysilicon is deposited to a thickness of about 160 nm using a low pressure (LP) CVD method so as to cover 4, and B ⁺ is ion-implanted over the entire surface of the polycrystalline silicon by an ion implantation method.

Subsequently, patterning is performed by photolithography. Here, in order to improve patterning accuracy, an anti-reflection film (ARL-SIN) 35 made of a nitride film or the like for preventing reflection from a base is formed by PECVD for 30 n.
After about m deposition, the gate electrode 36 is patterned by etching using HBr + O ₂ gas.

[Step shown in FIG. 6D] Gate electrode 36
Is used as a mask to implant BF ₂ ⁺ to form a shallow p-type diffusion layer 37 serving as an electric field relaxation layer.

[Step shown in FIG. 7A] An oxide film is deposited on the entire surface of the substrate to a thickness of about 80 nm by the CVD method, and then anisotropically using a mixed gas of CHF ₃ , CF ₄ , and Ar. The oxide film and the gate nitride film 34 are etched back by reactive dry etching (RIE) to leave an oxide film only on the side wall of the gate electrode 36, thereby forming a side wall oxide film (sidewall spacer) 38 and the gate nitride film 3
4 is removed except for the portion located under the gate electrode 36.

[Step shown in FIG. 7B] After the antireflection film 35 is peeled off with phosphoric acid, B ⁺ ions are implanted using the side wall insulating film 38 and the gate electrode 36 as a mask. Accordingly, in the surface layer portion of the N-type well layer 32 located on both sides of the gate electrode 36, the p ⁺ -type high-concentration source region having a deeper junction depth than the p-type diffusion layer 37 as the electric field relaxation layer 39 and a drain region 40 are formed.

[Step shown in FIG. 7C] First, after a thin oxide film formed on the silicon active layer is removed with an etching solution (for example, hydrofluoric acid), for example, Co or the like is formed on the silicon active layer by sputtering. A refractory metal film is deposited.

Next, a two-step short-time heat treatment is performed. Specifically, after a low-temperature heat treatment is performed to cause a primary silicide reaction, the unreacted high-melting-point metal film is removed with an etchant (for example, ammonia peroxide + persulfuric acid), and a second heat treatment is performed. As a result, refractory metal silicide antinodes 36a, 39a, and 40a are formed in a self-aligned manner on the exposed silicon active layer (that is, the gate electrode 36, the source region 39, and the drain region 40).

[Step shown in FIG. 7D] After a silicon oxide film is deposited on the entire surface of the substrate by using the plasma CVD method, an SOG film is applied by a spin-on-glass method (SOG) for planarization. Vitrification by heating. Thereby, an interlayer insulating film 41 is formed on the upper surface of the substrate. The flattening method includes CMP.
(Chemical mechanical polishing) method may be used.

Subsequently, by a photolithography process,
A gate electrode 36, a source region 39,
Silicide films 36a, 39a, 4 on drain region 40
After forming a contact hole 41a for exposing the contact hole 41a, a barrier metal or A
A metal wiring layer including one alloy layer is arranged, and the source region 39 and the drain region 40 are formed by patterning the metal wiring layer.
And the like to form each electrode to be connected.

Thereafter, although not shown, a passivation film is formed so as to cover the electrode surface. Thus, a CZ silicon substrate 31 as a semiconductor substrate having an N-type well layer 32 as a semiconductor layer, a gate nitride film 34 formed on the N-type well layer 32, and a metal electrode formed on the gate nitride film And a gate electrode 36 as a layer. As will be described later, a salicide structure in which the fluorine concentration of the gate nitride film 34 is 9% to 12% in atomic composition ratio and the Si—N bond amount is 2 to 2.5. Is completed.

As described above, also in the MOS transistor, by forming the gate nitride film 34 formed in the same manner as in the first embodiment, the gate nitride film 3 is formed.
The interface level at the interface between the N-type well 4 and the N-type well layer 32 can be reduced, and the driving capability of the MOS transistor and the saturation current can be improved. Further, during a heat treatment step performed after the formation of the gate nitride film 34, it is possible to prevent so-called “boron removal” in which boron existing in the gate electrode 36 diffuses into the gate nitride film 34.

(Other Embodiments) In the above embodiments, the thickness of the gate nitride film 4 is set to 4 nm. However, this is an example, and the thickness of the gate nitride film 4 may be any value. I do not care. However, the present invention is particularly effective for miniaturized semiconductor devices, for example, when the thickness of the gate nitride film 4 is 1 to 5
It is effective when it is set to about nm.

In the first and second embodiments, SiF ₄ and NH ₃ are used as gases used for forming the nitride film. However, a gas in which one of these elements is replaced with an isotope may be used. good. For example, H (hydrogen) in NH ₃ may be replaced with D (deuterium), which is an isotope.

In the first and second embodiments, the case where the present invention is applied to a MOS diode or a MOS transistor having a salicide structure has been described. However, the present invention can be applied to a semiconductor device having another MOS structure. Further, the present invention can be applied to a tunnel film of a semiconductor memory in which a floating gate is disposed on a tunnel film.
Also, like a liquid crystal (TFT), an insulating film having a structure in which a source and a drain are formed on a glass substrate, and polycrystalline (amorphous) silicon, an insulating film, and a gate electrode are sequentially stacked so as to include the source and the drain. It is also possible to apply the present invention. In this case, a step of forming a source and a drain on a glass substrate, a step of forming polycrystalline silicon on a glass substrate including the source and the drain, and including silicon tetrafluoride (SiF ₄ ) and ammonia (NH ₃ ) In a gas atmosphere, a semiconductor device having the above structure can be manufactured by a step of forming a silicon nitride film containing fluorine on polycrystalline silicon, a step of forming a gate electrode on the silicon nitride film, and the like. Needless to say, a semiconductor device having the above structure can be manufactured by a method of forming a source and a drain in polycrystalline silicon after forming polycrystalline silicon on a glass substrate.

In each of the above embodiments, the case where the nitride film manufactured according to the present invention is applied to the gate insulating film, taking into account the effect of the interface level at the interface between the insulating film and the impurity layer, is taken into consideration. However, the present invention can be applied to insulating films for other uses.

For example, an etching stopper is formed on both sides of the interlayer insulating film, and the nitride film according to the present invention can be used for the etching stopper. A semiconductor device having such a structure includes a step of forming an interlayer insulating film on a semiconductor substrate provided with elements, and a step of forming a contact hole in the interlayer insulating film. Electrical connection is made. In the step of forming an interlayer insulating film, a silicon nitride film containing fluorine is formed in a gas atmosphere containing silicon tetrafluoride (SiF ₄ ) and ammonia (NH ₃ ). What is necessary is just to include the process of forming a film.

The nitride film of the present invention can be used as a passivation film. In particular, the present invention is effective because a passivation film can be formed by a low-temperature process. In the case of a semiconductor device having such a structure, a step of forming a passivation film on a semiconductor substrate provided with elements is included. In the step of forming the passivation film, silicon tetrafluoride (S
In a gas atmosphere containing iF ₄ ) and ammonia (NH ₃ ),
A step of forming a silicon nitride film containing fluorine may be included.

In these applications, since the nitride film of the present invention has a high insulating property, it is possible to obtain effects such as prevention of leak current.

In the first and second embodiments, the case where the gate nitride film is formed by the ECR-plasma CVD apparatus has been described. However, other apparatuses such as a UHF plasma CVD apparatus (plasma CV having a frequency of 500 MHz) may be used.
D apparatus), VHF plasma CVD apparatus (frequency 60 MH
The same effect as described above can be obtained by forming a gate nitride film using a plasma CVD apparatus of z to 100 MHz), an ICP plasma CVD apparatus (inductively coupled plasma CVD apparatus), a surface wave plasma CVD apparatus, or an RF parallel plate CVD apparatus. can get.

In the above embodiment, SiF ₄ and NH ₃
, But hydrogen (H ₂ ) or deuterium (D ₂ ) may be further introduced into the gas atmosphere.

In each of the above embodiments, the metal electrode layer 5
Although the case where the gate electrode 36 is formed of a metal is described, the metal electrode layer 5 and the gate electrode 36 may be arranged via a metal oxide film serving as a barrier layer or the like.

[Brief description of the drawings]

FIG. 1 is a diagram showing a manufacturing process of a MOS diode according to a first embodiment of the present invention.

FIG. 2 is a view showing a schematic configuration of an ECR-plasma CVD apparatus used for forming a gate nitride film of the MOS diode shown in FIG.

FIG. 3 is a diagram showing the relationship between the wave number of infrared light and the density occupied by bonds in a gate nitride film.

FIG. 4 is a CV characteristic diagram in which an interface state at an interface between a gate nitride film and an N-type well layer and a charge trap in the gate nitride film are examined.

5A is a diagram showing a relationship between a Si—N bond amount and a fluorine concentration with respect to a gas flow ratio, and FIG. 5B is a diagram showing a relationship between a gas flow ratio and an insulating property of a formed gate nitride film. It is a JV characteristic view showing a relationship.

FIG. 6 is a diagram illustrating a manufacturing process of a MOS transistor according to a second embodiment of the present invention.

FIG. 7 is a view showing a manufacturing step of the MOS transistor following FIG. 6;

[Description of Signs] 1, 31 ... CZ silicon substrate, 2, 32 ... N-type well layer, 4, 34 ... Gate nitride film, 5 ... Metal electrode layer, 36 ...
Gate electrode, 39: source region, 40: drain region.

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ Identification code FI Theme coat ゛ (Reference) H01L 21/336 H01L 29/78 617V 619A (72) Inventor Hiroyuki Ota Nagoya University F term (reference) 4K030 AA04 AA05 AA13 BA29 BA40 BB03 BB12 CA04 CA06 CA12 FA02 JA01 JA05 5F040 DA08 DA17 DA30 DC01 EB17 EC04 EC07 EC13 ED04 EF02 EH02 EJ03 EK01 EK05 EL06 FA05 FC19 FC27 5BF0BB07BF10 BC30 BC10BF30 5F110 AA06 AA17 AA30 BB03 CC02 DD02 EE03 EE05 EE32 EE43 FF03 FF07 FF31 GG02 GG13 GG15 HJ01 HJ13 HL03 HM15 NN02 NN24 NN35 QQ11 QQ21

Claims (30)

[Claims] A step of forming a silicon nitride film containing fluorine on a semiconductor layer in a gas atmosphere containing silicon tetrafluoride (SiF ₄ ) and ammonia (NH ₃ ); A method for manufacturing a semiconductor device, comprising: forming an electrode. 2. A step of forming a first conductivity type semiconductor layer on a semiconductor substrate, and forming fluorine on the semiconductor layer in a gas atmosphere containing silicon tetrafluoride (SiF ₄ ) and ammonia (NH ₃ ). Forming a gate electrode on the silicon nitride film; forming a gate electrode on the silicon nitride film; forming a gate electrode on the silicon nitride film; Forming a region and a drain region. Forming a source and a drain on the glass substrate; forming polycrystalline silicon on the glass substrate including the source and the drain; forming silicon polyfluoride (SiF ₄ ) and ammonia (NH ₃ ); ₃ ) forming a silicon nitride film containing fluorine on the polycrystalline silicon in a gas atmosphere containing ₃ ); forming a gate electrode on the silicon nitride film;
A method for manufacturing a semiconductor device, comprising: 4. A step of forming polycrystalline silicon on a glass substrate; a step of forming a source and a drain in the polycrystalline silicon; and a gas atmosphere containing silicon tetrafluoride (SiF ₄ ) and ammonia (NH ₃ ). Forming a silicon nitride film containing fluorine on the polycrystalline silicon; forming a gate electrode on the silicon nitride film;
A method for manufacturing a semiconductor device, comprising: 5. A step of forming a passivation film on a semiconductor substrate provided with an element, wherein the step of forming the passivation film includes silicon tetrafluoride (SiF ₄ ) and ammonia (NH ₃ ). A method for manufacturing a semiconductor device, comprising a step of forming a silicon nitride film containing fluorine in a gas atmosphere. 6. A method for manufacturing a semiconductor device, comprising the step of forming an interlayer insulating film on a semiconductor substrate provided with elements, wherein the step of forming the interlayer insulating film includes the step of forming silicon tetrafluoride (S
In a gas atmosphere containing iF ₄ ) and ammonia (NH ₃ ),
A method for manufacturing a semiconductor device, comprising a step of forming a silicon nitride film containing fluorine. 7. The method of manufacturing a semiconductor device according to claim 1, wherein the step of forming the silicon nitride film is performed by a plasma enhanced chemical vapor deposition method. 8. The method according to claim 7, wherein a pulse-modulated plasma is used as the plasma enhanced chemical vapor deposition method. 9. The method according to claim 1, wherein in the step of forming the silicon nitride film, a gas flow ratio of ammonia to silicon tetrafluoride is 1.9 or more. Of manufacturing a semiconductor device. 10. The method according to claim 1, wherein in the step of forming the silicon nitride film, a gas flow ratio of ammonia to the silicon tetrafluoride is set to 4.5 or less. Of manufacturing a semiconductor device. 11. The method according to claim 2, wherein in the step of forming the silicon nitride film, the silicon nitride film is formed with a thickness of 5 nm or less. 12. The method according to claim 1, wherein one of the elements constituting the silicon tetrafluoride uses silicon tetrafluoride composed of its isotope. A method for manufacturing a semiconductor device. 13. The method of manufacturing a semiconductor device according to claim 1, wherein one of the elements constituting ammonia uses ammonia composed of isotopes thereof. 14. The method for manufacturing a semiconductor device according to claim 1, wherein hydrogen (H ₂ ) or deuterium (D ₂ ) is introduced into the gas atmosphere. 15. A semiconductor device comprising: a semiconductor substrate having a semiconductor layer of a first conductivity type; a gate nitride film formed on the semiconductor layer; and a metal electrode layer formed on the gate nitride film. A semiconductor device, characterized in that the nitride film contains fluorine, and the fluorine concentration is 9% to 12% in atomic composition ratio. 16. The semiconductor device according to claim 15, wherein the amount of Si—N bonds in the gate nitride film is 2 to 2.6. 17. After forming a silicon nitride film containing fluorine on a semiconductor layer in a gas atmosphere containing silicon tetrafluoride (SiF ₄ ) and ammonia (NH ₃ ), an electrode is formed on the silicon nitride film. A semiconductor device constituted by forming a. 18. After forming a first conductivity type semiconductor layer on a semiconductor substrate, fluorine is contained on the semiconductor layer in a gas atmosphere containing silicon tetrafluoride (SiF ₄ ) and ammonia (NH ₃ ). Forming a silicon nitride film, further forming a gate electrode on the silicon nitride film, and forming a second conductivity type source region and a drain region in portions of the surface layer of the semiconductor layer located on both sides of the electrode. And a semiconductor device formed by forming a region. 19. Forming a source and a drain on a glass substrate and forming polycrystalline silicon on the glass substrate including the source and the drain,
F ₄ ) and a gas atmosphere containing ammonia (NH ₃ ), a silicon nitride film containing fluorine is formed on the polycrystalline silicon, and then a gate electrode is formed on the silicon nitride film. Semiconductor device. 20. Polycrystalline silicon is formed on a glass substrate, and a source and a drain are formed in the polycrystalline silicon, and silicon tetrafluoride (SiF ₄ ) and ammonia (N
A semiconductor device comprising: forming a silicon nitride film containing fluorine on the polycrystalline silicon in a gas atmosphere containing H ₃ ); and forming a gate electrode on the silicon nitride film. 21. A passivation film is formed on a semiconductor substrate provided with an element, wherein the passivation film is formed of silicon tetrafluoride (SiF ₄ ) and ammonia (N
A semiconductor device comprising a silicon nitride film containing fluorine formed in a gas atmosphere containing H ₃ ). 22. An interlayer insulating film formed on a semiconductor substrate provided with an element, wherein the interlayer insulating film is formed in a gas atmosphere containing silicon tetrafluoride (SiF ₄ ) and ammonia (NH ₃ ). A semiconductor device comprising a silicon nitride film containing fluorine. 23. The semiconductor device according to claim 17, wherein said silicon nitride film is formed by plasma enhanced chemical vapor deposition. 24. The plasma enhanced chemical vapor deposition method,
24. The semiconductor device according to claim 23, wherein a pulse-modulated plasma is used. 25. The silicon nitride film according to claim 17, wherein a gas flow ratio of ammonia to silicon tetrafluoride is 1.9 or more.
5. The semiconductor device according to any one of 4. 26. The silicon nitride film according to claim 17, wherein a gas flow ratio of ammonia to said silicon tetrafluoride is set to 4.5 or less.
6. The semiconductor device according to any one of 5. 27. The semiconductor device according to claim 19, wherein said silicon nitride film has a thickness of 5 nm or less. 28. The method according to claim 17, wherein one of the elements constituting silicon tetrafluoride uses silicon tetrafluoride composed of its isotope. 13. The semiconductor device according to claim 1. 29. The semiconductor device according to claim 17, wherein one of the elements constituting ammonia uses ammonia composed of its isotope. 30. The semiconductor device according to claim 17, wherein hydrogen (H ₂ ) or deuterium (D ₂ ) is introduced into the gas atmosphere.