CN1322565C - Semiconductor device comprising a thin oxide liner and method of manufacturing the same - Google Patents

Abstract

A method of forming a semiconductor device provides a gate electrode (32) on a substrate (30); and an oxide liner (34) that is less than 100 A in thickness on the substrate (30) and the gate electrode (32). A nitride layer (38) is formed on the oxide liner (34). The nitride layer (38) is etched to form nitride spacers (40), the etching stopping on the oxide liner (34). The thinner oxide liner (34), e.g., less than 100 A, prevents the liner (34) from acting as a sink for dopants during thermal processing so that the dopants in the source/drain extension regions (36) and the source/drain regions (42) remain in the substrate (30) during the thermal processing, thereby preventing degradation of transistor performance.

Description

Semiconductor device including thin oxide liner and method for making same

The technical field to which the invention belongs

The present invention relates to the field of a semiconductor device, and more specifically, relates to a structure of a doped region of a semiconductor device.

prior art

In recent decades, the semiconductor industry has undergone major changes through the application of semiconductor technology to manufacture electronic devices with small volume and high integration, and the most common semiconductor technology recently uses silicon as the material. Known procedures for fabricating such semiconductor devices include depositing a polysilicon gate layer on a silicon substrate. The polysilicon is then etched to the desired width. The etching is performed anisotropically to form substantially vertical sidewalls on the gate.

After this gate formation, implantation of source/drain extensions is usually performed next. The polysilicon gate overlies the substrate directly under the electrode whereby source/drain extensions are formed adjacent to the gate electrode.

After the source/drain extension implantation, sidewall spacers are formed on the gate. The source/drain regions are then generated by performing a deep source/drain implant procedure. A sidewall spacer formed on the gate acts as a shield to prevent the deep source/drain implant from being implanted directly into the substrate under the sidewall spacer. With this procedure, the deep source/drain region can be separated from the gate by the spacer. After the implantation procedure is completed, the implanted dopants are activated by an annealing step.

The sidewall spacers are typically formed on the sidewalls of the gate by etching a dielectric layer such as silicon nitride deposited on the substrate and gate. It is known to utilize a liner oxide deposited prior to the formation of the main dielectric layer as an etch stop layer during the etch of the silicon nitride sidewall spacers. Anisotropic etching of the dielectric layer etches the silicon nitride and terminates on the liner oxide, thereby preventing undue damage to the silicon substrate. The liner oxide is typically deposited to a thickness between about 100 angstroms and 300 angstroms, and is typically deposited to a thickness of 150 angstroms. A semiconductor device fabricated through the aforementioned processes is disclosed in FIG. 1 . The semiconductor device includes a substrate 10 , a gate 12 , a liner oxide 14 , silicon nitride spacers 16 , source/drain extensions 18 and deep source/drain regions 20 .

The inventors believe that problems related to dopant out-diffusion, especially from the source/drain extension 18 to the capping layer of the semiconductor device, will arise through the aforementioned structure or method. Out-diffusion of the dopant results in higher resistance source/drain and more sloped connections. Both of the aforementioned problems reduce the performance of the transistor. The oxide layer 14 used as an etch stop layer during the etching of the silicon nitride sidewall spacer serves as a dopant trench in a subsequent heat treatment process. Accordingly, the dopant can be out-diffused from the source/drain extension 18 to the oxide liner 14 . Therefore, although the etch stop layer can prevent the occurrence of faults during the spacer etching process, it cannot be used as a dopant trench for out-diffusion of dopants during the heat treatment process.

Contents of the invention

There is therefore a need for a semiconductor device structure and method that prevents dopant outdiffusion into the capping layer but provides an etch stop function to perform sidewall spacer etching without damaging the silicon substrate.

To solve the foregoing and other problems, embodiments of the present invention provide a method of forming a semiconductor device, including forming a gate on a substrate, and forming an oxide liner with a thickness less than 100 angstroms on the substrate and the gate. A nitride layer is deposited on the oxide liner, and the nitride layer is etched to form nitride spacers, the etching terminating on the oxide liner.

The oxide liner with a thickness of less than 100 angstroms is used to prevent dopant diffusion from occurring due to more dopant remaining in the substrate due to the lack of dopant trenches in the layer. In order to make the oxide liner continue to provide an etch stop function during the etch of the nitride layer, a specific dry etch can be used. In some preferred embodiments of the present invention, tetrafluoroethylene can be used during the spacer formation process. Methane (CF ₄ ) chemistry for dry etching. Prevention of dopant outdiffusion, especially in the source/drain extension region, will result in lower resistance source/drain and less sloped connections, thereby improving transistor performance.

The aforementioned problems can also be solved by providing a semiconductor device in an embodiment of the present invention, the semiconductor device including a substrate, a gate on the substrate, and an oxide liner on the substrate. The oxide liner has a thickness of about 100 Angstroms. Nitride sidewall spacers are formed on the oxide liner.

The foregoing and other features, aspects, and advantages of the present invention will be more apparent from the accompanying drawings and the following detailed description of the invention.

Description of drawings

FIG. 1 is a schematic diagram for showing a cross-sectional view of a semiconductor device constructed according to a conventional method;

FIG. 2 is a schematic diagram showing a first process stage of a semiconductor device manufactured according to an embodiment of the present invention;

FIG. 3 is a schematic diagram illustrating the structure of FIG. 2 after forming an oxide liner according to an embodiment of the present invention;

FIG. 4 is a schematic diagram illustrating the structure of FIG. 3 after performing source/drain extension implantation according to an embodiment of the present invention;

5 is a schematic diagram illustrating the structure of FIG. 4 after depositing a dielectric layer according to an embodiment of the present invention;

6 is a schematic diagram illustrating the structure of FIG. 5 after etching the dielectric layer to form sidewall spacers on the gate according to an embodiment of the present invention;

7 is a schematic diagram illustrating the structure of FIG. 6 after performing deep source/drain implantation to form source/drain regions of the semiconductor device according to an embodiment of the present invention; and

8a to 8c are schematic diagrams illustrating a form of a disposable spacer and an injection procedure using the disposable spacer according to an embodiment of the present invention.

Detailed ways

The present invention is used to cope with and solve the problem of lower transistor performance due to the out-diffusion of dopants into the capping layer during heat treatment, resulting in higher resistance source/drain and more inclined connections. To some extent, the present invention solves the aforementioned problems by forming a semiconductor device with a 100 angstrom thick oxide liner on the substrate and gate. The nitride layer formed on the oxide liner is etched to form nitride spacers, the etch being made to terminate on the oxide liner. The thinner oxide liner prevents outdiffusion of previously implanted dopants during the subsequent heat treatment, which does not provide large dopant trenches as in the prior art. Therefore, more dopants will remain in the substrate. This results in lower resistance source/drain and less sloped connections, thereby improving transistor performance.

FIG. 2 is used to show the structure of the semiconductor device in the first step of the process. In this schematic illustration, a gate 32 formed of a material such as polysilicon is formed on the substrate 30 . The structure of the polysilicon gate 32 or, for example, a metal gate structure can be formed by existing techniques such as depositing a polysilicon gate electrode on a silicon substrate after photolithography and etching steps. A gate oxide (not shown) may also be formed between the substrate 30 and the polysilicon gate 32 to form a gate dielectric layer.

As shown in FIG. 3, after the gate 32 is formed, an oxide liner 34 is deposited. A typical method for forming the oxide liner is through a plasma enhanced chemical vapor deposition (Plasma Enhanced Chemical Vapor Deposition; PECVD) method known to those skilled in the art. The oxide liner is deposited to a thickness of less than 100 angstroms, and in preferred embodiments the thickness may be between 20 angstroms and 70 angstroms. In a more preferred embodiment, the oxide liner is less than 45 Angstroms thick. The oxide liner 34 covers the gate 32 and the surface of the substrate 30 .

In FIG. 4 , source/drain extension implants are performed according to known methods to form source/drain extensions 36 adjacent to the gate 32 . The gate covers the substrate 30 to prevent dopants from being directly injected into the substrate 30 under the gate 32 . Although an embodiment of a sequence of process steps of the present invention is disclosed in FIGS. 3 and 4, in other embodiments the order of the steps in FIGS. The oxide liner 34 deposition is performed.

In FIG. 5 , a dielectric layer 38 , such as silicon nitride, is deposited on oxide liner 34 . The dielectric layer 38 may be deposited by known means such as chemical vapor deposition. Other materials may also be used in the dielectric layer 38 which etch more selectively than oxides.

In FIG. 6 , the nitridation in the dielectric layer 38 has been etched to form sidewall spacers 40 . During the nitride etch process, the oxide liner 34 must act as an etch stop to prevent damage to the substrate 30 . Since the oxide liner 34 is thinner than the prior art, care must be taken to prevent overetching. Accordingly, the sidewall spacers 40 can be formed by highly selective etching. The etch chemistry must be highly nitrogen-to-oxide selective in order for the thin liner to act as a suitable etch stop. Exemplary chemicals may include tetrafluoromethane (CF ₄ ). Other chemistries or recipes for etching, including plasma etching or reactive ion etching, etc. may include CF ₄ /HBr/HeO ₂ and CL ₂ /HBr/HeO ₂ .

FIG. 7 is a schematic diagram illustrating the structure of FIG. 6 after forming source/drain regions 42 by performing deep implantation and subsequent heat treatment. During the deep source/drain implantation process, the sidewall spacer 40 acts as a shield, whereby dopants are implanted directly into the substrate 30 under the sidewall spacer 40 . Known dose, implant energy, and thermal anneal parameters can be used.

During thermal firing, the thin oxide liner 34 prevents the source/drain region 42 from contacting the source due to the thickness of the oxide liner 34 substantially preventing the liner from becoming a dopant trench. / Out-diffusion of dopants in drain extension 36 . Therefore, more dopants remain in the substrate 30 . This overall effect reduces the resistance and less sloped connection of the source/drain regions 42 and source/drain extensions 36, thereby improving transistor performance.

In another aspect, highly etch selective films for deposition spacing procedures can be provided. In this procedure, germanium oxide is utilized as the disposable spacer material. This germanium oxide has a property of being dissolved in water. The germanium oxide can be formed by sputtering, or with subsequent oxidation by chemical vapor deposition of germanium. Spacers are then formed by anisotropic dry etching. FIG. 8 a is used to show a structure in which germanium oxide spacers 50 are deposited on a liner 52 made of oxide, nitride or other materials.

Disposable spacers can be used in different ways, one example method is to perform deep source/drain implants 54 after the spacers are formed, as shown in Figure 8b. Since the source/drain extensions formed after spacer removal cannot withstand higher temperatures, a higher temperature annealing process may then be performed than in the prior art. As shown in FIG. 8 c , the spacer 50 is then deposited and lightly doped drain (LDD) and low temperature annealing are performed.

The germanium oxide has the advantage that it can be safely removed in water and can be selected from other thin film materials currently used in semiconductor processing.

The above-mentioned embodiments are only illustrative to illustrate the principles and effects of the present invention, and are not intended to limit the present invention. Those skilled in the art can modify and change the above-mentioned embodiments without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention should be listed in the following claims.

Claims (7)

1. semiconductor device comprises:

Substrate (30);

Be formed on the grid (32) on this substrate (30);

Be formed on the oxide liner (34) on this substrate (30), this oxide liner (34) has the thickness less than 45 dusts;

Be formed on the nitride sidewall spacers (40) on this oxide liner (34); And

(36) and regions and source (42) are injected in the source/drain elongated area that is formed in this substrate (30).

2. method that forms semiconductor device comprises:

Go up formation grid (32) at substrate (30);

And in the last oxide liner (34) that forms thickness less than 45 dusts of this substrate (30) and grid (32);

Go up nitride layer (38) in this oxide liner (34); And

To form nitride spacers (40), this etch-stop is on this oxide liner (34) by this nitride layer of etching (38).

3. method as claimed in claim 2, wherein the step of this nitride layer of etching (38) comprises by having and makes this oxide liner (34) as the high nitrogen oxygen ratio of etch stop layer this nitride layer of etch chemistries dry-etching (38) optionally.

4. one kind prevents that alloy from from the method for injection zone outdiffusion to the semiconductor device cover layer, comprising:

Go up formation grid (32) at substrate (30);

Inject alloy to this substrate (30), inject (36) in this substrate (30), to form the source/drain elongated area;

Go up the oxide liner (34) of formation thickness at this substrate (30) less than 45 dusts;

Go up formation sidewall spacers (40) in this grid (32) and oxide liner (34); And

In this substrate (30), form regions and source (42).

5. method as claimed in claim 4, wherein in the step that forms this sidewall spacers (40), be included in this oxide liner (34) and go up nitride layer (38) with this grid (32), and by have make this oxide liner (34) as the high nitrogen oxygen ratio of etch stop layer optionally the etching chemistry prescription come anisotropic ground this nitride layer of dry-etching (38).

6. method as claimed in claim 5, wherein this etching chemistry prescription comprises CF ₄/ HBr/HeO ₂And Cl ₂/ HBr/HeO ₂In at least a.

7. method as claimed in claim 5, wherein this etching chemistry prescription comprises chemical substance CF ₄

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