JP2000223348A - Multilayer ceramic capacitor - Google Patents
Multilayer ceramic capacitorInfo
- Publication number
- JP2000223348A JP2000223348A JP11333798A JP33379899A JP2000223348A JP 2000223348 A JP2000223348 A JP 2000223348A JP 11333798 A JP11333798 A JP 11333798A JP 33379899 A JP33379899 A JP 33379899A JP 2000223348 A JP2000223348 A JP 2000223348A
- Authority
- JP
- Japan
- Prior art keywords
- multilayer
- capacitor
- multilayer ceramic
- internal electrode
- ceramic capacitor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000003985 ceramic capacitor Substances 0.000 title claims abstract description 71
- 239000003990 capacitor Substances 0.000 claims abstract description 99
- 239000000919 ceramic Substances 0.000 claims description 14
- 229910052751 metal Inorganic materials 0.000 claims description 7
- 239000002184 metal Substances 0.000 claims description 7
- 239000007772 electrode material Substances 0.000 claims description 6
- 239000003989 dielectric material Substances 0.000 claims description 4
- 208000031481 Pathologic Constriction Diseases 0.000 claims description 2
- 239000004020 conductor Substances 0.000 claims description 2
- 208000037804 stenosis Diseases 0.000 claims description 2
- 230000036262 stenosis Effects 0.000 claims description 2
- 238000003475 lamination Methods 0.000 claims 2
- 239000010410 layer Substances 0.000 abstract description 43
- 238000000034 method Methods 0.000 abstract description 6
- 238000010030 laminating Methods 0.000 abstract description 5
- 239000011241 protective layer Substances 0.000 abstract description 3
- 238000010586 diagram Methods 0.000 description 10
- 230000008878 coupling Effects 0.000 description 2
- 238000010168 coupling process Methods 0.000 description 2
- 238000005859 coupling reaction Methods 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 238000005245 sintering Methods 0.000 description 2
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 1
- 239000011230 binding agent Substances 0.000 description 1
- 230000003139 buffering effect Effects 0.000 description 1
- 230000001413 cellular effect Effects 0.000 description 1
- 239000002131 composite material Substances 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000002844 melting Methods 0.000 description 1
- 230000008018 melting Effects 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
- 230000005855 radiation Effects 0.000 description 1
- 229910052709 silver Inorganic materials 0.000 description 1
- 229910052715 tantalum Inorganic materials 0.000 description 1
- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 description 1
- 239000010936 titanium Substances 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
Landscapes
- Ceramic Capacitors (AREA)
- Fixed Capacitors And Capacitor Manufacturing Machines (AREA)
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は、電子機器の受動部
品として用いられる積層セラミックコンデンサに関す
る。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multilayer ceramic capacitor used as a passive component of electronic equipment.
【０００２】[0002]
【従来の技術】携帯電話機やノートパソコン等の電子機
器から発生する放射雑音を低減する方法として、回路基
板上のＬＳＩの動作に必要な電流を供給するコンデンサ
として、電流供給ライン経路の増加に伴うカップリング
で発生する雑音を抑制するためにカップリングを緩衝す
るためのデカップリング・コンデンサが用いられてい
る。2. Description of the Related Art As a method for reducing radiated noise generated from electronic equipment such as a cellular phone and a notebook personal computer, a capacitor for supplying a current necessary for the operation of an LSI on a circuit board is used as a current supply line path increases. A decoupling capacitor for buffering the coupling is used to suppress noise generated by the coupling.
【０００３】デカップリング・コンデンサの入れ方とし
て、消費電流や駆動電流がほとんど変化しないＴＴＬ
ＩＣの場合、ＴＴＬ ＩＣ１個当たり２．２μＦを２〜
３個入れていた。また、回路構成としては、電荷供給の
コンデンサとして、大容量で高周波帯域で周波数特性が
悪いタンタルコンデンサと低容量で高周波特性の良い積
層セラミックコンデンサの組み合わせが一般的である。As a method of inserting a decoupling capacitor, TTL in which current consumption and drive current hardly change is considered.
In the case of IC, 2.2 μF per TTL IC
I had three in it. Further, as a circuit configuration, a combination of a tantalum capacitor having a large capacity and a poor frequency characteristic in a high frequency band and a multilayer ceramic capacitor having a low capacity and a good high frequency characteristic is generally used as a capacitor for supplying a charge.
【０００４】[0004]
【発明が解決しようとする課題】しかしながら、動作周
波数が高いＬＳＩの場合、ＬＳＩから離れた位置に実装
されたり、静電容量が少ない場合、遠くのデカップリン
グ・コンデンサから電荷供給されるため、電流ラインが
長くなりデカップリング効果が得られなくなる。また、
隣接したコンデンサの距離と、そのラインを流れる高周
波電流の波長が一致し、共振現象を引き起こし放射雑音
が大きくなるという問題点があった。However, in the case of an LSI having a high operating frequency, the LSI is mounted at a position distant from the LSI, and when the capacitance is small, electric charge is supplied from a distant decoupling capacitor. The line becomes longer and the decoupling effect cannot be obtained. Also,
There is a problem that the distance between adjacent capacitors and the wavelength of the high-frequency current flowing through the line coincide with each other, causing a resonance phenomenon and increasing radiation noise.
【０００５】上述したことから、回路基板上に最低２個
のコンデンサを実装する必要があり、その実装も共振現
象を引き起こさない距離が必要であるため、実装時の部
品点数が多く、かつ、実装面積が大きくなるという問題
点があった。[0005] As described above, it is necessary to mount at least two capacitors on a circuit board, and the mounting requires a distance that does not cause a resonance phenomenon. There was a problem that the area became large.
【０００６】また、２つ以上の容量の異なる積層コンデ
ンサ部を有する１チップにした積層セラミックコンデン
サとして、実願平５−２１４２９や特願平７−１４２２
８５で開示されている。[0006] Japanese Patent Application No. Hei 5-21429 and Japanese Patent Application No. Hei 7-1422 disclose a single-chip multilayer ceramic capacitor having two or more multilayer capacitor parts having different capacities.
85.
【０００７】いずれの方法もある程度の効果は上がって
いるが、最近の小型、大容量及び高周波化に対して効果
が不十分であった。[0007] Each of these methods has been effective to some extent, but is inadequate for recent miniaturization, large capacity and high frequency operation.
【０００８】本発明の目的は、高周波特性が良く、大容
量と低容量の積層セラミックコンデンサ部を有した１チ
ップ部品とし、実装時の部品点数及び実装面積低減を図
るための積層セラミックコンデンサを提供する事にあ
る。An object of the present invention is to provide a monolithic ceramic capacitor which is a one-chip component having a high-frequency characteristic, a large-capacity and a low-capacity monolithic ceramic capacitor part, and which reduces the number of components and the mounting area during mounting. To do.
【０００９】[0009]
【課題を解決するための手段】本発明によれば、誘電体
セラミック層と低抵抗導体からなる内部電極層とを交互
に複数層積み重ねて形成する積層体に外部電極を設けて
なる積層セラミックコンデンサにおいて、容量の異なる
２つ以上の積層コンデンサ部を有し、厚み方向に対して
隣り合う積層コンデンサ部の一方は、他方の積層コンデ
ンサ部の積層間隔が同じかそれよりも広い間隔で形成さ
れていることを特徴とする積層セラミックコンデンサが
得られる。According to the present invention, a multilayer ceramic capacitor is provided in which external electrodes are provided on a laminate formed by alternately stacking a plurality of dielectric ceramic layers and internal electrode layers made of a low-resistance conductor. Has two or more multilayer capacitor sections having different capacities, and one of the multilayer capacitor sections adjacent to each other in the thickness direction is formed at the same or wider interval than the other multilayer capacitor sections. Thus, a multilayer ceramic capacitor is obtained.
【００１０】さらに、本発明によれば、前記一方の積層
コンデンサ部と前記他方の積層コンデンサ部との間隔が
０．１５ｍｍ以上離れていることを特徴とする積層セラ
ミックコンデンサが得られる。Further, according to the present invention, there is provided a multilayer ceramic capacitor wherein the distance between the one multilayer capacitor portion and the other multilayer capacitor portion is at least 0.15 mm.
【００１１】さらに、本発明によれば、前記一方の積層
コンデンサ部と前記他方の積層コンデンサ部との前記間
隔部を挟んで対向する電極を同極性にしたことを特徴と
する積層セラミックコンデンサが得られる。Further, according to the present invention, there is provided a multilayer ceramic capacitor in which electrodes facing each other across the gap between the one multilayer capacitor portion and the other multilayer capacitor portion have the same polarity. Can be
【００１２】さらに、本発明によれば、前記他方の積層
コンデンサ部の容量と内部電極層の電気抵抗が前記一方
の積層コンデンサ部より大きくなっていることを特徴と
する積層セラミックコンデンサが得られる。Further, according to the present invention, there is provided a multilayer ceramic capacitor characterized in that the capacitance of the other multilayer capacitor portion and the electrical resistance of the internal electrode layer are larger than those of the one multilayer capacitor portion.
【００１３】さらに、本発明によれば、前記他方の積層
コンデンサ部の内部電極層の電極材料は低抵抗金属に、
請求項１記載の誘電体材料を１〜１０％添加して電気抵
抗を高めることを特徴とする積層セラミックコンデンサ
が得られる。Further, according to the present invention, the electrode material of the internal electrode layer of the other multilayer capacitor portion is a low-resistance metal,
A multilayer ceramic capacitor characterized by increasing electric resistance by adding 1 to 10% of the dielectric material according to claim 1 is obtained.
【００１４】さらに、本発明によれば、前記他方の積層
コンデンサ部の内部電極パターンの外部電極と電気的に
接合する部分に狭窄、スリット等を設けて電気抵抗を高
めることを特徴とする積層セラミックコンデンサが得ら
れる。Further, according to the present invention, a multilayer ceramic characterized by providing a constriction, a slit or the like in a portion of the other multilayer capacitor portion electrically connected to an external electrode of an internal electrode pattern to increase electric resistance. A capacitor is obtained.
【００１５】さらに、本発明によれば、前記一方の積層
コンデンサ部の容量と内部電極層の電気抵抗が前記他方
の積層コンデンサ部より小さくなっていることを特徴と
する積層セラミックコンデンサが得られる。Further, according to the present invention, there is provided a multilayer ceramic capacitor wherein the capacitance of the one multilayer capacitor portion and the electric resistance of the internal electrode layer are smaller than those of the other multilayer capacitor portion.
【００１６】さらに、本発明によれば、前記一方の積層
コンデンサ部の内部電極層は電極材料の低抵抗金属の厚
みを前記他方の積層コンデンサ部の内部電極層の厚みを
増すことで電気抵抗を下げることを特徴とする積層セラ
ミックコンデンサが得られる。Further, according to the present invention, the internal electrode layer of the one multilayer capacitor portion has an electric resistance by increasing the thickness of the low-resistance metal of the electrode material by increasing the thickness of the internal electrode layer of the other multilayer capacitor portion. Thus, a multilayer ceramic capacitor characterized by lowering is obtained.
【００１７】又、本発明によれば、誘電体セラミック層
と低抵抗金属からなる内部電極層とを交互に複数層積み
重ねて形成する積層体に外部電極を設けてなる積層セラ
ミックコンデンサにおいて、積層体の内部電極が積層方
向と直交する方向に分離され２つ以上の容量の異なった
積層コンデンサ部を有していることを特徴とする積層セ
ラミックコンデンサが得られる。Further, according to the present invention, there is provided a multilayer ceramic capacitor in which external electrodes are provided on a laminate formed by alternately stacking a plurality of dielectric ceramic layers and internal electrode layers made of a low-resistance metal. Wherein the internal electrodes are separated in a direction perpendicular to the laminating direction and have two or more laminated capacitor portions having different capacities.
【００１８】さらに、本発明によれば、積層方向と直交
する方向に対して隣り合う積層コンデンサ部の電極間隔
が０．０５ｍｍ以上離れていることを特徴とする積層セ
ラミックコンデンサが得られる。Further, according to the present invention, there is provided a multilayer ceramic capacitor characterized in that adjacent multilayer capacitor portions are separated from each other by a distance of 0.05 mm or more in a direction perpendicular to the laminating direction.
【００１９】さらに、本発明によれば、前記隣り合う積
層コンデンサの内、容量の小さなコンデンサ部の内部電
極パターンの面積は、容量の大きい方の積層コンデンサ
部の内部電極パターンの面積よりも小さくすることを特
徴とする積層セラミックコンデンサが得られる。Further, according to the present invention, of the adjacent multilayer capacitors, the area of the internal electrode pattern of the capacitor part having the smaller capacitance is smaller than the area of the internal electrode pattern of the multilayer capacitor part having the larger capacitance. Thus, a multilayer ceramic capacitor is obtained.
【００２０】さらに、本発明によれば、前記隣り合う積
層コンデンサの内、容量の大きなコンデンサ部の内部電
極パターンの外部電極と電気的に接合する部分の断面積
を共通電極部分よりも小さくすること（狭窄、スリット
等）によって電気抵抗を高めることを特徴とする積層セ
ラミックコンデンサが得られる。Further, according to the present invention, the cross-sectional area of a portion of the adjacent multilayer capacitor electrically connected to the external electrode of the internal electrode pattern of the capacitor portion having a large capacitance is made smaller than that of the common electrode portion. (Stenosis, slits, etc.) can provide a multilayer ceramic capacitor characterized by increasing electric resistance.
【００２１】[0021]
【作用】以上のように構成した積層セラミックコンデン
サによれば、高周波特性が良く、大容量と低容量の積層
セラミックコンデンサ部を有した１チップ部品とし、実
装時の部品点数及び実装面積低減を図るための積層セラ
ミックコンデンサである。According to the multilayer ceramic capacitor configured as described above, the high frequency characteristics are good, and a one-chip component having a large-capacity and low-capacity multilayer ceramic capacitor portion is formed, and the number of components and the mounting area during mounting are reduced. For a multilayer ceramic capacitor.
【００２２】[0022]
【発明の実施の形態】以下に、本発明の積層セラミック
コンデンサの一実施の形態について図１を参照して説明
する。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the multilayer ceramic capacitor according to the present invention will be described below with reference to FIG.
【００２３】図１（ａ）は、本発明の一実施の形態に係
わる積層セラミックコンデンサの外観図である。積層セ
ラミックコンデンサは誘電体層１と内部電極層２を交互
に積層して脱バインダ、焼結を行い得られたセラミック
焼結体１０に外部電極６によって電気的に接続をしたも
のである。FIG. 1A is an external view of a multilayer ceramic capacitor according to an embodiment of the present invention. The multilayer ceramic capacitor is obtained by alternately laminating dielectric layers 1 and internal electrode layers 2 and removing the binder and sintering, and electrically connected to a ceramic sintered body 10 obtained by external electrodes 6.
【００２４】図１（ｂ）は、図１（ａ）のＡ−Ａ′断面
図である。この積層セラミックコンデンサは、誘電体層
１と内部電極層２を交互に積層した２つの積層コンデン
サ部３と４が積層体厚み方向に所定の容量部間隔７をお
いて離されて、その外側に設けた誘電体による２つの保
護層５と、外部電極６から構成されている。ここで、積
層コンデンサ部３は、もう一方の積層コンデンサ部４に
比べて、誘電体層の厚みが薄く多層構造であるので、高
容量を有する。また、２つの積層コンデンサ部３と４の
隣り合う内部電極の方向が同一方向となっている。誘電
体層１は鉛リラクサ系及びチタバリ系、単体或いは複合
系どちらでもよい。誘電率εは１００〜２００００とす
る。内部電極層２は低融点金属であるＡｇ、Ａｇ−Ｐ
ｄ、Ｎｉ、Ｃｕ等の誘電体材料と同時焼成が可能なもの
を使用した。FIG. 1B is a sectional view taken along the line AA 'of FIG. 1A. In this multilayer ceramic capacitor, two multilayer capacitor portions 3 and 4 in which dielectric layers 1 and internal electrode layers 2 are alternately laminated are separated by a predetermined capacitance portion interval 7 in the thickness direction of the multilayer body, and are provided on the outside thereof. It comprises two protective layers 5 made of a provided dielectric and external electrodes 6. Here, the multilayer capacitor unit 3 has a higher capacity because the thickness of the dielectric layer is smaller than that of the other multilayer capacitor unit 4 and has a multilayer structure. The directions of the internal electrodes adjacent to the two multilayer capacitor portions 3 and 4 are the same. The dielectric layer 1 may be a lead relaxer-based or titanium-based, single or composite type. The dielectric constant ε is set to 100 to 20,000. The internal electrode layer 2 is made of a low melting point metal such as Ag or Ag-P.
A material that can be fired simultaneously with a dielectric material such as d, Ni, or Cu was used.
【００２５】次に、本発明の積層セラミックコンデンサ
の周波数−インピーダンス特性について説明する。図２
は、図１の積層構造を有する積層セラミックコンデンサ
の等価回路を示したものである。コンデンサの等価回路
は一般的に直列のＣ、Ｌ、Ｒで現せられ、積層セラミッ
クコンデンサは外部電極６で並列接続されるような形と
なる。Next, the frequency-impedance characteristics of the multilayer ceramic capacitor of the present invention will be described. FIG.
1 shows an equivalent circuit of the multilayer ceramic capacitor having the multilayer structure of FIG. The equivalent circuit of the capacitor is generally represented by C, L, and R in series, and the multilayer ceramic capacitor has such a form that it is connected in parallel by the external electrode 6.
【００２６】積層コンデンサ部３と４の等価回路定数は
以下のようになる。The equivalent circuit constants of the multilayer capacitor units 3 and 4 are as follows.
【００２７】（１）積層コンデンサ部３：Ｃ1 ＝１０μ
Ｆ、Ｌ1 ＝１．２ｎＨ、Ｒ1 ＝１０ｍΩ （２）積層コンデンサ部４：Ｃ2 ＝０．１μＦ、Ｌ2 ＝
１．２ｎＨ、Ｒ2 ＝７５ｍΩ 図３（ａ）〜（ｃ）は、図３の等価回路定数になるよう
に設計し、図１の積層構造を有する積層セラミックコン
デンサのコンデンサ部の容量部間隔を変化させたときの
周波数−インピーダンス特性を示す。積層セラミックコ
ンデンサの素子形状は長さ３．２ｍｍ、幅が２．５ｍｍ
のものを使用し、誘電体層１と内部電極層２を交互に積
層した２つの積層コンデンサ部３，４の静電容量をそれ
ぞれ１０μＦと０．１μＦとなるように積層数及び誘電
体層厚みを設計した。このとき、２つの積層コンデンサ
部３と４の距離を変化させる。ここで、誘電体層の小部
の誘電体層厚みが２つの積層コンデンサ部３，４の距離
よりも大きくなっても良い。なお、積層セラミックコン
デンサの共振周波数およびインピーダンス値は、使用す
る材料の誘電率、抵抗率および積層構造によっても変化
する。(1) Multilayer capacitor section 3: C1 = 10 μm
F, L1 = 1.2 nH, R1 = 10 mΩ (2) Multilayer capacitor part 4: C2 = 0.1 μF, L2 =
1.2 nH, R2 = 75 mΩ FIGS. 3 (a) to 3 (c) are designed to have the equivalent circuit constants shown in FIG. 3, and change the capacitance interval of the capacitor portion of the multilayer ceramic capacitor having the multilayer structure of FIG. 4 shows the frequency-impedance characteristics when this is performed. The element shape of the multilayer ceramic capacitor is 3.2 mm in length and 2.5 mm in width
The number of layers and the thickness of the dielectric layer are set so that the capacitance of the two multilayer capacitor sections 3 and 4 in which the dielectric layers 1 and the internal electrode layers 2 are alternately laminated is 10 μF and 0.1 μF, respectively. Was designed. At this time, the distance between the two multilayer capacitor units 3 and 4 is changed. Here, the dielectric layer thickness of the small portion of the dielectric layer may be larger than the distance between the two multilayer capacitor sections 3 and 4. Note that the resonance frequency and the impedance value of the multilayer ceramic capacitor also change depending on the dielectric constant, the resistivity, and the multilayer structure of the material used.
【００２８】図３の結果より、２つの積層コンデンサ部
３と４の距離が狭い場合、周波数−インピーダンス特性
は、積層コンデンサ部の大部に支配され、１個の共振点
しか、観測されないが２つの隣り合う積層コンデンサ部
の厚み方向の距離が０．１５ｍｍ以上になると、それぞ
れの積層コンデンサ部の共振点が観測されるようにな
る。従って、本発明の積層セラミックコンデンサによれ
ば、広帯域で低いインピーダンス領域を確保できること
がわかる。According to the results shown in FIG. 3, when the distance between the two multilayer capacitor sections 3 and 4 is small, the frequency-impedance characteristic is dominated by the majority of the multilayer capacitor section, and only one resonance point is observed. When the distance in the thickness direction between two adjacent multilayer capacitor portions is 0.15 mm or more, resonance points of the respective multilayer capacitor portions are observed. Therefore, according to the multilayer ceramic capacitor of the present invention, it can be seen that a low impedance region can be secured in a wide band.
【００２９】次に、本発明の積層セラミックコンデンサ
の容量の大きな積層コンデンサ部の電気抵抗を大きくし
たときの周波数−インピーダンス特性について説明す
る。図４は、図２の等価回路定数において積層コンデン
サ部３の抵抗値Ｒ1 ＝１００ｍΩにしたときの周波数−
インピーダンス特性を示す。点線部は、積層コンデンサ
部３の抵抗値Ｒ1 ＝１００ｍΩで図３（ｃ）の周波数−
インピーダンス特性である。実線部は積層コンデンサ部
３の抵抗値Ｒ1 ＝１００ｍΩにしたときの周波数−イン
ピーダンス特性で、通常は点線部の様に共振点を有する
ものが抵抗を大きくしているために、その設定の抵抗値
（１００ｍΩ）でカットされた状態となり、平坦な形で
かつ広帯域なインピーダンス特性を示している。Next, the frequency-impedance characteristic when the electric resistance of the multilayer capacitor portion of the multilayer ceramic capacitor of the present invention having a large capacity is increased will be described. FIG. 4 is a graph showing the relationship between the frequency when the resistance value R1 of the multilayer capacitor unit 3 is set to 100 mΩ in the equivalent circuit constant of FIG.
4 shows impedance characteristics. The dotted line indicates that the resistance value R1 of the multilayer capacitor unit 3 is 100 mΩ and the frequency of FIG.
It is an impedance characteristic. The solid line indicates the frequency-impedance characteristic when the resistance value R1 of the multilayer capacitor unit 3 is set to 100 mΩ. Usually, a resistor having a resonance point as indicated by a dotted line increases the resistance. (100 mΩ), showing a flat shape and wide-band impedance characteristics.
【００３０】このような、平坦な形でかつ広帯域なイン
ピーダンス特性を得るためには内部電極層の抵抗値を制
御する必要がある。抵抗値を制御する方法として、大き
な容量の積層セラミック部の内部電極材を、小さな容量
の積層セラミック部と変化させてある。内部電極部材内
に誘電体材料を１〜１０％添加することによって、積層
構造及び内部電極面積を変化させることなく抵抗値を制
御することができる。但し、２０％以上添加すると、焼
結時に内部電極が断線状態なってしまったり、インピー
ダンス特性が悪くなってしまう。In order to obtain such a flat and wide-band impedance characteristic, it is necessary to control the resistance value of the internal electrode layer. As a method of controlling the resistance value, the internal electrode material of the large-capacity laminated ceramic portion is changed to a small-capacity laminated ceramic portion. By adding 1 to 10% of a dielectric material into the internal electrode member, the resistance value can be controlled without changing the laminated structure and the internal electrode area. However, if added in an amount of 20% or more, the internal electrodes will be disconnected during sintering, or the impedance characteristics will deteriorate.
【００３１】また、大きな容量の積層セラミック部の内
部電極材と小さな容量の積層セラミック部と一緒にする
方法として、大きな容量の積層セラミック部の内部電極
パターンと外部電極パターンとを電気的に接合する部分
に、図５（ａ）、（ｂ）、（ｃ）のように狭窄、スリッ
トとを設けて抵抗値を大きくすることができた。図５は
図１の積層セラミックコンデンサを厚さ方向から１層だ
けを抽出したものである。誘電体層１の上に内部電極層
２が形成され、内部電極層２の外部電極と電気的に接合
される部分に狭窄部１１、スリット部１２が形成されて
いる。大きな容量の積層セラミック部の内部電極の積層
構造は、各層、１〜数層おきに図５の内部電極パターン
を必要な抵抗値になるように構成する。As a method of combining the internal electrode material of the large-capacity laminated ceramic part with the small-capacity laminated ceramic part, the internal electrode pattern and the external electrode pattern of the large-capacity laminated ceramic part are electrically connected. As shown in FIGS. 5A, 5B, and 5C, constrictions and slits were provided in the portion to increase the resistance value. FIG. 5 shows the multilayer ceramic capacitor of FIG. 1 in which only one layer is extracted from the thickness direction. The internal electrode layer 2 is formed on the dielectric layer 1, and a constriction portion 11 and a slit portion 12 are formed in a portion of the internal electrode layer 2 which is electrically connected to an external electrode. The laminated structure of the internal electrodes of the large-capacity laminated ceramic portion is configured such that the internal electrode pattern of FIG.
【００３２】次に、本発明の積層セラミックコンデンサ
の容量の小さな積層コンデンサ部の電気抵抗を小さくし
たときの周波数−インピーダンス特性について説明す
る。図６は、図２の等価回路定数において積層コンデン
サ部４の抵抗値Ｒ1 ＝３０ｍΩにしたときの周波数−イ
ンピーダンス特性を示す。点線部は、積層コンデンサ部
４の抵抗値Ｒ1 ＝７５ｍΩで図３（ｃ）の周波数−イン
ピーダンス特性である。実線部は積層コンデンサ部４の
抵抗値Ｒ1 ＝３０ｍΩにしたときの周波数−インピーダ
ンス特性で、図３（ｃ）の特性と比較して高周波側のイ
ンピーダンスが低くなっていることがわかる。Next, the frequency-impedance characteristic when the electric resistance of the multilayer capacitor part of the multilayer ceramic capacitor of the present invention having a small capacity is reduced will be described. FIG. 6 shows frequency-impedance characteristics when the resistance value R1 of the multilayer capacitor unit 4 is set to 30 mΩ in the equivalent circuit constant of FIG. The dotted line indicates the frequency-impedance characteristic of FIG. 3C when the resistance value R1 of the multilayer capacitor unit 4 is 75 mΩ. The solid line indicates the frequency-impedance characteristic when the resistance value R1 of the multilayer capacitor unit 4 is set to 30 mΩ. It can be seen that the impedance on the high frequency side is lower than the characteristic shown in FIG.
【００３３】次に、本発明の他の実施の形態に係わる積
層セラミックコンデンサの図７（ａ）は、本発明の積層
セラミックコンデンサの外観図である。図７（ｂ）は、
本発明に係わる積層セラミックコンデンサのＢ−Ｂ′断
面図である。この積層セラミックコンデンサは、誘電体
層１と内部電極層２を交互に積層し、積層方向と直交す
る方向に分離された２つ積層コンデンサ部８と９が所定
の距離に離されて、その外側に設けた２つの保護層５
と、外部電極６から構成されている。ここで、積層コン
デンサ部８は、もう一方の積層コンデンサ部９に比べ
て、内部電極層の幅を狭く設計し、同一の積層数で、低
容量を有する。Next, FIG. 7A of a multilayer ceramic capacitor according to another embodiment of the present invention is an external view of the multilayer ceramic capacitor of the present invention. FIG. 7 (b)
It is a BB 'sectional view of the multilayer ceramic capacitor concerning the present invention. In this multilayer ceramic capacitor, dielectric layers 1 and internal electrode layers 2 are alternately laminated, and two laminated capacitor portions 8 and 9 separated in a direction orthogonal to the laminating direction are separated by a predetermined distance, and the outer portions thereof are separated from each other. Two protective layers 5 provided on
And an external electrode 6. Here, the multilayer capacitor unit 8 is designed so that the width of the internal electrode layer is smaller than that of the other multilayer capacitor unit 9, and has the same number of layers and low capacitance.
【００３４】図８は図７の積層セラミックコンデンサを
厚さ方向から１層だけを抽出したものである。誘電体層
１の上に内部電極層２が形成され、内部電極層２の外部
電極と電気的に接合する部分に狭窄部１１、スリット部
１２が形成されている。大きな容量の積層セラミック部
の内部電極の積層構造は、各層、１〜数層おきに図６の
内部電極パターンを必要な抵抗値になるように構成す
る。FIG. 8 shows the multilayer ceramic capacitor of FIG. 7 in which only one layer is extracted from the thickness direction. An internal electrode layer 2 is formed on the dielectric layer 1, and a constriction portion 11 and a slit portion 12 are formed in a portion of the internal electrode layer 2 which is electrically connected to an external electrode. The laminated structure of the internal electrodes of the large-capacity laminated ceramic portion is configured such that the internal electrode pattern of FIG.
【００３５】以上の結果により、積層コンデンサ部の間
隔及び各積層コンデンサ部の電気抵抗を設定すること
で、様々な形態の広帯域な周波数−インピーダンス特性
が得られる。According to the above results, by setting the interval between the multilayer capacitor portions and the electric resistance of each multilayer capacitor portion, various forms of frequency-impedance characteristics can be obtained.
【００３６】[0036]
【発明の効果】以上、説明したように本発明によれば、
高周波特性が良く、実装時のコンデンサ部品点数を少な
くできる為、実装面積を低減することができる積層セラ
ミックコンデンサを提供することが可能となった。As described above, according to the present invention,
Since high-frequency characteristics are good and the number of capacitor components during mounting can be reduced, it has become possible to provide a multilayer ceramic capacitor capable of reducing the mounting area.
【図１】（ａ）は本発明の一実施形態に係わる積層セラ
ミックコンデンサの外観図であり、（ｂ）は（ａ）のＡ
−Ａ′断面図である。FIG. 1A is an external view of a multilayer ceramic capacitor according to an embodiment of the present invention, and FIG.
It is -A 'sectional drawing.
【図２】本発明の積層セラミックコンデンサの等価回路
を示した図である。FIG. 2 is a diagram showing an equivalent circuit of the multilayer ceramic capacitor of the present invention.
【図３】図１に示した積層セラミックコンデンサの周波
数−インピーダンス特性を示す図であり、（ａ）は、積
層コンデンサ部の間隔が０．１５ｍｍ未満の場合の周波
数−インピーダンス特性を示す図であり、（ｂ）は、積
層コンデンサ部の間隔が、０．１５ｍｍ以上、０．３ｍ
ｍ未満の場合の周波数−インピーダンス特性を示す図で
あり、（ｃ）は、積層コンデンサ部の距離が、０．３ｍ
ｍ以上の場合の周波数−インピーダンス特性を示す図で
ある。3A and 3B are diagrams illustrating frequency-impedance characteristics of the multilayer ceramic capacitor illustrated in FIG. 1, and FIG. 3A is a diagram illustrating frequency-impedance characteristics when a distance between multilayer capacitor portions is less than 0.15 mm; , (B) show that the interval between the multilayer capacitor portions is 0.15 mm or more and 0.3 m
FIG. 7C is a diagram illustrating frequency-impedance characteristics when the distance is less than 0.3 m.
It is a figure which shows the frequency-impedance characteristic in case of m or more.
【図４】図１に示した積層セラミックコンデンサの周波
数−インピーダンス特性を示す図であり、点線部は、積
層コンデンサ部の距離が、０．３ｍｍ以上の場合の周波
数−インピーダンス特性を示す図であり、実線部は大き
い容量部の内部電極層の抵抗値を大きくした場合の周波
数−インピーダンス特性を示す図である。4 is a diagram illustrating frequency-impedance characteristics of the multilayer ceramic capacitor illustrated in FIG. 1, and a dotted line portion is a diagram illustrating frequency-impedance characteristics when the distance between the multilayer capacitor portions is 0.3 mm or more. The solid line shows the frequency-impedance characteristics when the resistance value of the internal electrode layer of the large capacitance part is increased.
【図５】本発明の図１に示した積層セラミックコンデン
サを厚さ方向から１層だけを抽出したものであり、
（ａ）、（ｂ）は内部電極パターンと電気的に外部電極
と接続する部分に狭窄部を設けたものであり、（ｃ）は
内部電極パターンと電気的に外部電極と接続する部分に
スリット部を設けた内部電極パターンを示す図である。FIG. 5 is a diagram in which only one layer is extracted from the thickness direction of the multilayer ceramic capacitor shown in FIG. 1 of the present invention;
(A) and (b) are provided with a constriction at a portion electrically connected to the internal electrode pattern and the external electrode, and (c) is a slit provided at a portion electrically connected to the internal electrode pattern and the external electrode. FIG. 6 is a view showing an internal electrode pattern provided with a portion.
【図６】図１に示した積層セラミックコンデンサの周波
数−インピーダンス特性を示す図であり、点線部は、積
層コンデンサ部の距離が、０．３ｍｍ以上の場合の周波
数−インピーダンス特性を示す図であり、実線部は小さ
い容量部の内部電極層の抵抗値を小さくした場合の周波
数−インピーダンス特性を示す図である。6 is a diagram illustrating frequency-impedance characteristics of the multilayer ceramic capacitor illustrated in FIG. 1, and a dotted line portion is a diagram illustrating frequency-impedance characteristics when the distance between the multilayer capacitor portions is 0.3 mm or more. The solid line shows the frequency-impedance characteristics when the resistance of the internal electrode layer of the small capacitor is reduced.
【図７】（ａ）は本発明の他の実施形態に係わる積層セ
ラミックコンデンサの外観図であり、（ｂ）は（ａ）の
Ｂ−Ｂ′断面図である。7A is an external view of a multilayer ceramic capacitor according to another embodiment of the present invention, and FIG. 7B is a cross-sectional view taken along line BB ′ of FIG.
【図８】本発明の図７に示した積層セラミックコンデン
サを厚さ方向から１層だけを抽出したものであり、
（ａ）、（ｂ）は内部電極パターンと電気的に外部電極
と接続する部分に狭窄部を設けたものであり、（ｃ）は
内部電極パターンと電気的に外部電極と接続する部分に
スリット部を設けた内部電極パターンを示す図である。FIG. 8 is a diagram in which only one layer is extracted from the thickness direction of the multilayer ceramic capacitor shown in FIG. 7 of the present invention;
(A) and (b) are provided with a constriction at a portion electrically connected to the internal electrode pattern and the external electrode, and (c) is a slit provided at a portion electrically connected to the internal electrode pattern and the external electrode. FIG. 6 is a view showing an internal electrode pattern provided with a portion.
１ 誘電体層 ２ 内部電極層 ３，４ 積層コンデンサ部 ５ 誘電体による保護層 ６ 外部電極 ７ 容量部間隔 ８，９ 積層コンデンサ部 １０ セラミック焼結体 １１ 狭窄部 １２ スリット部 DESCRIPTION OF SYMBOLS 1 Dielectric layer 2 Internal electrode layer 3, 4 Multilayer capacitor part 5 Dielectric protection layer 6 External electrode 7 Capacitance part space 8, 9 Multilayer capacitor part 10 Ceramic sintered body 11 Narrow part 12 Slit part
Claims (12)
る内部電極層とを交互に複数層積み重ねて形成する積層
体に外部電極を設けてなる積層セラミックコンデンサに
おいて、容量の異なる２つ以上の積層コンデンサ部を有
し、厚み方向に対して隣り合う積層コンデンサ部の一方
は、他方の積層コンデンサ部の積層間隔が同じかそれよ
りも広い間隔で形成されていることを特徴とする積層セ
ラミックコンデンサ。1. A multilayer ceramic capacitor in which external electrodes are provided on a laminate formed by alternately stacking a plurality of dielectric ceramic layers and internal electrode layers made of a low-resistance conductor, wherein two or more laminates having different capacitances are provided. A multilayer ceramic capacitor having a capacitor portion, wherein one of the multilayer capacitor portions adjacent to each other in the thickness direction is formed so that the other multilayer capacitor portions have the same or larger lamination interval.
サにおいて、前記一方の積層コンデンサ部と前記他方の
積層コンデンサ部との間隔が０．１５ｍｍ以上離れてい
ることを特徴とする積層セラミックコンデンサ。2. The multilayer ceramic capacitor according to claim 1, wherein a distance between the one multilayer capacitor portion and the other multilayer capacitor portion is 0.15 mm or more.
サにおいて、前記一方の積層コンデンサ部と前記他方の
積層コンデンサ部との前記間隔部を挟んで対向する電極
を同極性にしたことを特徴とする積層セラミックコンデ
ンサ。3. The multilayer ceramic capacitor according to claim 1, wherein electrodes facing each other across said space between said one multilayer capacitor portion and said other multilayer capacitor portion have the same polarity. Ceramic capacitors.
サにおいて、前記他方の積層コンデンサ部の容量と内部
電極層の電気抵抗が前記一方の積層コンデンサ部より大
きくなっていることを特徴とする積層セラミックコンデ
ンサ。4. The multilayer ceramic capacitor according to claim 1, wherein the capacitance of the other multilayer capacitor and the electrical resistance of the internal electrode layer are larger than those of the one multilayer capacitor. .
サにおいて、前記他方の積層コンデンサ部の内部電極層
の電極材料は低抵抗金属に、請求項１記載の誘電体材料
を１〜１０％添加して電気抵抗を高めることを特徴とす
る積層セラミックコンデンサ。5. The multilayer ceramic capacitor according to claim 4, wherein the electrode material of the internal electrode layer of the other multilayer capacitor portion is a low-resistance metal and the dielectric material according to claim 1 is added by 1 to 10%. Multilayer ceramic capacitors characterized by increasing electrical resistance.
サにおいて、前記他方の積層コンデンサ部の内部電極パ
ターンの外部電極と電気的に接合する部分に狭窄、スリ
ット等を設けて電気抵抗を高めることを特徴とする積層
セラミックコンデンサ。6. The multilayer ceramic capacitor according to claim 4, wherein a constriction, a slit, or the like is provided in a portion of the other multilayer capacitor portion electrically connected to an external electrode of the internal electrode pattern to increase electric resistance. To be a multilayer ceramic capacitor.
サにおいて、前記一方の積層コンデンサ部の容量と内部
電極層の電気抵抗が前記他方の積層コンデンサ部より小
さくなっていることを特徴とする積層セラミックコンデ
ンサ。7. The multilayer ceramic capacitor according to claim 1, wherein the capacitance of the one multilayer capacitor portion and the electric resistance of the internal electrode layer are smaller than those of the other multilayer capacitor portion. .
サにおいて、前記一方の積層コンデンサ部の内部電極層
は電極材料の低抵抗金属の厚みを前記他方の積層コンデ
ンサ部の内部電極層の厚みを増すことで電気抵抗を下げ
ることを特徴とする積層セラミックコンデンサ。8. The multilayer ceramic capacitor according to claim 7, wherein the internal electrode layer of said one multilayer capacitor part increases the thickness of the low resistance metal of the electrode material and the thickness of the internal electrode layer of said other multilayer capacitor part. A multilayer ceramic capacitor characterized in that the electrical resistance is reduced by the above.
る内部電極層とを交互に複数層積み重ねて形成する積層
体に外部電極を設けてなる積層セラミックコンデンサに
おいて、積層体の内部電極が積層方向と直交する方向に
分離され２つ以上の容量の異なった積層コンデンサ部を
有していることを特徴とする積層セラミックコンデン
サ。9. A multilayer ceramic capacitor in which external electrodes are provided in a multilayer body formed by alternately stacking a plurality of dielectric ceramic layers and internal electrode layers made of a low-resistance metal, wherein the internal electrodes of the multilayer body are arranged in a stacking direction. A multilayer ceramic capacitor having two or more multilayer capacitor sections separated in a direction orthogonal to the multilayer capacitor and having different capacities.
ンサにおいて、積層方向と直交する方向に対して隣り合
う積層コンデンサ部の電極間隔が０．０５ｍｍ以上離れ
ていることを特徴とする積層セラミックコンデンサ。10. The multilayer ceramic capacitor according to claim 9, wherein an electrode interval between adjacent multilayer capacitor portions in a direction orthogonal to the lamination direction is 0.05 mm or more.
する積層セラミックコンデンサにおいて、前記隣り合う
積層コンデンサの内、容量の小さなコンデンサ部の内部
電極パターンの面積は、容量の大きい方の積層コンデン
サ部の内部電極パターンの面積よりも小さくすることを
特徴とする積層セラミックコンデンサ。11. The multilayer ceramic capacitor having the multilayer capacitor part according to claim 9, wherein the area of the internal electrode pattern of the capacitor part having the smaller capacitance among the adjacent multilayer capacitors is smaller than that of the multilayer capacitor part having the larger capacitance. A multilayer ceramic capacitor characterized by being smaller than the area of the internal electrode pattern.
する積層セラミックコンデンサにおいて、前記隣り合う
積層コンデンサの内、容量の大きなコンデンサ部の内部
電極パターンの外部電極と電気的に接合する部分の断面
積を共通電極部分よりも小さくすること（狭窄、スリッ
ト等）によって内部電極層の電気抵抗を高めることを特
徴とする積層セラミックコンデンサ。12. The multilayer ceramic capacitor having the multilayer capacitor portion according to claim 9, wherein a cross-sectional area of a portion of the adjacent multilayer capacitor electrically connected to an external electrode of an internal electrode pattern of the capacitor portion having a large capacitance. A multilayer ceramic capacitor characterized in that the electrical resistance of the internal electrode layer is increased by making smaller than the common electrode portion (stenosis, slit, etc.).
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11333798A JP2000223348A (en) | 1998-11-26 | 1999-11-25 | Multilayer ceramic capacitor |
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10-335519 | 1998-11-26 | ||
| JP33551998 | 1998-11-26 | ||
| JP11333798A JP2000223348A (en) | 1998-11-26 | 1999-11-25 | Multilayer ceramic capacitor |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JP2000223348A true JP2000223348A (en) | 2000-08-11 |
Family
ID=26574643
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP11333798A Pending JP2000223348A (en) | 1998-11-26 | 1999-11-25 | Multilayer ceramic capacitor |
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| Country | Link |
|---|---|
| JP (1) | JP2000223348A (en) |
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| JP2006261584A (en) * | 2005-03-18 | 2006-09-28 | Tdk Corp | Multilayer capacitor |
| JP2006286731A (en) * | 2005-03-31 | 2006-10-19 | Tdk Corp | Multilayer capacitor |
| WO2002052591A3 (en) * | 2000-12-22 | 2007-11-15 | Epcos Ag | Electric multilayer component and arrangement with this component |
| US7659568B2 (en) | 2004-08-27 | 2010-02-09 | Murata Manufacturing Co., Ltd. | Monolithic ceramic capacitor and method for adjusting equivalent series resistance thereof |
| JP2010087260A (en) * | 2008-09-30 | 2010-04-15 | Tdk Corp | Multilayer capacitor |
| JP2012156193A (en) * | 2011-01-24 | 2012-08-16 | Tdk Corp | Stacked capacitor |
| EP1953777A4 (en) * | 2005-11-22 | 2014-06-25 | Murata Manufacturing Co | Multilayer capacitor |
| JP2015140134A (en) * | 2014-01-30 | 2015-08-03 | 豊田合成株式会社 | Airbag door and airbag device |
| JP2016187036A (en) * | 2016-06-02 | 2016-10-27 | 太陽誘電株式会社 | Multilayer ceramic capacitor |
| JP2018117098A (en) * | 2017-01-20 | 2018-07-26 | Tdk株式会社 | Multilayer capacitor and electronic component device |
| JP2020096074A (en) * | 2018-12-12 | 2020-06-18 | 太陽誘電株式会社 | Ceramic electronic component and wiring board |
| US10847314B2 (en) | 2017-01-20 | 2020-11-24 | Tdk Corporation | Multilayer capacitor and electronic component device |
| JP2021013016A (en) * | 2019-07-08 | 2021-02-04 | サムソン エレクトロ−メカニックス カンパニーリミテッド． | Capacitor parts |
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| WO2002052591A3 (en) * | 2000-12-22 | 2007-11-15 | Epcos Ag | Electric multilayer component and arrangement with this component |
| JPWO2006022258A1 (en) * | 2004-08-27 | 2008-05-08 | 株式会社村田製作所 | Multilayer ceramic capacitor and its equivalent series resistance adjustment method |
| WO2006022258A1 (en) * | 2004-08-27 | 2006-03-02 | Murata Manufacturing Co., Ltd. | Multilayer ceramic capacitor and method for controlling equivalent series resistance |
| US7659568B2 (en) | 2004-08-27 | 2010-02-09 | Murata Manufacturing Co., Ltd. | Monolithic ceramic capacitor and method for adjusting equivalent series resistance thereof |
| TWI405227B (en) * | 2005-03-18 | 2013-08-11 | Tdk Corp | Laminated capacitors |
| JP2006261584A (en) * | 2005-03-18 | 2006-09-28 | Tdk Corp | Multilayer capacitor |
| JP2006286731A (en) * | 2005-03-31 | 2006-10-19 | Tdk Corp | Multilayer capacitor |
| KR101147626B1 (en) * | 2005-03-31 | 2012-05-23 | 티디케이가부시기가이샤 | Multilayer Capacitor |
| TWI404091B (en) * | 2005-03-31 | 2013-08-01 | Tdk Corp | Multilayer capacitor |
| EP1953777A4 (en) * | 2005-11-22 | 2014-06-25 | Murata Manufacturing Co | Multilayer capacitor |
| JP2010087260A (en) * | 2008-09-30 | 2010-04-15 | Tdk Corp | Multilayer capacitor |
| US8659872B2 (en) | 2011-01-24 | 2014-02-25 | Tdk Corporation | Multilayer capacitor that includes a capacitor element body and at least four terminal units |
| JP2012156193A (en) * | 2011-01-24 | 2012-08-16 | Tdk Corp | Stacked capacitor |
| JP2015140134A (en) * | 2014-01-30 | 2015-08-03 | 豊田合成株式会社 | Airbag door and airbag device |
| JP2016187036A (en) * | 2016-06-02 | 2016-10-27 | 太陽誘電株式会社 | Multilayer ceramic capacitor |
| JP2018117098A (en) * | 2017-01-20 | 2018-07-26 | Tdk株式会社 | Multilayer capacitor and electronic component device |
| US10847314B2 (en) | 2017-01-20 | 2020-11-24 | Tdk Corporation | Multilayer capacitor and electronic component device |
| JP2020096074A (en) * | 2018-12-12 | 2020-06-18 | 太陽誘電株式会社 | Ceramic electronic component and wiring board |
| US11521798B2 (en) | 2018-12-12 | 2022-12-06 | Taiyo Yuden Co., Ltd. | Ceramic electronic device and wiring substrate |
| JP2021013016A (en) * | 2019-07-08 | 2021-02-04 | サムソン エレクトロ−メカニックス カンパニーリミテッド． | Capacitor parts |
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