JP2000208753A - Semiconductor device and manufacturing method thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce resistance between a source electrode and drain electrode and a channel layer, while the mutual conductance and linearity of a source-gate capacitance to a gate voltage are superior, for conducting high-efficiency low voltage drive. SOLUTION: Provided with a channel layer 34, a source electrode 38 and a drain electrode 39 are provided on its sides with a gate electrode 40 interposed inbetween. Distances from the source electrode 38 and drain electrode 39 to the channel layer 34 are set shorter than that from the gate electrode 40 to the channel layer 34.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a single semiconductor device having at least a field effect transistor, or a semiconductor device such as a semiconductor integrated circuit and a method of manufacturing the same.

[0002]

2. Description of the Related Art In recent years, there has been a strong demand for miniaturization and low power consumption of terminals in mobile communication systems such as mobile phones. For this reason, similar demands have been made on semiconductor devices such as transistors constituting the semiconductor device. For example, there is a demand for a digital cellular power amplifier that can be operated as a single positive power supply and that can be driven at low voltage and high efficiency.

[0003] One of the devices practically used for power amplifiers at present is a heterojunction field effect transistor HFET (Hetero Junction Field Effect Transistor).
r: HFET). This HFET performs current modulation using a heterojunction, and FIG.
FIG. 2 is a diagram schematically illustrating the configuration of a conventional HFET. This H
The FET includes a base layer 11 made of semi-insulating single crystal GaAs, a buffer layer 12 made of GaAs, a second barrier layer 13 made of AlGaAs, a channel layer 14 made of InGaAs, and a first barrier layer 15 made of AlGaAs. Are sequentially stacked, and a gate electrode 20 is formed on the first barrier layer 15. Each of the barrier layers 13 and 15
Carrier supply regions 13a and 15a containing n-type impurities
In the high resistance regions 13b and 15b, respectively.

On the first barrier layer 15, a gate electrode 20 is formed.
Are arranged on both sides of the gate electrode 20,
A source electrode 18 and a drain electrode 19 are formed in ohmic contact with a cap layer 16 interposed therebetween. With this configuration, the current between the source electrode 18 and the drain electrode 19 is modulated by the voltage applied to the gate electrode 20.

In general, an HFET generally has a recess structure in which the thickness of the first barrier layer 15 is reduced below and in the vicinity of the gate electrode 20 as shown in FIG. In this region, a carrier is depleted, or a region having less carriers than other channel regions is formed.

In an HFET having such a structure, carriers are accumulated in a channel layer by applying a positive voltage to a gate electrode to form a channel. In principle, the HFET having this structure has a gate-source capacitance Cgs and a transconductance that are different from those of other junction field effect transistors (hereinafter referred to as JFETs) and Schottky junction field effect transistors (hereinafter referred to as MESFETs). It has a feature that it has excellent linearity with respect to the gate voltage Vg of Gm. This is a great advantage in aiming for higher efficiency of the power amplifier.

[0007]

SUMMARY OF THE INVENTION As described above, HFE
Although T has a great advantage, in the case of the above-described structure, the current injected into the drain electrode 19 crosses the cap layer 16 and the first barrier layer 15 immediately below the drain current, reaches the channel layer 14, and the source electrode as it is. 18, the cap layer 1 under the barrier layer 15 and the source electrode 18.
6 and reaches the source electrode 18. By the way, in general, the first barrier layer 15 includes the high resistance region 15b, so that the resistance between the source and the drain is not sufficiently reduced, the current loss is large, and the current portion due to generation of Joule heat or the like is reduced. There is a problem that deterioration of the glass is likely to occur.

The present invention seeks to solve the above-mentioned problems,
Features of the HFET, that is, it can be easily operated with a single positive power supply, has excellent transconductance Gm and excellent linearity of the source-gate capacitance Cgs with respect to the gate voltage Vg, and has a reduced resistance between the source and drain electrodes and the channel layer. Accordingly, the present invention provides, for example, a semiconductor device and a method of manufacturing the same, which can perform high-efficiency low-voltage driving.

[0009]

A semiconductor device according to the present invention has a channel layer, and a source electrode and a drain electrode are arranged on both sides of a gate electrode with a gate electrode interposed therebetween. Each distance from the electrode and the drain electrode is set to be smaller than the distance from the gate electrode to the channel layer. In the above structure, a gate cap layer having a band gap larger than the band gap of the channel layer is provided between the gate cap layer and the channel layer below the gate electrode.

A method of manufacturing a semiconductor device according to the present invention is a method of manufacturing a semiconductor device having a channel layer and a source electrode and a drain electrode disposed on both sides of a gate electrode. Forming at least a channel layer, a first barrier layer, a first barrier layer having a band gap larger than the band gap of the channel layer, and a gate cap layer; Removing the formation portions of the source electrode and the drain electrode, and obtaining a semiconductor device in which each distance from the source electrode and the drain electrode to the channel layer is smaller than the distance from the gate electrode to the channel layer. It is.

According to the present invention, as described above, the distance between the source electrode and the drain electrode with respect to the channel layer is selected to be small, thereby reducing the resistance between the source and the drain. Accordingly, low-voltage driving can be performed.

In the present invention, by providing a layer having a larger band gap than the channel layer below the gate electrode, carriers from the first barrier layer can be transferred to the channel layer having a smaller band gap. A semiconductor element which can efficiently supply carriers to the channel layer and is driven with high efficiency and low voltage, especially HF
A semiconductor device having ET is configured.

[0013]

DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of a semiconductor device according to the present invention will be described. FIG. 1 shows a schematic cross-sectional view of an example of a semiconductor device in which a single HFET is formed on a semiconductor substrate 61, but the device of the present invention is not limited to this example. In this example, a buffer layer 32 made of, for example, undoped GaAs to which impurities are not added is epitaxially grown on a base 11 made of, for example, semi-insulating GaAs single crystal, and a buffer layer 32 made of a III-V compound semiconductor is formed thereon. The second barrier layer 33, the channel layer 34, and the first barrier layer 35 are sequentially stacked by epitaxial growth.

On the first barrier layer 35, an etching stopper layer 50 used in an etching step described later is formed.
It is deposited with a thickness on the order of nm. Then, the gate cap layer 36 is formed on the portion where the gate electrode is formed on the etching stopper layer 50.

An insulating film 37 having a thickness of, for example, 300 nm is formed on the gate cap layer 36 and the surface facing the outside of the etching stopper layer 50. The insulating film 37 is formed on the gate cap layer 36 and on both sides thereof. The electrode windows 37WG, 37WS and 37WD are respectively opened on the etching stopper layer 50 of FIG.
Through WS and 37WD, the gate electrode 40, the source electrode 38, and the drain electrode 39 are in contact with the gate cap layer 36 and the etching stopper layer 50.

The second barrier layer 33 is formed of a semiconductor having a band gap larger than that of the semiconductor constituting the channel layer 34, for example, Al _x Ga.
It is preferable to be constituted by a _1-X As mixed crystal, and the composition ratio x of Al is set to 0.2 ≦ x ≦ 0.3. The second barrier layer 33 is formed from the side of the base 31 from the undoped high-resistance region 33b having a thickness of, for example, about 200 nm.
An n-type impurity, for example, Si having a thickness of, for example, 4 nm is highly concentrated, for example, from 3.0 × 10 ¹⁸ / cm ^{3 to} 4.0 × 10 ¹⁸ / cm ^3.
It has a structure in which a carrier supply layer 33a to which a degree of addition is added and a high resistance region 33b similar to the above are sequentially laminated.

The channel layer 34 forms a current path between the source electrode 38 and the drain electrode 39.
The first and second barrier layers 35 and 33 are formed of an undoped semiconductor having a smaller band gap than that of the semiconductor forming the barrier layers 35 and 33. As the channel layer 34, for example, I
is preferably configured by n _x Ga _1-x As mixed crystal composition ratio y of the In is a 0.1 ≦ x ≦ 0.2.

The first barrier layer 35 is formed of the channel layer 3
4 is made of a semiconductor having a wider band gap than the semiconductor constituting the semiconductor device 4. For example, Al _X Ga _1-X A
s, and in this case, Al
The composition ratio x is set to 0.2 ≦ x ≦ 0.3. The first barrier layer 35 is formed from the channel layer 34 side from the undoped high-resistance region 35b having a thickness of, for example, about 2 nm, and an n-type impurity, for example, 4 nm in thickness having a high concentration of, for example, 3.0 × 10 3. ^The carrier supply layer 35a to which about ¹⁸ / cm ^{3 to} 4.0 × 10 ¹⁸ / cm ^{3 is} added is sequentially laminated.

With this configuration, carriers supplied from the carrier supply layer 33a of the second barrier layer 33 and the carrier supply layer 35a of the first barrier layer 35 are accumulated in the channel layer 34.

The etching stopper layer 50 has an effect of stopping the etching in an etching step for forming the gate cap layer 36 only in the gate formation portion, as will be described later. When the layer 36 is made of AlGaAs, the etching stopper layer 50 is preferably made of GaAs, particularly n-type GaAs. When the gate cap layer 36 is made of GaAs, the etching stopper layer 50 is made of AlGa having an Al composition ratio of about 0.5.
It is preferable to be constituted by As.

The gate cap layer 36 is made of a semiconductor having a wider band gap than at least the semiconductor forming the channel layer 34. The gate cap layer 36 is preferably made of, for example, Al _z Ga _{1 -z} As, and the Al composition z is set to 0.2 ≦ z ≦ 0.3. The gate cap layer 36 is made of an undoped high-resistance semiconductor to which no impurity is added.

On the gate cap layer 36 having the large band gap, a gate electrode 40 formed by laminating, for example, Ti, Pt, and Au is sequentially formed in an ohmic manner. On both sides of the gate electrode 40, for example, AuGe, Ni, and Au are sequentially deposited from the lower layer on the etching stopper layer 50, respectively, and ohmic to the first barrier layer 35 by heat treatment for alloying. The source electrode 38 and the drain electrode 39 contacted
Is formed.

According to this structure, since the gate cap layer 36 having a larger band gap than the channel layer 34 is arranged between the channel layer 34 and the gate electrode 40, the mutual contactance Gm and the An FET having excellent linearity of the source-to-source capacitance Cgs with respect to the gate voltage Vg and having higher power load efficiency can be configured.

That is, the threshold voltage _Vth can be controlled by the arrangement of the gate cap layer 36.
By setting the band gap of the gate cap layer 36 to be large, it is possible to prevent a carrier from entering the gate cap layer 36 from the carrier supply layer 35a and generating parallel conduction. Further, for example, in a JFET or MESFET, a channel layer is formed by impurity introduction and ion activation by ion implantation. This channel layer is relatively thick and distribution of carriers occurs. Therefore, the gate voltage Vg of the conductance Gm is generated. Is less linear, but HFE
T has a characteristic excellent in the linearity of Gm described above because its channel layer is formed by epitaxial growth and its thickness is made thin, for example, about 15 nm. Further, the depletion layer capacitance in the JFET and the MESFET is closely related to the gate-source capacitance Cgs, but in the above-described HFET, a predetermined high resistance layer (between the channel flannel layer and the gate electrode) is used. Since the capacitance of the gate cap layer) is related to Cgs, the dependence of the gate voltage Vg is reduced.

As described above, the selection of the threshold voltage _Vth of the HFET depends on the distance between the gate electrode 40 and the channel layer 34 as one factor. For example, the thickness and the resistivity of the gate cap layer 36 interposed under the gate electrode 40 can be selected. Thus, the gate electrode 4
0 and the channel layer 34, the gate cap layer 3
6, the electrodes 38 and 39 are in ohmic contact with the first barrier layer 35, and the distance between the source electrode 38 and the drain electrode 39 and the channel layer 34 is increased. The distance between the electrode 39 and the channel layer 34 is smaller than the distance between the gate electrode 40 and the channel layer 34, for example, several n
By selecting m, the on-resistance R _ON between the source and the drain can be reduced.

Next, an example of a method of manufacturing the semiconductor device according to the present invention shown in FIG. 1 will be described.

First, a substrate 6 whose schematic sectional view is shown in FIG.
1. In manufacturing the substrate 61, first, the base 31 made of, for example, a semi-insulating GaAs single crystal is prepared. A buffer layer 32 is formed on the substrate 31, and then a second barrier layer 33, a channel layer 34, a first barrier layer 35,
The etching stopper layer 50 and the gate cap layer 361 are sequentially formed, for example, by MOCVD (Metalorganic Chemical Vapor).
Deposition: Metalorganic vapor phase epitaxy, MBE (Molecular)
Beam Epitaxy: Epitaxial growth by the molecular beam epitaxy method.

That is, a buffer layer 32 made of, for example, undoped GaAs, which is not doped with an impurity, is epitaxially grown on a substrate 31.
High resistance region 33 made of undoped AlGaAs, for example.
b, an n-type carrier supply layer 33a doped with Si of a first conductivity type, for example, n-type impurity, and a high resistance region 33b made of undoped AlGaAs, for example, are successively epitaxially grown to form a second barrier layer 33. Form. Subsequently, a channel layer 34 of an undoped InGaAs layer is epitaxially grown, and a high resistance region 35b of undoped, for example, AlGaAs and an n-type carrier supply layer doped with a first conductivity type, for example, n-type impurity Si, are formed thereon. 35a are successively epitaxially grown to form a first barrier layer 35. Subsequently, a first conductivity type impurity, for example, n-type impurity Si
Is epitaxially grown, and a gate cap layer 361 made of, for example, AlGaAs having a larger band gap than the channel layer 34 is continuously epitaxially grown thereon.
The semiconductor substrate 61 is formed.

Although not shown, for example, when a plurality of HFETs electrically separated from each other are formed on the common substrate 61 in the form of adjacent semiconductor elements, or the HFET is electrically connected to another HFET. Separation grooves are formed by performing so-called mesa etching between circuit elements to be separated into each other, and an insulation layer is filled in the separation grooves as necessary, or an insulation layer is formed on the wall surfaces of the separation grooves. Performs element isolation.

Next, as shown in FIG. 3, the gate cap layer 361 shown in FIG. 2 is selectively removed from the other portions except for the portion immediately below the gate electrode to be finally formed and the vicinity thereof. The gate cap layer 36 is formed by etching. This etching is performed using an etchant having a higher etching rate with respect to the gate cap layer 361 than the etching rate with respect to the etching stopper layer 50, so that at least a portion where a source electrode and a drain electrode are finally formed is formed. The gate cap layer 361 is removed by etching.

Thereafter, as shown in FIG. 4, an insulating layer 37 made of, for example, silicon nitride SiN is entirely formed by CVD (Chemical
It is formed by a vapor deposition method or the like. The insulating layer 37 is subjected to pattern etching by photolithography, that is, application, pattern exposure, and development of a photoresist layer to form a pattern, and using this as an etching mask, pattern etching is performed on the insulating layer 37 to form a gate electrode. An electrode window 37WG is opened in the portion.

As shown in FIG. 5, a gate electrode 40 is formed through the electrode window 37WG. This gate electrode 4
0 can be formed by, for example, temporarily vapor-depositing Ti, Pt, and Au sequentially on the entire surface and pattern-etching the laminated metal layer by photolithography. Thereafter, the electrode windows 37Ws and 37W are formed in the portions of the insulating layer 37 where the source and drain electrodes are formed by pattern etching by photolithography.
Form D.

As shown in FIG. 1, a source electrode 38 and a drain electrode 39 are formed through the respective electrode windows 37Ws and 37WD. These electrodes 38 and 3
For example, first, an AuGe alloy and Ni are sequentially vapor-deposited once on the entire surface, and pattern etching is performed by photolithography, thereby forming a source electrode 38 and a drain electrode 39 each having a required pattern. Thereafter, for example, an alloying process is performed by a heat treatment at about 400 ° C.
A source electrode 38 and a drain electrode 39 that are in ohmic contact with the carrier supply layer 35a of the first barrier layer 35 are formed. Thus, the semiconductor substrate 61
A semiconductor device in which at least a semiconductor element by an HFET is formed.

According to the above-described manufacturing method of the present invention, the gate cap layer 36 and the etching stopper layer 50 are formed under the gate electrode 40. These layers are formed by continuous epitaxial growth together with the channel layer and the barrier layer. Since it can be formed, the number of manufacturing steps does not increase so much. In addition, since the etching depth for removing the gate cap layer 36 in the formation portions of the source and drain electrodes is determined by the etching stopper layer 50, the etching depth can be reliably selected. The semiconductor device described above can be obtained.

In the above-described example, the GaAs substrate 31 is used. However, for example, an InP-based substrate can be used. In this case, the InAs-based semiconductor layer is grown to grow the InAs-based semiconductor layers. Can be configured.

In the examples described with reference to FIG. 1 and FIGS. 2 to 5, the gate cap layer 36 having a large band gap is
In the case where the gate cap layer is undoped, that is, a high-resistance gate cap layer is formed, the second through the electrode window 37WG shown in FIG.
As shown in FIG. 6, a second conductivity type region 46 containing a second conductivity type impurity is formed in a part of the gate cap layer 36 in the thickness direction by diffusing a conductive type, for example, Zn of a p-type impurity in a gas phase. FIG. 7 shows a structure in which the second conductivity type region 46 and the high resistance region are formed in the gate gap layer 36.
As shown in FIG. 5, a recess 47 having a required depth can be provided to obtain a required threshold voltage _Vth .
A combination of these can also be used.

In the illustrated example, the first conductivity type is the n-type and the second conductivity type is the p-type. However, the configuration may be such that these are the opposite conductivity types. .

In the example shown, HFE is placed on the substrate 61.
In the case where T is formed singly, this HFET is
The present invention is not limited to the example described above, for example, a semiconductor device having one circuit configuration can be applied, and can be applied to semiconductor devices having various configurations.

[0039]

As described above, in the semiconductor device according to the present invention, the gate cap layer 36 having a larger band gap than the channel layer 34 is disposed between the channel layer 34 and the gate electrode 40. , The dependence of the mutual conductance Gm and the gate-source capacitance Cgs on the gate electrode Vg is small, and the power load efficiency is high.
ET can be configured.

The selection of the threshold voltage V _th of the HFET according to this configuration depends on the selection of the distance between the gate electrode 40 and the channel layer 34 as one factor. This can be performed by selecting the thickness, the resistivity, and the like of the gate cap layer 36 interposed below the gate electrode 40. Thus, the gate electrode 40
A gate cap layer 36 is provided between the
, But the source electrode 38 and the drain electrode 3
9 and the channel layer 34, the electrodes 38 and 39 are in ohmic contact with the first barrier layer 35, and the distance between the source electrode 38 and the drain electrode 39 and the channel layer 34 is changed to the gate electrode. 4
Smaller than the distance between 0 and the channel layer 34, for example, several nm
, The on-resistance R _ON between the source and the drain can be reduced, and high power load efficiency can be obtained. Thus, low-voltage driving can be performed, and high-frequency characteristics can be improved.

Further, according to the manufacturing method of the present invention, a stable and highly reliable semiconductor device with little variation can be manufactured without significantly increasing the number of steps as described above.

[Brief description of the drawings]

FIG. 1 is a schematic configuration diagram of an example of a semiconductor device according to the present invention.

FIG. 2 is a cross-sectional view illustrating one step of an example of a method for manufacturing a semiconductor device according to the present invention.

FIG. 3 is a cross-sectional view illustrating one step of an example of a method for manufacturing a semiconductor device according to the present invention.

FIG. 4 is a cross-sectional view illustrating one step of an example of a method for manufacturing a semiconductor device according to the present invention.

FIG. 5 is a cross-sectional view illustrating one step of an example of a method for manufacturing a semiconductor device according to the present invention.

FIG. 6 is a schematic configuration diagram of another example of the semiconductor device according to the present invention.

FIG. 7 is a schematic configuration diagram of still another example of a semiconductor device according to the present invention.

FIG. 8 is a schematic configuration diagram of a conventional HFET.

[Explanation of symbols]

11, 31 ... substrate, 12, 32 ... buffer layer,
13, 33 ... second barrier layer, 15, 35 ... first
, A carrier supply region, 13b, 33b, 15b, 35b,...
High resistance region, 16 ... cap layer, 18, 38 ...
Source electrode, 19, 39 ... Drain electrode, 20, 4
0 ... gate electrode, 36 ... gate cap layer, 3
7 ... insulating layer, 37WS, 37WD, 37WG ...
Electrode window, 46: second conductivity type region, 61: substrate

Claims (11)

[Claims] 1. A semiconductor device having a channel layer and having a source electrode and a drain electrode on both sides of a gate electrode, wherein each distance from the source electrode and the drain electrode to the channel layer is different. A semiconductor device which is selected to be smaller than a distance from the gate electrode to the channel layer. 2. The semiconductor according to claim 1, wherein a gate cap layer having a band gap larger than the band gap of the channel layer is provided between the channel layer and the channel layer below the gate electrode. apparatus. 3. A gate cap layer having a band gap larger than a band gap of the channel layer is provided between the gate cap layer and the channel layer below the gate electrode. A first barrier layer having a band gap larger than the band gap of the channel layer is provided, and a carrier supply region containing a first conductivity type impurity is provided in the first barrier layer. 2. The semiconductor device according to claim 1, wherein: 4. A gate cap layer having a band gap larger than a band gap of the channel layer is provided between the gate electrode and the channel layer, and the gate cap layer is provided at a portion facing the gate electrode. ,
2. The semiconductor device according to claim 1, comprising one or both of a high resistance region and a second conductivity type region. 5. The semiconductor device according to claim 3, wherein an etching stopper layer having a thickness of 2 nm or more is arranged between said gate cap layer and said first barrier layer. 6. The carrier supply region of the first barrier layer is made of an AlGaAs mixed crystal of a group III-V compound semiconductor; the etching stopper layer is made of GaAs of a group III-V compound semiconductor; Is a group III-V compound semiconductor InGa
6. The semiconductor device according to claim 5, comprising an As mixed crystal. 7. The semiconductor device according to claim 3, wherein a second barrier layer is arranged on a side of said channel layer opposite to said first barrier layer. 8. The channel layer is made of an InGaAs mixed crystal of a group III-V compound semiconductor, and the second barrier layer is made of an AlGaAs mixed crystal of a group III-V compound semiconductor. 8. The semiconductor device according to claim 7, further comprising a carrier supply region containing a first conductivity type impurity.
3. The semiconductor device according to claim 1. 9. The semiconductor device according to claim 1, wherein the channel layer is made of an InAs-based compound semiconductor of a group III-V compound semiconductor. 10. A method of manufacturing a semiconductor device having a channel layer and having a source electrode and a drain electrode on both sides of a gate electrode, wherein at least the channel layer and the channel are formed on a substrate. Forming a first barrier layer having a band gap larger than the band gap of the layer and a gate cap layer; and etching and removing a portion of the gate cap layer where a source electrode and a drain electrode are formed. Wherein a distance from the source electrode and the drain electrode to the channel layer is selected to be smaller than a distance from the gate electrode to the channel layer. Production method. 11. In the film forming step, the gate cap layer is formed on the first barrier layer via an etching stopper layer, and a portion of the gate cap layer where a source electrode and a drain electrode are formed is removed. 11. The method of manufacturing a semiconductor device according to claim 10, wherein the etching is performed by controlling an etching depth by the channel stopper layer.