JP3002291B2 - Semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to a semiconductor device having a portion in which a current flows in a direction perpendicular to a semiconductor surface.

In recent years, with an increase in the amount of information handled by communication systems and the like, there has been a demand for higher speed (higher frequency) and higher output of semiconductor devices used in these systems.

[0003]

2. Description of the Related Art In a radio communication system such as a satellite communication system, a GaAs power FET is used for a transmission device requiring high output, and a reception device for detecting a weak signal includes:
A low noise HEMT is used. When trying to operate such a field-effect transistor at a high frequency,
It is required to shorten the gate electrode length (gate length) in the direction connecting the source electrode and the drain electrode.

FIG. 2 shows an example of a conventional GaAs field effect transistor. FIG. 2A is a cross-sectional view illustrating the configuration. On the i-type GaAs substrate 51, an n-type GaAs layer 52 for forming an active layer having an impurity concentration of 2 × 10 ¹⁷ cm ⁻³ and a thickness of 100 nm is formed. On the surface of the n-type GaAs layer 52, a source electrode 56, a gate electrode 57, and a drain electrode 58 are formed. For example, a source electrode 56 and a drain electrode 58 formed of AuGe / Au form ohmic contact with the n-type GaAs layer 52, and a gate electrode 57 formed of Al is formed of n-type GaAs.
A Schottky contact is formed in the s layer 52.

For example, the source electrode 56 is grounded, a negative control voltage is applied to the gate electrode 57, and the drain electrode 58
To apply a positive drain voltage. FIG. 2B shows the IV characteristics of the drain current versus the drain voltage observed at this time. When the gate voltage Vg is 0 V, the source electrode 5
6 and the drain electrode 58 are wide open, and a large drain current IDS flows. Gate voltage V
When g is changed in the negative direction, a depletion region develops below the gate electrode 57, and the cross-sectional area of the current path narrows. As the cross-sectional area of the current path decreases, the drain current IDS decreases.

In a region where the drain voltage VDS is equal to or higher than a certain value, the drain current IDS takes a constant value in accordance with the value of the gate voltage Vg irrespective of the increase in the drain voltage VDS. preferable.

The operating speed of such a field-effect transistor depends on the transit time during which carriers are transported from the source electrode 56 to the drain electrode 58. One effective means for increasing the frequency (speeding up) of a transistor is to shorten the gate length. By the way, for example,
If the length is reduced to μ μm or less, the influence of the drain voltage extends below the gate electrode, and a so-called short channel effect occurs.

FIG. 2C shows the IV characteristics of the field effect transistor in a state where the short channel effect has occurred. As shown in the figure, as the drain voltage VDS increases, the rate at which the drain current IDS increases increases, and the absolute value of the voltage required to pinch off the channel increases. This indicates that the influence of the drain voltage extends to the source side, and the influence of the gate voltage applied to the gate electrode becomes less likely. When such a short channel effect occurs, the output resistance decreases and the amplification factor decreases. That is, when the gate length is reduced for higher frequency, the performance of the transistor is reduced due to the short channel effect.

[0009]

As described above,
According to the prior art, there is a limit in improving the performance of the transistor.

An object of the present invention is to provide a semiconductor device whose performance can be easily improved. Another object of the present invention is to provide a semiconductor device having a transistor which operates at a high frequency and has a high output power.

[0011]

According to an aspect of the present invention, there is provided a semiconductor base having conductivity, a semiconductor base disposed on the semiconductor base, and having a reduced cross-sectional area in a direction parallel to the surface of the semiconductor base; A semiconductor neck having conductivity, a semiconductor head disposed on the semiconductor neck, having an enlarged cross-sectional area and having conductivity, and a surface of the semiconductor head spaced laterally from above the semiconductor neck. A first current terminal formed thereon and a second current terminal formed on a surface of the semiconductor base.
A current terminal that defines a current path from the first current electrode to the second current terminal via the semiconductor head, the semiconductor neck, and the semiconductor base. And a control electrode disposed on a region of the semiconductor head above the semiconductor neck and controlling a current flowing through the current path.

[0012]

A first current terminal and a control electrode are formed on a semiconductor head, and a second current terminal is formed on a semiconductor base connected via a semiconductor neck. The current path formed between the second current terminal and the second current terminal can be sufficiently affected by the control electrode in a portion on the semiconductor neck.

If the first current terminals are formed on both sides of the control electrode, a current flows from both sides of the control electrode, so that a high output operation is facilitated.

Since the control electrode and the second current terminal are arranged at different heights, it is easy to reduce the parasitic capacitance.

[0015]

FIG. 1 shows a field effect transistor according to an embodiment of the present invention. FIG. 1A shows a sectional view, and FIG.
(B) shows a plan view.

On an i-type GaAs substrate 11, an n-type GaAs
An n-type GaAs semiconductor neck 13 surrounded by an insulator region 14 made of an insulator such as SiO ₂ , Si ₃ N ₄ is arranged on the semiconductor base 12. Have been. A semiconductor head 15 made of n-type GaAs is continuous with the semiconductor neck 13 and extends over the insulator region 14. Source electrodes 2 made of AuGe / Ni / Au on both sides of the semiconductor head 15
1 are formed to form an ohmic contact. Ti over the center of the semiconductor head 15 so as to cover the semiconductor neck 13
A gate electrode 23 made of / Al is arranged to form a Schottky contact. In addition, a drain electrode 25 made of AuGe / Ni / Au is arranged in a region outside the insulator region 14 of the semiconductor base 12 to form an ohmic contact.

In such a configuration, the current path is continuous from the source electrode 21 to the side of the semiconductor head 15, proceeds from the side of the semiconductor head to the center, and extends from the center of the semiconductor head to the semiconductor neck and the semiconductor base. It proceeds in the vertical direction and again in the semiconductor base in the horizontal direction to reach the drain electrode 25. When a gate voltage is applied to the gate electrode 23 to develop a depletion layer to reach the insulator region 14, the current path from the source electrode 21 to the drain electrode 25 is completely cut off.

The drain electrode 25 for extracting an output signal is
Since it is separated from the gate electrode 23 to which the input signal is applied and is separated by the insulator region 14 and the like, the parasitic capacitance can be reduced. As described above, the transistor employing the D-shaped structure prevents the short channel effect,
High output power can be obtained.

A method for manufacturing a field effect transistor as shown in FIG. 1 will be described below. FIG. 3 is a cross-sectional view for explaining the first manufacturing method.

As shown in FIG. 3A, an n-type GaAs layer 12 is formed on an i-type GaAs substrate 11, and an insulating film formed of an insulating material such as SiO ₂ or Si ₃ N ₄ thereon. 14
To form This insulating film 1 is formed by photolithography.
An opening 17 is created in 4. The opening 17 has a shape according to a cross-sectional shape of a semiconductor neck portion to be formed later.

Next, as shown in FIG. 3B, the exposed n
The n-type GaAs is epitaxially grown on the surface of the n-type GaAs layer 12 to form a semiconductor neck 13 and a semiconductor head 1.
5 is formed. Unnecessary portions of the epitaxial layer grown on the insulating film 14 are removed by patterning. By continuously performing epitaxial growth from the exposed surface of the n-type GaAs 12, the grown n-type GaAs
The layers 13 and 15 are single crystal regions.

Next, as shown in FIG.
Is patterned to form an n-type GaAs layer 1 serving as a semiconductor base.
A drain electrode 25 made of AuGe / Ni / Au is formed on the semiconductor head 15, and AuGe / N is formed on both sides of the semiconductor head 15.
A source electrode 21 formed of i / Au is formed, and Ti / Ti is formed on the center of the semiconductor head 15 so as to cover the semiconductor neck 13.
A gate electrode 23 made of Al is formed.

The thickness of the insulating film 14 is, for example, 10
0 to 500 nm. The n-type GaAs layer 12 has an impurity concentration of, for example, 10 ¹⁷ to 10 ¹⁸ cm ⁻³ and a thickness of 50
nm to 1 μm. The opening 17 formed in the insulating film 14 has, for example, a width of 0.1 to 1 μm and a desired length. The semiconductor head 15 shown in FIG.
Is, for example, 2 to 5 on the insulating film 14 in the lateral direction.
Extend 0 μm. Gate electrode 23 shown in FIG.
Has a width of about 0.
Extend 5 to 10 μm. Source electrode 21 and drain electrode 25 have a width of, for example, 10 μm or more. The substrate 1
1, i-type GaAs was used, but Ga
A layer obtained by growing an As layer may be used.

FIG. 4 shows a second manufacturing method. FIG.
As shown in (A), an n-type G
A mask 33 made of a nitride film or the like is formed on the surface of the substrate on which the aAs layer 32 is formed. This mask 3
Anisotropic etching is performed using the n-type GaAs layer 3
2 is etched to form an n-type GaAs region 32 having a predetermined shape. The narrow n formed under the mask 33
The type GaAs region forms the semiconductor neck 13 shown in FIG.

Next, as shown in FIG. 4B, the surface of the n-type GaAs region 32 dug by etching is
An insulating film 14 made of iO ₂ , Si ₃ N ₄ or the like is formed. The mask 33 shown in FIG. 4A is removed at an appropriate time. In FIG. 4B, the n-type GaAs region 3
It is preferable that the top of 2 protrudes above the surface of the insulating film 14 as shown in the figure.

Next, as shown in FIG. 4C, using the exposed n-type GaAs region 32 as a seed, an n-type GaAs epitaxial layer 34 is grown mainly using lateral growth. In this manner, a structure similar to that shown in FIG. 3B is formed, and then an electrode is formed by the same steps as those in FIG. 3 to obtain the transistor shown in FIG.

FIG. 5 shows a third manufacturing method using selective etching. As shown in FIG. 5A, i-type GaAs
An n-type GaAs layer 35 and an n-type AlGaAs
A substrate structure in which s36 and an n-type GaAs layer 37 are sequentially stacked is prepared.

Next, as shown in FIG.
A resist mask 38 is formed on the surface of the s layer 37, and the n-type GaAs 37 is etched by anisotropic dry etching or the like, exposing the surface of the n-type AlGaAs layer 36. Thereafter, the n-type AlGaAs layer 36 is etched from the side by selective etching in which AlGaAs is etched without etching GaAs, thereby forming an n-type AlGaAs region 36a to be a narrow semiconductor neck. After that, the resist mask 38 is removed. Thus, an E-shaped semiconductor structure is obtained.

Next, as shown in FIG. 5C, n-type GaAs
The source electrode 21 and the gate electrode 23 are formed on the s layer 37a, and the drain electrode 25 is formed on the surface of the n-type GaAs layer 35.

In the structure shown in FIG.
The space between the type GaAs layers 35 and 37a may be backfilled with an inorganic or organic insulator.

FIG. 6 shows a bipolar transistor structure according to another embodiment of the present invention. As in the embodiment shown in FIG.
A semiconductor base 42 made of n-type GaAs and a semiconductor neck 43 made of n-type GaAs are formed on the i-type GaAs substrate 11, and the periphery thereof is surrounded by the insulator region 14. A semiconductor head including a p-type GaAs region 44 and an n-type GaAs region 45 is formed on the semiconductor neck 43 and the insulator region 14. Note that only the p-type GaAs region 44 is in contact with the semiconductor neck 43. That is, the n-type GaAs region 45 is replaced by the p-type GaAs region 44.
An n-type GaAs region 42 arranged below for the first time through
43. Thus, a bipolar transistor structure is formed. An emitter electrode 47 is formed on the n-type GaAs region 45, a base electrode 48 is formed on the p-type GaAs region 44, and a collector electrode 49 is formed on the n-type GaAs layer 42. p-type GaAs region 44
Can be formed, for example, by implanting Be ions into an n-type GaAs region.

The case of a semiconductor device using GaAs (AlGaAs) has been described above.
Semiconductor materials such as aAs) and InAs can also be used. Although the case where SiO ₂ is used as the insulator region has been described, other insulator materials, for example, SiN _x , Si
ON, Al ₂ O ₃ , insulating resin and the like can also be used.

The present invention has been described in connection with the preferred embodiments.
The present invention is not limited to these. For example,
It will be apparent to those skilled in the art that various modifications, improvements, combinations, and the like can be made.

[0034]

As described above, according to the present invention,
A high-performance semiconductor device having a novel configuration is provided.

By supplying a current from both sides of the control electrode, a high-output semiconductor device can be realized.

Since the signal input electrode and the signal output electrode are formed apart from each other, the feedback capacitance is reduced, and high-frequency operation is facilitated.

[Brief description of the drawings]

FIG. 1 illustrates a field effect transistor according to an embodiment of the present invention. 1A is a sectional view, and FIG. 1B is a plan view.

FIG. 2 shows a field effect transistor according to the prior art. FIG. 2A is a cross-sectional view showing the configuration, FIG.
(C) is a graph showing IV characteristics.

FIG. 3 illustrates a method of manufacturing a semiconductor device according to an embodiment of the present invention. 3A, 3B, and 3C are cross-sectional views of the semiconductor structure.

FIG. 4 illustrates a method of manufacturing a semiconductor device according to an embodiment of the present invention. 4A, 4B, and 4C are cross-sectional views of the semiconductor structure.

FIG. 5 illustrates a method of manufacturing a semiconductor device according to an embodiment of the present invention. 5A, 5B, and 5C are cross-sectional views of the semiconductor structure.

FIG. 6 is a cross-sectional view illustrating a semiconductor device including a bipolar transistor according to another embodiment of the present invention.

[Explanation of symbols]

 Reference Signs List 11 i-type GaAs substrate 12 n-type GaAs base 13 n-type GaAs neck 14 insulator region 15 n-type GaAs head 17 opening 21 source electrode 23 gate electrode 25 drain electrode 32 n-type GaAs region 33 mask 34 n-type GaAs epitaxial layer 35 n-type GaAs layer 36 n-type AlGaAs layer 37 n-type GaAs layer 38 resist mask 42 n-type GaAs layer (collector) 43 n-type GaAs region 44 p-type GaAs region (base region) 45 n-type GaAs region (emitter region)

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁷ , DB name) H01L 21/338 H01L 21/331 H01L 29/73 H01L 29/80 H01L 29/812

Claims (3)

(57) [Claims] 1. A semiconductor base having conductivity, a semiconductor neck disposed on the semiconductor base, having a reduced cross-sectional area in a direction parallel to the surface of the semiconductor base, and having conductivity, and on the semiconductor neck. A semiconductor head having conductivity, having an enlarged cross-sectional area, and a first current terminal formed on a surface of the semiconductor head that is laterally separated from above the semiconductor neck portion; A second current terminal formed on a surface of the semiconductor base, from the first current electrode to the second current terminal via the semiconductor head, the semiconductor neck, and the semiconductor base; A semiconductor device, comprising: the second current terminal defining a current path; and a control electrode disposed on a region of the semiconductor head above the semiconductor neck and controlling a current flowing through the current path. 2. The semiconductor device according to claim 1, further comprising an insulator region formed around said semiconductor neck in a space between said semiconductor base and said semiconductor head. 3. A region of the semiconductor head in contact with the first current terminal has a first conductivity type, a region of the semiconductor head on the semiconductor neck has a second conductivity type, The semiconductor device according to claim 1, wherein the semiconductor base has a first conductivity type and forms a bipolar transistor structure.