JP2000114372A - Method for manufacturing semiconductor device - Google Patents

Abstract

(57) Abstract: Provided is a method of manufacturing a semiconductor device capable of forming a self-aligned contact in which a wiring short and an increase in contact resistance are suppressed without causing an etch stop. A step of forming a gate electrode having sidewalls on a semiconductor substrate; a step of forming source / drain regions having an LDD structure; and a step of forming an etching stopper layer on the entire surface. Forming an organic insulating film 14 buried between gate electrodes, forming an interlayer insulating film 9 on the entire surface, and forming an etching stopper layer 8.
Providing an opening by etching the interlayer insulating film 9 and the organic insulating film 14 while depositing a polymer layer on the surface of the substrate, and forming the contact hole 10 by removing the polymer layer and the etching stopper layer 8 at the bottom of the opening. A method for manufacturing a semiconductor device, comprising: a step of forming an upper wiring 11;

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for forming a safe and highly reliable self-aligned contact in which problems such as an etch stop, a short circuit of a wiring, and an increase in contact resistance have been solved. And a method of manufacturing a semiconductor device.

[0002]

2. Description of the Related Art In recent years, high integration of semiconductor integrated circuits has advanced to the next generation in three years, and design rules have been reduced to 70% of the previous generation. Along with this reduction, the speed of the semiconductor device has also been increased. For example, MOS (Metal Oxi
2. Description of the Related Art In semiconductor devices such as de semiconductor devices, fine design rules have been applied due to advances in fine processing technology, particularly to higher resolution of light exposure technology.

[0003] Higher resolution of the light exposure technology has been achieved by improving the exposure apparatus, the resist material, and the resist patterning process while satisfying the dimensional processing accuracy and the overlay accuracy corresponding to the design rules. For example, the wavelength of an exposure light source has been shortened, a resist material suitable for the wavelength of the light source has been developed, or a fine pattern has been formed by a phase shift method.

[0004] However, it is difficult for an exposure apparatus to reduce the variation in the alignment of the stepper. In order to keep the variation in the alignment within the allowable range, it is necessary to secure a sufficient design margin (processing margin) for the alignment, which hinders the reduction in the cell size. Therefore, there is a demand for a fine processing technique capable of reducing the design margin for alignment and reducing the cell size. As one of them, a self-aligned contact (SAC; which does not need to provide a design margin for alignment in a mask used for a contact hole opening process).
A Self Aligned Contact (Self Aligned Contact) technology has attracted attention.

FIG. 6A shows a field effect transistor (MOS transistor) having the above-mentioned SAC.
This will be described with reference to the sectional view of FIG. FIG. 6A shows one of the element formation regions (active regions) separated from each other by an element isolation insulating film (not shown) formed on the silicon substrate 1. The element isolation insulating film is formed by a known method, for example, a LOCOS method of thermally oxidizing a silicon substrate using a silicon nitride film as a mask, or an STI method of depositing an insulating film in an element isolation groove.

The gate insulating film 2 is formed on the active region.
Is formed, and a gate electrode 3 made of, for example, polysilicon is formed thereon. An offset insulating film 4 made of, for example, silicon oxide is formed on the upper layer of the gate electrode 3, and a sidewall 5 made of, for example, silicon oxide is formed on the side walls of the gate electrode 3 and the offset insulating film 4. Further, at both ends of the channel formation region located below the gate electrode, an LDD
A region 6 and a source / drain region 7 containing a high concentration of impurities are formed.

[0007] An etching stopper layer 8 made of, for example, silicon nitride is formed so as to cover the offset insulating film 4 and the side walls 5. On top of that,
For example, an interlayer insulating film 9 made of silicon oxide is formed. A contact hole 10 reaching the source / drain region 7 is opened in the interlayer insulating film 9, and the etching stopper layer 8 in a portion in contact with the source / drain region 7 is formed.
Has been removed. On the inner wall surface of the contact hole 10,
Upper layer wiring 11 connected to source / drain region 7 is formed.

Next, a method of manufacturing the above-described semiconductor device will be described with reference to FIGS. First,
An element isolation insulating film (not shown) is formed on the silicon substrate 1 by, for example, the LOCOS method, and the element formation regions are separated from each other. Subsequently, as shown in FIG.
Is thermally oxidized to form a gate insulating film 2 having a thickness of 5 to 10 nm.
Formed in the degree. For example, a CVD method (che
A polysilicon layer for the gate electrode 3 is deposited by a physical vapor deposition. Silicon oxide is deposited thereon by, for example, a CVD method to form an offset insulating film 4. Further, a resist 12 having a gate electrode pattern is formed on the offset insulating film 4 by a photolithography process.
Reactive ion etching (RI) is performed on the offset insulating film 4 and the polysilicon layer 3 using the resist 12 as a mask.
Anisotropic etching such as E) is performed to pattern the gate electrode.

Next, as shown in FIG. 6C, after the resist 12 is removed by ashing, a low-concentration conductive impurity is ion-implanted into the silicon substrate 1 using the offset insulating film 4 as a mask, and the LDD region 6 is removed. To form Next, silicon oxide is deposited on the entire surface and then etched back to form sidewalls 5 as shown in FIG. This etch back is performed by, for example, RIE.
Further, high concentration conductive impurities are ion-implanted into the silicon substrate 1 using the side walls 5 as a mask to form source / drain regions 7.

Next, as shown in FIG.
Silicon nitride is deposited on the entire surface by the VD method to form an etching stopper layer 8. Subsequently, as shown in FIG. 7C, the entire surface of the upper layer of the etching stopper layer 8 is
For example, silicon oxide is deposited to form an interlayer insulating film 9. As the interlayer insulating film 9, for example, an LP-TEOS film formed by oxidizing tetraethoxysilane (TEOS) under reduced pressure using ozone can be used. A resist 13 having a contact hole pattern is formed thereon by a photolithography process.

Next, as shown in FIG. 8A, the interlayer insulating film 9 is etched by, for example, RIE using the resist 13 as a mask, and a contact hole 10 for exposing the upper surface of the etching stopper layer 8 is opened. . This etching can be performed, for example, using a magnetron etcher under the following conditions. Etching conditions Etching gas: C ₄ F ₈ / CO / Ar = 15/300
/ 400 sccm Pressure: 5.3 Pa RF power (13.56 MHz): 1700 W

By performing etching under the above conditions, the selectivity of the interlayer insulating film 9 (silicon oxide) to the etching stopper layer 8 (silicon nitride) can be made about 10.

Next, as shown in FIG. 8B, the etching for etching the contact hole and the etching conditions are changed, a part of the etching stopper layer 8 in the contact hole is removed, and the source / drain is removed. Etching for exposing the region 7 is performed. This etching can be performed, for example, using a magnetron etcher under the following conditions. Etching conditions Etching gas: CHF ₃ / O ₂ / Ar = 10/10 //
50 sccm pressure: 5.3 Pa RF power (13.56 MHz): 600 W

Subsequently, after removing the resist 13, the inner wall of the contact hole 10 is covered with a conductor such as aluminum and the upper wiring 11 connected to the source / drain region 7 is formed. Through the above steps, the structure of the semiconductor device illustrated in FIG.

According to the above-described conventional method for manufacturing a semiconductor device, even if misalignment occurs when a contact hole pattern is formed in the resist 13, the etching of the contact hole opening is stopped once on the upper surface of the etching stopper layer 8. I do. Therefore, the gate electrode 3 is not exposed, and a short circuit between the gate electrode 3 and the upper wiring 11 can be prevented. In the step of changing the etching conditions and restarting the etching to remove the etching stopper layer 8, the gate electrode 3 is covered with the offset insulating film 4 and the side wall 5. Therefore,
The exposure of the gate electrode 3 is prevented, and the design margin on the mask for positioning in the contact hole opening step is not required.

[0016]

However, when a contact hole is opened by the above-mentioned conventional method, the following problems may occur. FIG. 7 (C)
In the process shown in FIG. 2, in order to perform etching for exposing the upper surface of the etching stopper layer 8 in the contact hole 10, the depth D ₁ of the interlayer insulating film 9 up to the etching stopper layer 8 above the gate electrode 3, 3 of the upper surface of the upper etching stopper layer 8 combined depth D ₂ to the upper surface of the etching stopper layer 8 between the gate electrodes, it is necessary to perform the depth of the etching of D ₁ + D _2.

In particular, when etching is performed for a depth D _2, a part of the etching stopper layer 8 is exposed,
It is necessary to etch the interlayer insulating film 9 under the condition that the selectivity is sufficiently secured with respect to the etching stopper layer 8. However, the selectivity of the interlayer insulating film (LP-TEOS film) 9 to the etching stopper layer 8 is about 10, which is not sufficient. 1/10 the thickness of the depth D ₂ to the etching stopper layer 8 is required, for example, D ₂
= 400 nm, required etching stopper layer 8
Has a thickness of 40 nm. Actually, since the thickness of the interlayer insulating film 9 varies, a thickness of 40 nm or more is required.

For example, if the etching stopper layer 8 has a thickness of 100 nm, there is no problem with the function as an etching stopper. In that case, however, a problem occurs that the interval between the gate electrodes 3 becomes narrow as shown in FIG. I do. FIG.
As shown in FIG. 2A, the portion of the interlayer insulating film 9 to be removed has a high aspect ratio by increasing the thickness of the etching stopper layer 8. Thus, as shown in FIG. 9B, in the etching step until the upper surface of the etching stopper layer 8 is exposed, an etch stop occurs in the middle, and the etching for exposing the source / drain region 7 in the next step is performed. You cannot do it.

As a method of avoiding the etch stop caused by the high aspect ratio as described above, in the etching process until the etching stopper layer 8 is exposed,
A small amount of oxygen (for example, 3 to 5 sccm) in the etching gas
Is added. According to this method, FIG.
As shown in (A), the above-described etch stop is prevented, but the selectivity of the interlayer insulating film 9 to the etching stopper layer 8 is also reduced.

As shown in FIG. 10A, when a part of the etching stopper layer 8 is etched away and disappears, the etching for exposing the source / drain region 7 is performed in a subsequent step. As shown in (2), a part of the offset insulating film 4 on the gate electrode 3 is etched, and a part of the gate electrode 3 is exposed. In this case, even if the upper layer wiring 11 is formed in the contact hole 10, the gate electrode 3 and the upper layer wiring 11 are short-circuited and the device does not operate normally.

Further, by adjusting the etching conditions optimally, it is possible to prevent the gate electrode 3 from being exposed,
Even if the drain region 7 is exposed and a contact hole can be opened, another problem remains. As described above, since the distance between the gate electrodes 3 is small, the contact hole 1
0, the surface area of the source / drain region 7 exposed is small, and the contact resistance increases. Alternatively, a method is also conceivable in which the offset insulating film 4 and the side walls 5 covering the gate electrode 3 are formed using silicon nitride to function as an etching stopper layer. According to this method, it is possible to increase the effective thickness of the etching stopper layer without reducing the distance between the gate electrodes, but this is not practical because the hot carrier resistance of the transistor is reduced.

The present invention has been made in view of the above-mentioned problems, and accordingly, the present invention provides a safe and reliable self-alignment device which has solved the problems such as an etch stop, a short circuit in a wiring, and an increase in contact resistance. It is an object to provide a method for manufacturing a semiconductor device having a contact.

[0023]

In order to achieve the above object, a method for manufacturing a semiconductor device according to the present invention comprises a step of forming a conductor layer on a semiconductor substrate, and a step of forming an offset insulating film on the conductor layer. Forming, forming a gate electrode by performing predetermined patterning on the offset insulating film and the conductor layer, forming a sidewall made of an insulator on the side surface of the gate electrode, Diffusing impurities into the semiconductor substrate as a mask to form source / drain regions;
Forming an etching stopper layer made of an insulator and covering the gate electrode and the side walls; and forming an organic insulating layer on the etching stopper layer such that an upper end thereof coincides with the height of the etching stopper layer on the gate electrode. Forming a film, filling the gap between the gate electrodes with the organic insulating film, forming an interlayer insulating film on the entire surface, providing an opening by etching the interlayer insulating film and the organic insulating film, Removing the organic insulating film in the opening while depositing a polymer layer that is a reaction product of etching on the surface of the etching stopper layer exposed in the opening; and removing the polymer layer. Removing the etching stopper layer at the bottom of the opening to expose the source / drain regions, Characterized by a step of forming a step of forming a hole, the upper wiring made of a conductor in the contact hole.

In the method for manufacturing a semiconductor device according to the present invention, preferably, the step of embedding the space between the gate electrodes with the organic insulating film includes the step of depositing the organic insulating film on the entire surface including on the gate electrode. Performing an etch-back process by anisotropic etching until the upper end of the organic insulating film matches the height of the etching stopper layer on the gate electrode. In the method for manufacturing a semiconductor device according to the present invention, preferably, the organic insulating film is an organic SOG.
(Spin on glass) film.

In the method of manufacturing a semiconductor device according to the present invention, preferably, the step of forming an opening by etching the interlayer insulating film and the organic insulating film is performed by using an etching gas containing a fluorine atom. Step, wherein the polymer layer is a fluorocarbon polymer layer containing carbon atoms and fluorine atoms. In the method of manufacturing a semiconductor device according to the present invention, more preferably, the etching gas is a gas containing CF ₄ or C ₄ F ₈ .

In the method of manufacturing a semiconductor device according to the present invention, preferably, the offset insulating film and the sidewall are made of silicon oxide. In the method of manufacturing a semiconductor device according to the present invention, preferably, the etching stopper layer is made of silicon nitride. Alternatively, in the method of manufacturing a semiconductor device according to the present invention, preferably, the etching stopper layer is made of silicon nitride oxide. Alternatively, in the method of manufacturing a semiconductor device according to the present invention, preferably, the etching stopper layer is made of aluminum oxide.

In the method of manufacturing a semiconductor device according to the present invention, preferably, the interlayer insulating film is made of silicon oxide. Preferably, the method for manufacturing a semiconductor device according to the present invention, wherein the gate electrode is used as a mask on the semiconductor substrate,
An impurity of the same conductivity type as the source / drain region;
Diffusion at a lower concentration than the source / drain regions,
The method is characterized by including a step of forming a DD (lightly doped drain) region.

This allows the polymer layer to function as a protective film during etching for opening a contact hole,
The etching selectivity of the interlayer insulating film or the organic insulating film with respect to the etching stopper layer can be increased. Therefore, the thickness of the etching stopper layer can be reduced, and the distance between the gate electrodes can be prevented from being reduced. Since the contact area is sufficiently secured, an increase in contact resistance can be suppressed. According to the method of manufacturing a semiconductor device of the present invention, since a contact hole is formed in a self-aligned manner using an etching stopper layer, it is necessary to provide a design margin for alignment in a mask for opening a contact hole. In addition, the size of the formed pattern can be reduced.

Further, according to the method of manufacturing a semiconductor device of the present invention, it is necessary to use the same material as the etching stopper layer for the offset insulating film and the side wall in order to increase the effective thickness of the etching stopper layer. Absent. Therefore, an insulating film having high hot carrier resistance, preferably silicon oxide, can be used for the offset insulating film and the side wall, and a stable and highly reliable self-aligned contact hole can be formed.

[0030]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of the method for manufacturing a semiconductor device according to the present invention will be described below with reference to the drawings. FIG. 1A is a cross-sectional view of a semiconductor device manufactured by the method for manufacturing a semiconductor device according to the present embodiment. FIG.
1A shows one of the element formation regions (active regions) separated from each other by an element isolation insulating film (not shown) formed on the silicon substrate 1. The element isolation insulating film is formed by a known method, for example, a LOCOS method of thermally oxidizing a silicon substrate using a silicon nitride film as a mask, or an STI method of depositing an insulating film in an element isolation groove.

The gate insulating film 2 is formed on the active region.
Is formed, and a gate electrode 3 made of, for example, polysilicon is formed thereon. An offset insulating film 4 made of, for example, silicon oxide is formed on the upper layer of the gate electrode 3, and a sidewall 5 made of, for example, silicon oxide is formed on the side walls of the gate electrode 3 and the offset insulating film 4. Further, at both ends of the channel formation region located below the gate electrode, an LDD
A region 6 and a source / drain region 7 containing a high concentration of impurities are formed.

An etching stopper layer 8 made of, for example, silicon nitride is formed so as to cover the offset insulating film 4 and the side walls 5. An organic insulating film (organic SOG film) 14 is formed as a first interlayer insulating film up to the upper end of the etching stopper layer 8 above the gate electrode, and a second interlayer insulating film (hereinafter, referred to as silicon oxide) made of, for example, silicon oxide is formed thereon. An interlayer insulating film is formed.) 9 is formed. A contact hole 10 reaching the source / drain region 7 is opened in the interlayer insulating film 9 and the organic SOG film 14, and a portion of the etching stopper layer 8 in contact with the source / drain region 7 is removed. An upper wiring 11 connected to the source / drain region 7 is formed on the inner wall surface of the contact hole 10.

Next, a method of manufacturing the semiconductor device according to the present embodiment will be described with reference to the drawings. First, an element isolation insulating film (not shown) is formed on the silicon substrate 1 by, for example, the LOCOS method, and the element formation regions are separated from each other. Subsequently, as shown in FIG. 1B, the surface of the silicon substrate 1 is thermally oxidized to form a gate insulating film 2 with a thickness of about 5 to 10 nm. A polysilicon layer for the gate electrode 3 is deposited thereon by, for example, a CVD method. Silicon oxide is deposited on the upper layer by, for example, a CVD method using TEOS as a raw material to form an offset insulating film 4.

Next, as shown in FIG. 1C, a resist 12 having a gate electrode pattern is formed on the offset insulating film 4 by a photolithography process.
Reactive ion etching (RI) is performed on the offset insulating film 4 and the polysilicon layer 3 using the resist 12 as a mask.
Anisotropic etching such as E) is performed to pattern the gate electrode.

Next, as shown in FIG. 2A, after the resist 12 is removed by ashing, low concentration conductive impurities are ion-implanted into the silicon substrate 1 using the offset insulating film 4 as a mask, and the LDD region 6 is removed. To form continue,
As shown in FIG. 2B, after a silicon oxide layer 5 ′ is deposited on the entire surface so as to cover the offset insulating film 4,
Etchback is performed as shown in FIG. 2C to form a sidewall 5. This etch back is performed, for example, by RI
Perform by E.

Next, as shown in FIG. 3A, high concentration conductive impurities are ion-implanted into the silicon substrate 1 using the sidewalls 5 as a mask to form source / drain regions 7. Subsequently, as shown in FIG.
Silicon nitride is deposited on the entire surface by the method D to form an etching stopper layer 8. Etching stopper layer 8
Any material other than silicon nitride can be used as long as it can have a sufficient selectivity with respect to a silicon oxide-based material such as LP-TEOS. For example, a material such as silicon nitride oxide or aluminum oxide can be used. Is mentioned.

Thereafter, as shown in FIG.
After applying the OG film 14 on the entire surface, a heat treatment is performed at 400 ° C. for 30 minutes to bake the coating film. Subsequently, FIG.
As shown in (2), etch back by anisotropic etching such as RIE is performed to flatten the gate electrode at the position where the upper surface of the etching stopper layer 8 is exposed. Due to this etch back, the organic SOG film 14 remains only between the gate electrodes including the contact hole formation region.

Next, as shown in FIG.
For example, silicon oxide is deposited on the entire surface so as to cover the G film 14 and the etching stopper layer 8 to form an interlayer insulating film 9. As the interlayer insulating film 9, for example, an LP-TEOS film formed by oxidizing tetraethoxysilane (TEOS) under reduced pressure using ozone can be used. A resist 13 having a contact hole pattern is formed thereon by a photolithography process.

Next, as shown in FIG. 4C, using the resist 13 as a mask, the interlayer insulating film 9 and the organic SOG film 1 are formed.
4 is a contact hole 1 for performing etching such as RIE to expose the upper surface of the etching stopper layer 8.
Open 0 This etching can be performed, for example, using a magnetron etcher under the following conditions. Etching conditions Etching gas: C ₄ F ₈ / CO / Ar = 15/300
/ 400 sccm Pressure: 5.3 Pa RF power (13.56 MHz): 1700 W

When a contact hole is opened in the interlayer insulating film 9 under the above conditions and the etching of the organic SOG film 14 is started, a fluorocarbon-based etching gas is dissociated by collision with electrons in plasma, and CF _x molecules are removed. Generate
It adsorbs on the surface of the organic SOG film 14. Organic SOG film 14
When ions bombard CF _x molecules adsorbed on the surface of
With C _x F _y O _z layer is formed, SiF from the surface
₄ , volatile reaction products such as SiF ₂ , CO, CO ₂ , COF ₂ are desorbed, and etching proceeds.

When excess carbon etched from the organic SOG film 14 reacts with radicals, fluorocarbon is formed and is deposited thinly on the etching stopper layer 8.
Since the etching stopper layer 8 made of silicon nitride has a low oxygen content, carbon is not removed, and the fluorocarbon polymer layer 15 is formed on the surface. Since the fluorocarbon polymer layer 15 functions as a protective film,
The interlayer insulating film (LP-
The selectivity of the TEOS film 9 can be about 15 to 20.

Next, as shown in FIG. 5A, light ashing is performed to remove the fluorocarbon polymer layer 15 deposited on the etching stopper layer 8. This light ashing is performed for about 10 seconds using oxygen plasma. Next, as shown in FIG. 5B, the etching for etching the contact hole and the etching conditions are changed, and the etching for removing the etching stopper layer 8 exposed at the bottom of the contact hole 10 is performed. This etching can be performed, for example, using a magnetron etcher under the following conditions. Etching conditions Etching gas: CHF ₃ / O ₂ / Ar = 10/10 //
50 sccm pressure: 5.3 Pa RF power (13.56 MHz): 600 W

Subsequently, after the resist 13 is removed, the inner wall of the contact hole 10 is covered with a conductor such as aluminum, and the upper wiring 11 connected to the source / drain region 7 is formed. According to the method for manufacturing a semiconductor device of the present embodiment, the organic SOG film 14 is used as an interlayer insulating film near the surface of the silicon substrate 1. Organic S
Since the OG film 14 has a lower resistance to high-temperature heat treatment than the interlayer insulating film 9 made of silicon oxide, a low-melting-point metal is suitable as a material of the upper wiring 11 buried in the contact hole. In order to use a polysilicon wiring as the upper wiring 11, it is necessary to perform processing by a high-temperature heat treatment.
Low melting metal materials such as aluminum and aluminum alloys are particularly preferred.

Through the above steps, the semiconductor device shown in FIG. 1A is obtained. The method for manufacturing a semiconductor device according to the present invention includes:
The present invention can be applied to any semiconductor memory including a MOS transistor such as a DRAM or an SRAM, or a semiconductor device having a multilayer wiring and a self-aligned contact hole formed therein, such as a bipolar transistor and an A / D converter.

According to the method of manufacturing a semiconductor device according to the embodiment of the present invention, since a contact hole is formed in a self-aligning manner using an etching stopper layer, a mask for opening a contact hole is used for positioning. There is no need to provide a design margin, and the formation pattern can be reduced. Further, according to the method for manufacturing a semiconductor device of the present embodiment, the etching selectivity of the interlayer insulating film (silicon oxide) to the etching stopper layer can be improved, and the etching stopper layer can be made thinner. This prevents the interval between the gate electrodes from being reduced, so that a contact area can be secured and an increase in contact resistance can be suppressed.

According to the method of manufacturing a semiconductor device of the present embodiment, it is not necessary to use the same material as the etching stopper layer for the offset insulating film and the side wall in order to increase the effective thickness of the etching stopper layer. . Therefore, an insulating film having high hot carrier resistance can be used for the offset insulating film and the sidewall, and a stable and highly reliable self-aligned contact hole can be formed.

The method of manufacturing a semiconductor device according to the present invention is not limited to the above embodiment. For example, in this embodiment, the gate electrode is a single polysilicon layer, but a polycide structure (two-layer structure) in which a tungsten silicide layer is stacked on the upper layer, or a two-layer structure made of large grain polysilicon is stacked. And a three-layer structure in which a silicide layer is stacked thereover. In addition, various changes can be made without departing from the gist of the present invention.

[0048]

According to the method of manufacturing a semiconductor device of the present invention, the etching selectivity of the interlayer insulating film with respect to the etching stopper layer is improved, and the etching stopper layer can be made thinner. And the etch stop can be prevented. Therefore, it is possible to form a stable and highly reliable self-aligned contact in the semiconductor device in which a wiring short-circuit and an increase in contact resistance are suppressed.

[Brief description of the drawings]

1A is a cross-sectional view of a semiconductor device manufactured by a method of manufacturing a semiconductor device of the present invention, and FIGS. 1B and 1C show manufacturing steps of the method of manufacturing a semiconductor device of the present invention; It is sectional drawing.

FIGS. 2A to 2C are cross-sectional views illustrating manufacturing steps of a method for manufacturing a semiconductor device according to the present invention.

FIGS. 3A to 3C are cross-sectional views illustrating manufacturing steps of a method for manufacturing a semiconductor device according to the present invention.

4A to 4C are cross-sectional views illustrating manufacturing steps of a method for manufacturing a semiconductor device according to the present invention.

FIGS. 5A and 5B are cross-sectional views illustrating manufacturing steps of a method for manufacturing a semiconductor device according to the present invention.

6A is a cross-sectional view of a semiconductor device manufactured by a conventional method of manufacturing a semiconductor device, and FIGS. 6B and 6C are cross-sectional views illustrating manufacturing steps of the conventional method of manufacturing a semiconductor device. It is.

FIGS. 7A to 7C are cross-sectional views illustrating a manufacturing process of a conventional method for manufacturing a semiconductor device.

FIGS. 8A to 8C are cross-sectional views illustrating manufacturing steps of a conventional method for manufacturing a semiconductor device.

FIGS. 9A and 9B are cross-sectional views illustrating manufacturing steps of a conventional method for manufacturing a semiconductor device.

FIGS. 10A and 10B are cross-sectional views illustrating manufacturing steps of a conventional method for manufacturing a semiconductor device.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Silicon substrate, 2 ... Gate insulating film, 3 ... Gate electrode, 4 ... Offset insulating film, 5 ... Side wall, 5 '
... Silicon oxide layer, 6 LDD region, 7 source / drain region, 8 etching stopper layer, 9 interlayer insulating film, 10 contact hole, 11 upper wiring, 12,
13: resist, 14: organic SOG film, 15: fluorocarbon polymer layer.

 ──────────────────────────────────────────────────続 き Continued on the front page F term (reference) RR06 RR08 RR25 SS04 SS11 SS13 SS22 TT04 TT07 VV04 XX02 XX09 5F040 DA10 DA14 DB01 EA08 EA09 EF02 EF03 EH02 EH05 EJ03 EJ08 EK01 FA02 FA05 FA10 FA12 FA16 FA18 FB01 FC21 FC22 FC27

Claims (11)

[Claims] A step of forming a conductor layer on the semiconductor substrate; a step of forming an offset insulating film on the conductor layer; and performing predetermined patterning on the offset insulating film and the conductor layer. Forming a gate electrode; forming a sidewall made of an insulator on a side surface of the gate electrode; and forming a source / drain region by diffusing an impurity into the semiconductor substrate using the sidewall as a mask. Forming an etching stopper layer made of an insulator on the entire surface and covering the gate electrode and the sidewalls; Forming an organic insulating film so as to match, and filling the space between the gate electrodes with the organic insulating film; Forming an interlayer insulating film on the entire surface, etching the interlayer insulating film and the organic insulating film to form an opening, and forming a surface of the etching stopper layer exposed in the opening with an etching reaction product. Removing the organic insulating film at the opening while depositing a certain polymer layer; removing the polymer layer; removing the etching stopper layer at the bottom of the opening;
A method of manufacturing a semiconductor device, comprising: a step of exposing the source / drain region to form a contact hole; and a step of forming an upper wiring made of a conductor in the contact hole. 2. The step of embedding the organic insulating film between the gate electrodes with the step of depositing the organic insulating film on the entire surface including on the gate electrode, wherein the upper end of the organic insulating film is formed on the gate electrode. Performing an etch-back by anisotropic etching until the height of the etching stopper layer coincides with the height of the etching stopper layer.
The manufacturing method of the semiconductor device described in the above. 3. The method according to claim 1, wherein the organic insulating film is formed of an organic SOG (spin).
3. The method for manufacturing a semiconductor device according to claim 2, which is an on-glass film. 4. The step of providing an opening by etching the interlayer insulating film and the organic insulating film is a step of performing etching by using an etching gas containing a fluorine atom. 2. The method for manufacturing a semiconductor device according to claim 1, wherein the method is a fluorocarbon polymer layer containing a fluorine atom. 5. An etching gas comprising CF ₄ or C ₄
The method according to claim 4, wherein a gas containing F _8. 6. The method according to claim 1, wherein said offset insulating film and said sidewall are made of silicon oxide. 7. The method according to claim 1, wherein said etching stopper layer is made of silicon nitride. 8. The method according to claim 1, wherein said etching stopper layer is made of silicon nitride oxide. 9. The method according to claim 1, wherein said etching stopper layer is made of aluminum oxide. 10. The method according to claim 1, wherein said interlayer insulating film is made of silicon oxide. 11. An LDD (lightly doped drain) is formed by diffusing impurities of the same conductivity type as the source / drain regions into the semiconductor substrate at a lower concentration than the source / drain regions using the gate electrode as a mask.
2. The method for manufacturing a semiconductor device according to claim 1, further comprising the step of: (in) forming a region.