JP2000068474A - Semiconductor storage device - Google Patents

Abstract

(57) [Problem] To provide a semiconductor memory device capable of preventing disturb deterioration at the time of self-refresh and reducing a refresh current. SOLUTION: This is a 256MDRAM having a negative voltage VB.
For normal control and shallow control of B, there are two systems, a voltage for normal control and a voltage for shallow control, and controls supply to the mat in self refresh in accordance with the mat select address. . In the refresh cycle S1, the mat n is a refresh period, and a negative voltage of about -1 V is supplied by normal control. Mat n +
In the case of No. 1, since the refresh period is approaching, a negative voltage of about -1 V is supplied by the normal control. Mat n + 2
Also, since the refresh period is approaching, the control is switched from the shallow control to the normal control at the timing T1. Since the mat n + 3 has time until the refresh period, a negative voltage of about -0.5 V is supplied by the shallow control.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device technology, and more particularly to a technology effective when applied to a semiconductor memory device such as a DRAM suitable for preventing disturb deterioration at the time of self-refresh and reducing a refresh current. .

[0002]

2. Description of the Related Art For example, as a technique studied by the present inventor, a memory cell substrate of a DRAM as an example of a semiconductor memory device is uniformly provided in terms of prevention of memory cells from minority carriers and controllability of transfer MOS transistors. Negative voltage (for example, VBB = −
1.2V) can be considered.

[0003] As a technique related to such a semiconductor memory device such as a DRAM, for example,
The technology described in the literature of “Advanced Electronics I-9 Ultra LSI Memory” issued by Baifukan Co., Ltd. on May 5 is mentioned.

[0004]

Incidentally, in the above-mentioned DRAM, it is necessary to make the voltage level of the negative voltage shallow in order to increase the capability of the pause refresh in order to reduce the current. That is, it is necessary to relax the electric field between the memory cell storage node diffusion layer and the substrate. However, if the negative voltage is made shallow, the threshold voltage of the transistor is reduced by the substrate effect, so that the disturb refresh resistance may be deteriorated. Therefore, it is necessary for the negative voltage to take an optimum value for both.

SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor memory device such as a DRAM which can prevent disturb deterioration at the time of self-refresh and reduce the refresh current.

The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[0007]

SUMMARY OF THE INVENTION Among the inventions disclosed in the present application, the outline of a representative one will be briefly described.
It is as follows.

That is, the semiconductor memory device according to the present invention utilizes a triple well structure in which an array substrate of a memory cell array is surrounded by an N-type well region / a relatively deep deep well region and the array substrate is separated for each unit mat. Means for controlling the potential of the negative voltage applied to the array substrate for each unit mat in the memory cell array or for each group of a plurality of unit mats in the self-refresh mode in which the word line rise order is determined. .

In this configuration, a unit mat or a group of a plurality of unit mats having a sufficiently long time from the refresh to the next refresh has a shallow negative voltage level, and the unit mat or the plurality of unit mats whose refresh is approaching. The second group is intended to restore the normal negative voltage level.

For this purpose, there are provided two systems, that is, a normal negative voltage and a voltage obtained by reducing the negative voltage, and at the time of self-refresh, the system is switched to one of them in accordance with a mat selection address.

Therefore, according to the semiconductor memory device, the pause time can be extended by making the negative voltage shallower, and the disturb deterioration can be prevented by returning the negative voltage to the normal level when the mat is selected. By increasing the self-refresh time, the refresh current can be reduced. As a result, it is possible to reduce the low power version current and improve the yield of low power products.

[0012]

Embodiments of the present invention will be described below in detail with reference to the drawings.

FIG. 1 is a schematic layout diagram and a partially enlarged view showing a semiconductor memory device according to an embodiment of the present invention. FIG. 2 is a sectional view showing a main part of the semiconductor memory device according to the embodiment. FIG. 5 is a layout diagram and a timing chart showing a negative voltage control method for each unit mat in the memory cell array in the self-refresh mode.

First, a schematic configuration of the semiconductor memory device according to the present embodiment will be described with reference to FIG.

The semiconductor memory device of the present embodiment is, for example, a 256 MDRAM. This memory chip 10 includes a main row decoder region 11, a main word driver region 12, a column decoder region 13, a peripheral circuit / bonding pad region 14, Memory cell array region 15,
Sense amplifier region 16, sub-word driver region 17,
The intersection region 18 and the like are formed on a single semiconductor chip by a known semiconductor manufacturing technique.

In this 256 MDRAM, the basic memory cell array in memory cell array region 15 is, for example, a pair of 512 word lines × 512 bit lines. FIG.
Is an example of a 4-bank configuration divided into four. The word lines extend in the long side direction and the bit lines extend in the short side direction. Using a hierarchical word line configuration and a multi-segmented bit line configuration, 256 Mbits are constituted by 16 k word lines × 16 k bit line pairs in total.

In this memory chip 10, a main word line and a predecoder line for controlling the driver of the sub-word driver region 17 from the main row decoder region 11 and the main word driver region 12 at the center of the long side are output to the left and right. The center of the short side is a peripheral circuit / bonding pad region 14, and a column decoder region 13 is placed between the peripheral circuit / bonding pad region 15 and the memory cell array region 15. The column selection line, which is the output of the column decoder, is connected to the memory cell array region 15
To control a number of sense amplifiers.

As shown in the partial enlarged view of FIG. 1B, sub-word driver regions 17 are arranged on both left and right ends of the memory cell array region 15, and sense amplifier regions 16 are arranged on both upper and lower sides. Therefore, the memory cell array region 1
5 is a sense amplifier area 16 and a sub word driver area 1
Surrounded by seven. A region where the sub-word driver region 17 and the sense amplifier region 16 intersect is called an intersection region 18 and is provided with a sense amplifier driver, an input / output line switch circuit, and the like.

The memory cell array area 15 of this DRAM
Has a triple well structure as shown in FIG. 2, for example. In this triple well structure, a P-type well region PWEL in a memory cell array is surrounded by an N-type well region NWEL / a relatively deep deep well region NISO to prevent noise from a peripheral circuit to a memory cell.
It is widely used in DRAMs of 64 Mbits or later as a means for improving the performance of S transistors and enhancing electrostatic protection.

As shown in FIG. 2, the memory cell array is formed on the array substrate of the P-type well region PWEL, and a negative voltage VBB for its operation is applied. This P-type well region PW
EL is covered with a deep well region NISO, and a boosted voltage VPP is applied to its potential. The sense amplifier is removed from the deep well region NISO, and the lower part thereof is a P-type substrate P
SUB, and the ground voltage VSS is applied to this P-type substrate PSUB.
Is applied. The boosted voltage VPP for the sense amplifier operation is applied to the N-type well region NWEL of the PMOS of the sense amplifier. In the triple well structure of this memory cell array, in the present embodiment, P is set for each unit mat of separated memory cells or for each group of a plurality of unit mats.
The negative voltage VBB applied to the mold well region PWEL is controlled.

Next, a method of controlling the negative voltage VBB in the self-refresh cycle will be described with reference to FIGS. FIG. 3 shows an example of negative voltage VBB control in the memory cell array,
FIG. 4 shows an example of negative voltage VBB control for each unit mat, and FIG. 5 shows an example of negative voltage VBB control timing.

In order to control the negative voltage VBB for each unit mat in the memory cell array, there is provided means for controlling the potential of the negative voltage VBB applied to the array substrate for each unit mat in the memory cell array. And a voltage for shallowing control in the memory chip 10, and a negative voltage VBB applied to the array substrate corresponding to the mat selection address at the time of self-refresh.
Is controlled.

As shown in FIG. 3, in the self-refresh cycle, the unit mats of two banks arranged with the main row decoder region 11 interposed among the four banks shown in FIG. 1 are simultaneously accessed. In this self-refresh mode, the cycle in which mats 0 to 15 are selected is, for example, dispersion 8 Kref, Tref = 128 m
Assuming a s, 512 WL / mat configuration, one mat is accessed every 128 ms for a period of 8 ms.
Accordingly, there is no access for a time of 120 ms, and the shallow control of the negative voltage VBB is performed in the absence of this access.

For example, as shown in FIG. 4, in the self-refresh mode, the word line WL is activated at a period of about 15.6 μs, and this is repeated 512 times for one mat. Therefore, it takes about 8 ms per mat. This is repeated for 16 mats from mat 0 to mat 15 in order, resulting in a refresh cycle of about 128 ms. In this case, for example, when the mat 7 is in a refresh cycle, normal control of the negative voltage VBB is performed including the mat 7 and the mats 8 and 9 whose refresh cycle is approaching. The other mats 0 to 6 and mats 10 to 15 except the mats 7 to 9 have time until the next refresh cycle, so that the negative voltage VBB shallow control is performed.

The normal control and the shallowening control of the negative voltage VBB are performed, for example, at the timing shown in FIG. For this control, for example, as a negative voltage VBB,
It has two systems, a voltage of about -1 V for normal control and a voltage of about -0.5 V for shallow control.
The supply of the mat 15 to the P-type well region PWEL is controlled.

(1) Refresh cycle S1 The mat n is a refresh period, and a negative voltage VBB of about -1 V is supplied by normal control of the negative voltage VBB. Since the refresh period is approaching for the mat n + 1, the negative voltage VBB of about -1 V is supplied by the normal control. Since the refresh period is approaching for the mat n + 2, the control is switched from the shallow control to the normal control at the timing T1. Since the mat n + 3 has a time until the refresh period, the negative voltage VBB is controlled to −0.5 by the shallow control of the negative voltage VBB.
A negative voltage VBB of about V is supplied.

(2) Refresh cycle S2 Since the refresh period of the mat n has been completed, the normal control is switched to the shallow control at timing T2. The mat n + 1 is a refresh period, and a negative voltage VBB of about -1 V is supplied by normal control. Mat n +
In No. 2, since the refresh period is approaching, a negative voltage VBB of about -1 V is supplied by normal control. Since the refresh period is approaching for the mat n + 3, the control is switched from the shallow control to the normal control at the timing T2.

(3) Refresh cycle S3 Since the mat n has time until the next refresh period, a negative voltage VBB of about -0.5 V is supplied by the shallow control. Since the refresh period of the mat n + 1 has been completed, the normal control is switched to the shallowening control at timing T3. Mat n + 2 is a refresh period,
A negative voltage VBB of about -1 V is supplied by normal control. Since the refresh period is approaching for the mat n + 3, the negative voltage VBB of about -1 V is supplied by the normal control.

(4) Refresh cycle S4 Since the mat n has time until the next refresh period, the supply of the negative voltage VBB of about -0.5 V is continued by the shallow control. Since the mat n + 1 has time until the next refresh period, a negative voltage VBB of about -0.5 V is supplied by the shallow control. Since the refresh period has ended for the mat n + 2, the normal control is switched to the shallow control at the timing T4. The mat n + 3 is a refresh period, and a negative voltage VBB of about -1 V is supplied by normal control.

(5) Refresh cycle S5 Since the mat n has time until the next refresh period, the supply of the negative voltage VBB of about -0.5 V is still continued by the shallow control. Since the mat n + 1 has time until the next refresh period, -0.5 V is applied by the shallow control.
Supply of the negative voltage VBB is continued. Mat n
Since +2 has time until the next refresh period, a negative voltage VBB of about -0.5 V is supplied by the shallowening control. Since the refresh period has ended for the mat n + 3, the normal control is switched to the shallow control at the timing T5.

As described above, the negative voltage VBB of about -1 V is supplied to the refresh period or the mat which is approaching the refresh period by the normal control, and the refresh period ends and the next refresh period is completed. For mats that have time, -0 by the shallow control.
A negative voltage VBB of about 5 V can be supplied.

Therefore, according to the semiconductor memory device of the present embodiment, the pause time of a mat which has a time until the refresh period can be extended by performing the shallow control of the negative voltage. Further, with respect to the mat in the refresh period, disturb deterioration can be prevented by performing normal control of the negative voltage. This allows
The refresh time can be improved, the self-refresh time can be increased, and the refresh current can be reduced.

Although the invention made by the inventor has been specifically described based on the embodiment, the invention is not limited to the embodiment, and various modifications may be made without departing from the gist of the invention. It goes without saying that it is possible.

For example, in the above-described embodiment, the case where the negative voltage is controlled for each unit mat in the self-refresh mode has been described. However, the present invention is not limited to this. It is also possible to control the negative voltage.

Although the description has been given of the 256-M DRAM having the 4-bank structure, other bank structures such as 8-bank,
Other capacity configurations such as 4Mbit, and synchronous D
The present invention can be widely applied to other semiconductor storage devices such as a RAM and a logic embedded DRAM.

[0036]

Advantageous effects obtained by typical ones of the inventions disclosed in the present application will be briefly described.
It is as follows.

(1) In the self refresh mode,
Means for controlling the potential of the negative voltage applied to the array substrate for each unit mat in the memory cell array or for each group of a plurality of unit mats, and a unit mat or a unit mat having a sufficiently long time until the next refresh after refreshing. By taking the negative voltage level shallow for the group, it becomes possible to extend the pause time by making the negative voltage shallow.

(2) In the above (1), the unit mat or group approaching the refresh is restored to the normal negative voltage level, and the negative voltage is returned to the normal level when the mat is selected, thereby preventing the disturb deterioration. It becomes possible.

(3) According to (1) and (2), the refresh time can be improved, and the refresh current can be reduced by increasing the self-refresh time. It is possible to reduce the power plate current / improve the yield of low power products.

[Brief description of the drawings]

FIGS. 1A and 1B are a schematic layout diagram and a partially enlarged view showing a semiconductor memory device according to an embodiment of the present invention.

FIG. 2 is a sectional view showing a main part of the semiconductor memory device according to the embodiment of the present invention;

FIG. 3 is a layout diagram showing a negative voltage control method for each unit mat in a memory cell array in a self-refresh mode in the semiconductor memory device according to one embodiment of the present invention;

FIG. 4 is an explanatory diagram showing a negative voltage control method for each unit mat in a memory cell array in a self-refresh mode in the semiconductor memory device according to one embodiment of the present invention;

FIG. 5 is a timing chart showing a negative voltage control method for each unit mat in a memory cell array in a self-refresh mode in the semiconductor memory device according to one embodiment of the present invention;

[Explanation of symbols]

 Reference Signs List 10 memory chip 11 main row decoder area 12 main word driver area 13 column decoder area 14 peripheral circuit / bonding pad area 15 memory cell array area 16 sense amplifier area 17 sub word driver area 18 intersection area PWEL P-type well area NISO deep well area PSUB P Type substrate NWEL N-type well region

Claims (4)

[Claims] 1. A semiconductor memory device having a triple-well structure in which an array substrate of a memory cell array is separated for each unit mat, and in a self-refresh mode, for each unit mat in the memory cell array or a group of a plurality of unit mats. A semiconductor memory device, comprising: a control unit for controlling a potential of a negative voltage applied to the array substrate every time. 2. The semiconductor memory device according to claim 1, wherein said control means takes the level of said negative voltage shallow with respect to said unit mat or a group of said plurality of unit mats between refreshes, and refreshing is performed. The semiconductor memory device according to claim 1, wherein the negative voltage is restored to a normal level for the approaching unit mat or the group of the plurality of unit mats. 3. The semiconductor memory device according to claim 1, wherein said negative voltage has two systems of a normal negative voltage and a voltage obtained by reducing said negative voltage, and one of said two systems corresponds to a mat selection address. A semiconductor memory device characterized by switching to one. 4. The semiconductor memory device according to claim 1, wherein the semiconductor memory device is a DRAM.