JP2008172081A - Semiconductor memory device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor memory device with reduced power consumption.
A semiconductor memory device includes a first mode in which operations including data reading and data writing and refresh are performed, and a second mode in which refresh is autonomously repeated without data reading and data writing; Have The element isolation region 12 is formed on the surface of the semiconductor substrate 11, partitions the element region, has an insulating film 31 on the surface, and includes a conductor 32 inside. The plurality of memory cells are formed in the element region, and each includes a capacitor 14 and a MOS transistor 16. The potential generation circuit 4 applies a first potential to the conductor in the first mode, and applies a second potential higher than the first potential in the second mode.
[Selection] Figure 3

Description

  The present invention relates to a semiconductor memory device, and more particularly to a dynamic random access memory (DRAM) used as a low power consumption memory mounted in, for example, a portable device.

  In the DRAM, the power consumption can be reduced by reducing the power consumed by the refresh operation in the standby mode and / or the self-refresh mode. For this purpose, it is effective to lengthen the data retention time of the DRAM cell to make the refresh interval longer. Note that the self-refresh mode is a mode that can be shifted by the DRAM being supplied with a command, and in this case, the DRAM autonomously repeats refresh to hold data.

  In recent years, for example, as a RAM mounted on a portable device, a DRAM cell having a 1 transistor + 1 capacitor configuration may be used instead of an SRAM (static RAM) cell (pseudo SRAM). The refresh is autonomously repeated even in the standby mode of the pseudo SRAM.

  On the other hand, the cell miniaturization increases the leakage current in the cell transistor and the leakage current between the pn junction (hereinafter simply referred to as the pn junction) between the storage node and the well. Data stored in the memory cell is easily lost. As a result, the data retention time is shortened and it is difficult to reduce the power required for refresh. In particular, in the design rule finer than 100 nm, the phenomenon that the electric field generated by the charge in the adjacent memory cell acts on the adjacent memory cell through the element isolation region and the charge of the cell capacitor leaks has become prominent.

  Assume that a memory cell adjacent to a memory cell holding “1” data holds “0” data (Low Level). In this state, the depletion layer width at the pn junction of the cell capacitor of the memory cell is shortened by the electric field generated by the adjacent memory cell. As a result, a kind of junction leakage current TFE (thermionic field emission) current increases, and the retention time of “1” data is shortened (Non-patent Document 1). In order to lengthen the depletion layer between the pn junctions of the cell capacitor, it is conceivable to reduce the amount of impurities injected into the channel portion. However, if the amount of impurities implanted into the channel portion is reduced, the threshold voltage of the cell transistor is lowered. When the threshold voltage is small, the leakage current in the transistor increases. In particular, when the bit line is held at a low potential for a long time at the time of writing or reading in the normal operation mode, a large amount of charge in the cell capacitor holding “1” data passes through the cell transistor. It leaks into.

  When the adjacent memory cell holds “1” data, a channel is induced on the side surface of the active region of the cell transistor. As a result, the threshold value of the cell transistor holds the data “0” in the adjacent memory cell. Lower than the case. Accordingly, the leakage current in the cell transistor increases as in the case where the impurity implantation amount into the channel portion is reduced. In response to the threshold voltage of the cell transistor being lowered by an electric field from an adjacent memory cell holding “1” data, a shield conductor is embedded in an element isolation insulating film having an STI (shallow trench isolation) structure. There has been proposed a technique for applying a negative potential to the non-patent document 2 (Non-patent Document 2). According to this technique, it is possible to avoid the adjacent memory cell holding “1” data from lowering the threshold voltage of the cell transistor. As a result, the leakage current in the cell transistor can be suppressed.

  However, in the technique of Non-Patent Document 2, the depletion layer width at the pn junction between the storage node and the p-well is shortened by the electric field generated by the negative potential of the shield conductor. As a result, as in the case where the adjacent memory cell holds “0” data, the increase in the TFE current increases the pn junction leakage current. Therefore, the refresh interval cannot be set long.

Thus, if the amount of impurities to the channel region is reduced as a countermeasure against the pn junction leakage current, the leakage current in the cell transistor increases. On the other hand, when a shield conductor is used as a measure against a leakage current in a cell transistor that is prominent when adjacent memory cells hold “1” data, a pn junction leakage current increases. That is, each measure is in a contradictory direction from the viewpoint of cell transistor threshold voltage control, and it is difficult to satisfy both. For this reason, at present, the pn junction leakage current is dealt with by using the STI shield, and for the leakage current in the cell transistor, it is allowed to increase the refresh current, and the refresh interval should be set short. I must. This means that power consumption due to refresh increases.
T. Hamamoto, et al., On the Retention Time Distribution of Dynamic Random Access Memory (DRAM), "IEEE transactions on electron devices", June 1998, VOL 45, No. 6, p.1300-1309 Jai-hoon Sim, et al., High-Performance Cell Transistor Design Using Metallic Shield Embeded Shallow Trench Isolation (MSE-STI) for Gbit Generation DRAM's `` IEEE Transactions on electron devices '', June 1999, VOL 46, No.6 , P.1212-1217

  An object of the present invention is to provide a semiconductor memory device with reduced power consumption.

  A semiconductor memory device according to one embodiment of the present invention includes a first mode in which operations including data reading, data writing, and refresh are performed, and a second mode in which refresh is autonomously repeated without data reading and data writing. (1) a semiconductor substrate, and (2) formed on the surface of the semiconductor substrate, defining an element region, having an insulating film on the surface, and including a conductor therein. An element isolation region; (3) a plurality of memory cells formed in the element region, each including a capacitor and a MOS transistor; and (4) applying a first potential to the conductor in the first mode. And a potential generating circuit for applying a second potential higher than the first potential in the second mode.

  According to the present invention, a semiconductor memory device with reduced power consumption can be provided.

  Embodiments of the present invention will be described below with reference to the drawings. In the following description, components having substantially the same function and configuration are denoted by the same reference numerals, and redundant description will be given only when necessary.

(First embodiment)
A first embodiment of the present invention will be described with reference to FIGS. FIG. 1 is a functional block diagram showing the configuration of the main part of the semiconductor device according to the first embodiment. As shown in FIG. 1, a semiconductor memory device (DRAM) 1, a memory cell array 2, a control circuit 3, a potential generation circuit 4, and a potential generation circuit control circuit 5 are included.

  The memory cell array 2 includes a plurality of DRAM memory cells 6 arranged in a matrix. Each memory cell 6 includes one cell capacitor 14 and one cell transistor 16. One end of the cell capacitor 14 is connected to one end of the cell transistor 16, and a plate potential Vpl is applied to the other end. The other end of the cell transistor 14 is connected to the bit line 17 and the gate is connected to the word line 15.

  The memory cells 6 are electrically isolated from each other by an element isolation region (not shown) having an STI (shallow trench isolation) structure. As will be described later in detail, the element isolation region includes an insulating film and a shield conductor formed inside the insulating film. The memory cell array 2 is connected to the control circuit 3.

  The control circuit 3 includes, for example, a row decoder, a column decoder, a sense amplifier, and the like. The control circuit 3 writes data to the memory cell 6 specified by an address signal supplied from the outside, for example, or receives data from the memory cell 6. Control to read. In addition, refreshing is performed on each memory cell 6 in order to prevent data from being lost due to loss of charge from the cell capacitor over time. The refresh interval is of such a length that data is not lost due to loss of charge due to junction leakage and cell transistor leakage in accordance with known techniques.

  Semiconductor memory device 1 has a normal operation mode and a self-refresh mode. In the normal operation mode, the control circuit 3 performs data writing, reading, refreshing, and the like. In addition, the semiconductor memory device 1 shifts to the self-refresh mode in response to, for example, a transfer command supplied from the outside. Further, the self-refresh mode is shifted to the normal operation mode by an exit command supplied from the outside. In the self-refresh mode, the control circuit 3 does not write or read data, but simply refreshes the memory cell 6 at an appropriate interval. The control circuit 3 is configured to perform refreshing at different intervals in the normal operation mode and the self-refresh mode.

  According to a known technique, the memory cell 6 can be a pseudo SRAM memory cell using the cell capacitor 14 and the cell transistor 16. The refresh is autonomously repeated even in the standby mode of the pseudo SRAM. Hereinafter, the term “refresh mode” includes a standby mode when the memory cell 6 is used as a pseudo SRAM. That is, all the embodiments of the present invention are not limited to the form of a memory, but are applied to all semiconductor memory devices having memory cells using capacitors and transistors connected in series.

  As will be described later, the potential generation circuit 4 is connected to a shield conductor in the element isolation region, and applies a predetermined potential to the shield conductor. The potential generation circuit 4 is connected to the potential generation circuit control circuit 5 and generates a potential according to the control of the potential generation circuit control circuit 5. The potential generation circuit control circuit 5 is controlled by the control circuit 3. The potential generation circuit control circuit 5 may be integrated with the control circuit 3.

  Next, the structure of the semiconductor device according to the first embodiment will be described with reference to FIGS. FIG. 2 is a plan view showing the structure of the main part of the semiconductor memory device according to the first embodiment. FIG. 3 is a cross-sectional view showing a structure taken along line III-III in FIG. 4 is a cross-sectional view showing a structure taken along line IV-IV in FIG.

  As shown in FIG. 2, the surface of the semiconductor substrate 11 made of, for example, silicon is partitioned into a plurality of active regions 13 by element isolation regions 12. The element isolation region 12 includes an insulating film 31 formed on the surface and a shield conductor 32 embedded therein. The insulating film 31 can be composed of a laminated film of a silicon oxide film and a silicon nitride film, for example. The active region 13 is electrically isolated from each other by being surrounded by the element isolation region 12. The active region 13 has, for example, a rectangular shape extending in the left-right direction in FIG. Two adjacent active regions 13 in the odd (even) rows in the vertical direction in FIG. 2 face each other at a position corresponding to the center in the left-right direction of the active regions 13 in the even (odd) rows.

  Cell capacitors 14 are provided at both ends of each active region 13 in the left-right direction. Accordingly, the capacitors 14 on the same side (left or right) of the active regions 13 in the even-numbered rows are located on the same straight line extending in the vertical direction. Similarly, each capacitor 14 on the same side of the active region 13 in the odd-numbered rows is located on the same straight line.

  The gate electrode 15 passes above each capacitor 14 on the same side (left or right) of the active regions 13 in even rows in the height direction. Similarly, the gate electrode 15 passes above the capacitors 14 on the same side (left or right) of the active regions 13 in the even-numbered rows in the height direction. Therefore, the four gate electrodes 15 extend over one active region 13.

  A cell transistor 16 is formed at each of two intersections formed by the active region 13 and the gate electrode 15 except for both ends (regions where capacitors are formed) of the active region 13. One cell transistor 16 and one cell capacitor 14 adjacent thereto constitute one memory cell 6.

  As shown in FIGS. 3 and 4, a p-well 21 is formed on the surface of the substrate 11. The p well 21 is set to a predetermined potential using a contact (not shown).

The cell capacitor 14 includes a trench 22, a plate diffusion layer 23, a capacitor insulating film 24, a collar oxide film 25, and a storage node 26. The trench 22 is formed on the surface of the substrate 11. The plate diffusion layer 23 is formed around the lower portion of the trench 22 and contains impurities. The capacitor insulating film 24 is formed on the lower inner surface of the trench 22. The collar oxide film 25 is formed on the upper inner surface of the trench 22. The upper end of the color oxide film 25 is located at a position lower than the upper end of the trench 22, so that the trench 22 is in contact with the p-well 21 at the top. An n ⁺ -type storage node diffusion layer 27 is provided at the boundary between trench 22 and p well 21 in p well 21 along the boundary. The storage node 26 is made of, for example, conductive polysilicon, and fills the trench 22 via the capacitor insulating film 24 and the collar oxide film 25.

  An element isolation region 12 is provided on the surface of the substrate 11 between the trenches 22. The element isolation region 12 protrudes in the planar direction at the upper portion of the trench 22, and this protruding portion covers the upper surface of each trench 22. A shield conductor 32 is embedded in the element isolation region 12. The shield conductor 32 is made of, for example, polycrystalline silicon into which an n-type impurity is introduced, and has a function as a shield against an electric field. The shield conductor 32 has a shape along the surface shape of the element isolation region 12 and embeds the inside of the element isolation region 12 excluding the surface.

  On the element isolation region 12, more specifically, on the upper surface of the shield conductor 32, an on-conductor insulating film 33 made of, for example, silicon oxide is formed.

  A cell transistor 16 is provided on the substrate 11 on the opposite side of the trench 22 from another adjacent trench 22. The cell transistor 16 is made of, for example, an n-type MOSFET (metal oxide semiconductor field effect transistor), and includes a gate insulating film 41 provided on the substrate 11, a gate electrode (word line) 15 provided on the gate insulating film 41, Source / drain diffusion layers 43 and 44 are included. Source / drain diffusion layer 44 is connected to storage node diffusion layer 27. Impurities are introduced into the channel region of the cell transistor 16, and the threshold value of the cell transistor 16 is set to a desired value by appropriately setting this concentration.

  The entire surface on the substrate 11 is covered with an interlayer insulating film 51. A bit line 17 is provided in the interlayer insulating film 51. The bit line 17 is connected to the source / drain diffusion layer 43 by a contact plug 52.

  The shield conductor 32 is electrically connected to the potential generation circuit 4 at the end of the memory cell array 2. The shield conductor 32 is set to the same potential throughout the memory cell array 2 by the potential generation circuit 4.

Next, details of the potential at which the shield conductor 32 is set will be described with reference to FIG. FIG. 5 is a timing chart of the potential applied to the shield conductor 32 in the first embodiment. The potential read from the memory cell 6 holding “0” data and “1” data to the bit line 17 is required for the characteristics of the memory cell 6 (for example, the capacitance of the capacitor), the characteristics of the sense amplifier, and the memory cell 6. Is determined according to various factors such as access speed. In the following description, for example, it is assumed that the potential (L bell) read to the bit line for holding “0” data is 0 V, and “1” data (H level) is 1.4 V. Hereinafter, this 1.4V is referred to as V _BLH .

As shown in FIG. 5, in the normal operation mode (to time T1), the shield conductor 32 is set to a predetermined first potential V _1. The first potential V ₁ is 0 V or less, for example, and is determined in consideration of the following factors.

At the time of reading and writing, depending on the position of the memory cell 6 to be accessed to be read or written and the data held by the memory cell 6 to be accessed, the bit line 17 has a low potential (L level potential (L level potential ( For example, it may be held at 0V)). As a result, in addition to the leakage current at the pn junction between the storage node 26 and the p-well 21, the active region (for example, the side surface of the element isolation region 12 on the color oxide film 25) is generated by the electric field generated by the charge held by the adjacent memory cell 6. ) Induces a leakage current through the cell transistor 16. On the other hand, the leakage current through the cell transistor 16 is suppressed by maintaining the potential of the shield conductor 32 at the first potential V ₁ . Therefore, the first potential V ₁ is set to a value that can achieve this purpose. The first potential V ₁ is, for example, 0 V as will be described later.

In addition, if a technique for applying an electric potential to the shield conductor 32 to eliminate the influence of the electric field is used,
Since the influence of the electric field due to the data of the adjacent memory cell with respect to the cell transistor 16 can be eliminated, a concentration capable of achieving a desired threshold voltage can be used as the impurity concentration of the channel portion of the cell transistor 16.

The shield conductor 32 is held at the first potential V ₁ over the period of the normal operation mode without depending on writing, reading, and refreshing.

On the other hand, at the same time as the semiconductor memory device shifts to the refresh mode at time T2, the shield conductor 32 is set to the second potential V ₂ different from the first potential V ₁ . The second potential V ₂ is maintained until the end of the refresh mode. Simultaneously with the transition to the normal operation mode, the shield conductor 32 is set to the first potential V ₁ again. The second potential V ₂ is higher than the first potential V ₁ and is selected in consideration of the following factors, and is 0.4 V, for example, as will be described later.

In the self-refresh mode, the bit line 17 is not activated except for the self-refresh operation. For this reason, the potential of the bit line 17 and thus the potential of the source / drain diffusion layer 43 is the precharge voltage, that is, _½ × V _BLH (= 0.7 V) in most of the time between refreshes. Therefore, the potential difference between the potential V _BL of the bit line 17 and the potential V _cell of the storage node 26 is 0.7 V (FIG. 6), and the potential of the bit line 17 that may be held for a long time in the normal operation mode. The potential is smaller than that in the case of 0V (FIG. 7). Further, the potential of the gate electrode 15 is held at 0 V except when the corresponding memory cell is refreshed, and is turned off at a negative voltage relative to 0.7 V of the source voltage (bit line contact portion diffusion layer 43). It will be. Therefore, it is difficult for the charge in the cell capacitor 14 to leak through the cell transistor 16. Therefore, the second potential V ₂ (the potential of the shield conductor 32 in the self-refresh mode) can be set higher than the first potential V ₁ (the potential of the shield conductor 32 in the normal operation mode). Even if the potential is set in this way, the shield conductor 32 does not significantly affect the effect of suppressing the electric field from the adjacent memory cell.

On the other hand, if the second potential is too high, the state becomes the same as when the adjacent memory cell holds “1” data when the conductor 31 is not used, and a channel is induced on the side surface of the active region 13 of the memory cell 6. Is done. That is, the cell transistor 16 leaks. Therefore, the second potential V ₂ is set so that a channel is not formed at the boundary between the surface of the substrate 11 and the element isolation region 12 when the bit potential 17 is higher than the first potential V ₁ and the bit line 17 is a precharge potential. Is done. This value is determined in consideration of design rules such as the shape of the element isolation region 12, the thickness of the insulating film 31, the concentration of the p-well 21, and the like. A method for setting the second potential V ₂ will be described in detail later.

By setting shield conductor 32 to an appropriate second potential V ₂ , depletion at the pn junction between source / drain diffusion layer 44 (storage node diffusion layer 27) and p well 31 is achieved in the refresh mode. The width of the layer is increased. As a result, the electric field strength in the depletion layer is lowered, and the pn junction leakage current can be made lower than that in the normal operation mode. Therefore, the data retention time in the self-refresh mode becomes long. Therefore, it sets the potential of the shield conductor 32 to the second potential V _2, the control circuit 3, the refresh interval of the self-refresh mode is longer than the refresh interval for normal operation mode.

Next, a more detailed setting method of the second potential V ₂ will be described with reference to FIGS. As described above, the leakage of the transistor becomes large when the bit line 17 is at a low level. Therefore, first, the relationship between the potential of the shield conductor 32 and the leak of the cell transistor 16 when the bit line 17 is maintained at the low level throughout the refreshing in the normal operation mode is obtained.

  FIG. 8 shows the relationship between the shield conductor potential and the current flowing through the storage node. The solid line shows the relationship under the worst condition in which the leakage current in the cell transistor 16 is maximized. This relationship is, for example, the potential when the “1” data is held in the storage node 26 in the test element group (TEG) of the cell transistor 16 embedded in the semiconductor device or in a dicing line for dividing the semiconductor device. In this example, 1.4 V) is applied, a low level (0 V in this example) is applied to the bit line 17, a low level (0 V in this example) is applied to the word line (gate electrode 15), and a p-well 21 is obtained by measuring the current flowing through the storage node 26 while changing the potential of the shield conductor 32 with a back gate voltage (-0.5 V in this example) applied.

  As shown in FIG. 8, the current flowing through the storage node depends on the shield conductor potential.

  Next, using this relationship, the relationship between the shield conductor potential and the storage node current when the bit line 17 is at the low level in the self-refresh mode is obtained. The time during which the bit line 17 is at the low level in the self-refresh mode depends on the refresh interval in the self-refresh mode. Here, although the refresh interval depends on many factors such as the capacity of the cell capacitor, it is assumed that the refresh interval is set to a feasible value of 320 ms.

  For example, it is assumed that the number of word lines connected to one column (configured by two bit lines) is 256, and the time for activating the bit line 17 in the self-refresh mode is 30 ns.

  Under the above conditions, the maximum time that the bit line 17 is kept at the low level without being refreshed during the self-refresh mode is 7.7 μs.

  On the other hand, the maximum time during which the bit line 17 is held at the low level during the normal operation mode is substantially equal to the refresh interval. Here, it is assumed that the refresh interval is set to 96 ms, for example, in consideration of various factors.

From the above, the time during which the bit line 17 is at the low level in the self-refresh mode is about 8 × 10 ⁻⁵ times the maximum time during which the bit line 17 is at the low level in the normal operation mode. This value is multiplied by the previously obtained straight line indicating the relationship between the current flowing through the storage node and the shield conductor potential in the normal operation mode. As a result, as shown by the broken line in FIG. 8, a straight line indicating the relationship between the average storage node current and the shield conductor potential in the self-refresh mode is obtained.

On the other hand, the storage node current I _off for preventing the “1” data from changing to “0” data until the next refresh is approximately calculated as follows.

I _off = C _s × (V ₁ −V _bp ) / t _ref (1)
However,
C _s : storage node capacitance V ₁ : “1” data write voltage V _bp : potential t _ref at the time of precharging the bit line: refresh interval time.

As a result of substituting each value into Expression (1), a specific value I _{off2 of the} current required to hold “1” data is obtained in the refresh mode (for example, 6.6 × 10 ⁻¹⁴ A). Shield conductor potential corresponding to the intersection of the dashed this value and FIG. 8 corresponds to the potential V _2. The potential V ₂ is, for example, 0.4V.

The shield conductor potential for preventing the “1” data from changing to “0” data in the normal operation mode is also obtained by the same method. For example, by substituting each value into the equation (1), I _off1 is obtained (for example, 2 × 10 ⁻¹³ A), and the shield conductor potential corresponding to the intersection of this value and the solid line in FIG. ₁ . The potential V ₁ is, for example, 0V.

Furthermore, when a chip that actually operates is already obtained, the potential V ₂ can be optimized in consideration of variations in characteristics of each bit (memory cell). This chip is set to a specific value with a refresh interval (for example, 96 ms in the normal operation mode and 320 ms in the self-refresh mode). For this chip, as shown in FIG. 9, the number of defective bits when the shield conductor potential in the self-refresh mode is changed is obtained (illustrated by a broken line).

As shown in FIG. 9, in the range below a certain value (V _2j ), the lower the shield conductor potential, the more defective bits due to pn junction leakage, and the shield conductor potential in a range above a certain value (V _2t ). The higher Vsh, the more defective bits due to cell transistor leakage. Therefore, a value that minimizes the number of defective bits between the value V _2j and the value V _2t is applied to the potential V ₂ .

The potential V ₁ in the normal operation mode can be obtained by the same method. That is, in the test using the timing when the bit line becomes low level, the corresponding refresh time (for example, 96 ms) and the data pattern, the value V _{1j at} which the increase of defective bits due to the pn junction leakage starts, A value that minimizes the number of defective bits is applied to the potential V ₁ between the value V _{1t at} which an increase in defective bits due to transistor leakage starts. The remaining defective bits can be replaced with spare cells using a redundancy circuit.

As described above, according to the first embodiment, the shield conductor 32 in the element isolation region 12 is set to the first potential V ₁ in the normal operation mode and the second potential higher than the first potential V ₁ in the refresh mode. The potential is V ₂ . Therefore, in the normal operation mode, the threshold fluctuation of the cell transistor can be avoided by the adjacent memory cell, and in the self refresh mode, the pn junction leakage current that can be caused by the shield conductor 32 can be suppressed. For this reason, the current consumption of the semiconductor memory device can be reduced.

(Second Embodiment)
In the first embodiment, the refresh interval during the self-refresh mode and the potential of the shield conductor 32 are uniform. On the other hand, in the second embodiment, these values differ depending on the time point in the self-refresh mode.

  A semiconductor memory device according to the second embodiment will be described with reference to FIGS. FIG. 10 is a functional block diagram showing the configuration of the main part of the semiconductor memory device according to the second embodiment. 11 and 12 are timing charts of potentials applied to the shield conductor 32 in the second embodiment.

  As for FIG. 10, a control circuit 61 is provided in place of the control circuit 3 of the first embodiment. The control circuit 61 is configured to perform refreshing at two or more different intervals in the self-refresh mode. Further, the control circuit 61 has a timer 62 for measuring a predetermined time. Except for these points, the control circuit 61 is the same as the control circuit 3 of the first embodiment.

  In the self-refresh mode, the control circuit 61 can perform the self-refresh interval at the first interval or at the second interval. The first interval is an interval used immediately after the transition to the self-refresh mode, and is at least equal to or longer than the refresh interval in the normal operation mode, for example, 128 ms. The second interval is a time used after a predetermined set time has elapsed after the transition to the self-refresh, for example, 320 ms.

After shifting to the self-refresh mode, the potential of the shield conductor 32 may be in a transition state from the first potential V ₁ to the second potential V ₂ . Therefore, as shown in FIG. 11, from time T1, until time T3 when the shield conductor potential reaches the second potential V _2, the refresh is performed in the first interval. After time T3, refresh is performed at the second interval.

The transition to the self-refresh mode and the exit from the self-refresh mode depend on an external command, and the duration of the self-refresh mode may be short or long. Nevertheless, the current for control required to set the second potential V _{2 to} be applied can be consumed. For this reason, when the duration of the self-refresh mode is very short, even if the shield conductor potential is set to the second potential V ₂ , the effect of suppressing a large current consumption cannot be expected, but rather a wasteful current consumption occurs. There is a possibility. Therefore, as shown in FIG. 12, on the condition that the self-refresh mode has continued for a predetermined waiting time, that is, has reached time T4 after elapse of the waiting time from time T1, the shield conductor potential is The second potential V ₂ is set. As a specific example of the standby time, for example, 96 ms can be set.

The timing of setting the shield conductor potential to the second potential V ₂ is controlled by the second potential generating circuit control circuit 5 after the control circuit 61 uses the timer 62 and a predetermined time elapses after shifting to the self-refresh mode. In addition, it can be executed by transmitting a signal for setting to the second potential V ₂ . Alternatively, a method may be used in which a timer is provided in the potential generation circuit control circuit 5 so that an instruction to change the potential is sent to the potential generation circuit 4 after a predetermined time has elapsed after reception of a signal notifying the transition from the control circuit 3 to the self-refresh mode. Good.

  The parts other than the contents described here are the same as those in the first embodiment.

According to the semiconductor memory device of the second embodiment, as in the first embodiment, the shield conductor 32 in the element isolation region 12 is set to the first potential V ₁ in the normal operation mode, and the first potential in the refresh mode. A higher second potential V ₂ is set. For this reason, the same effect as the first embodiment can be obtained.

  In addition, according to the second embodiment, the refresh interval in the self-refresh mode or (and) the change timing of the shield conductor potential is appropriately set in consideration of the operation of the semiconductor memory device. For this reason, it is prevented that the current required for the change of the shield conductor potential is consumed inefficiently.

  In addition, 1st, 2nd embodiment was demonstrated using the trench capacitor as a cell capacitor. However, even in the case of a stacked capacitor, the same problem as in the case of a trench capacitor as described above occurs, and this embodiment can be applied to a stacked capacitor in order to solve this problem.

  In addition, in the category of the idea of the present invention, those skilled in the art can conceive of various changes and modifications, and it is understood that these changes and modifications also belong to the scope of the present invention. .

1 is a functional block diagram of main parts of a semiconductor device according to a first embodiment. 1 is a plan view of a structure of a main part of a semiconductor memory device according to a first embodiment. Sectional drawing of the structure along the III-III line | wire of FIG. Sectional drawing of the structure along the IV-IV line of FIG. The timing chart of the potential applied to the shield conductor in the first embodiment. The figure which shows one state of the electric potential at the time of self-refresh mode. The figure which shows one state of the electric potential at the time of normal operation mode. The figure which shows the relationship between a shield conductor electric potential and a storage node electric current. The figure which shows the relationship between a shield conductor electric potential and the number of defective bits. It is a block diagram of the principal part of the semiconductor memory device which concerns on 2nd Embodiment. The timing chart of the electric potential applied to a shield conductor in 2nd Embodiment. The timing chart of the electric potential applied to a shield conductor in 2nd Embodiment.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 ... Semiconductor memory device, 2 ... Memory cell array, 3 ... Control circuit, 4 ... Potential generation circuit, 5 ... Potential generation circuit control circuit, 6 ... Memory cell, 11 ... Semiconductor substrate, 12 ... Element isolation region, 13 ... Active region , 14 ... cell capacitor, 15 ... gate electrode, 16 ... cell transistor, 17 ... bit line, 21 ... p-well, 22 ... trench, 23 ... plate diffusion layer, 24 ... capacitor insulating film, 25 ... color oxide film, 26 ... Storage node, 27 ... Storage node diffusion layer, 31 ... Insulating film, 32 ... Shield conductor, 33 ... Insulating film on conductor, 41 ... Gate insulating film, 42 ... Gate electrode, 43, 44 ... Source / drain diffusion layer, 51: Interlayer insulating film, 52: Contact plug.

Claims (5)

A semiconductor memory device having a first mode in which operations including data reading and data writing and refresh are performed, and a second mode in which refresh is autonomously repeated without data reading and data writing,
A semiconductor substrate;
An element isolation region formed on the surface of the semiconductor substrate, defining an element region, having an insulating film on the surface, and including a conductor inside;
A plurality of memory cells formed in the element region, each including a capacitor and a MOS transistor;
A potential generating circuit for applying a first potential to the conductor in the first mode and applying a second potential higher than the first potential in the second mode;
A semiconductor memory device comprising: In the first mode, refresh is performed every first time,
Refreshing is performed every second time longer than the first time in the second mode.
The semiconductor memory device according to claim 1.   2. The semiconductor memory device according to claim 1, wherein the potential generation circuit starts applying the second potential simultaneously with the transition of the semiconductor memory device to the second mode.   2. The semiconductor memory device according to claim 1, wherein the potential generation circuit starts applying the second potential after a lapse of a first time after the semiconductor memory device shifts to the second mode. In the first mode, refresh is performed every first time,
Refreshing is performed every second time longer than the first time between the transition to the second mode and the first time,
Refreshing is performed every third time longer than the second time from the first time to the end of the second mode.
The semiconductor memory device according to claim 1.

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