JP2000059033A - Multilayer circuit board and manufacture thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To form microscopic via holes with a CO2 laser having good dimensional accuracy. SOLUTION: In a via hole formation process, first the surface of an insulating resin layer 27 is roughened, and after an electroless Cu plated film 31 is formed on the layer 27, a photosensitive resin layer 33 is formed on the surface of the film 31. Then, exposure and developing are performed on the layer 33, so that only the parts, which are formed with via holes of this layer 33 are left to form plated resists 33a for via hole formation. After this, after an electrolytic Cu plated film 32 having holes 34 for via hole formation is formed on the surface of the film 31 using the plated resists 33a, the plated resists 33a are removed. Then, after the holes 34 for via hole formation are formed in the film 31 through etching using the film 32 as an etching resist, the via holes are formed in the insulating resin layer 27 with CO2 laser using the film 32 as a mask.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to relates to a multilayer circuit board and a manufacturing method thereof to form a via hole in a CO ₂ laser.

[0002]

2. Description of the Related Art With the recent increase in performance and miniaturization of semiconductor elements, increasing the wiring density of a circuit board on which semiconductor elements are mounted has become an important technical problem. At present, one of the high-density circuit boards put into practical use is a multilayer circuit board by a build-up method. A typical manufacturing method of this build-up multilayer circuit board is to form an epoxy-based photosensitive insulating resin layer on both sides or one side of a glass epoxy substrate serving as a core substrate, and to form a via hole in the photosensitive insulating resin layer by a photo-etching method. Is formed thereon, and an inner conductor pattern and a via conductor are formed thereon by Cu plating. Thereafter, the same steps are sequentially repeated to form a multilayer.

[0003]

With the recent miniaturization and weight reduction of electronic devices, circuit boards have become smaller and lighter.
Higher densities have been demanded, and accordingly, it has become necessary to reduce the diameter of via holes. However, in the method of forming a via hole by the photo etching method described above,
There is a limit on the diameter of via holes.

[0004] For this reason, the formation of minute via holes has been performed by a laser method. Laser used is a CO ₂ laser, there are an excimer laser or the like, CO ₂ laser, as compared to the excimer laser, the device is simple, because the fast processing speed, a CO ₂ laser from the viewpoint of production costs Use is more advantageous.

When a via hole is formed by a CO ₂ laser, an insulating resin layer 11 is formed on an insulating substrate (not shown) as shown in FIG. Cu plating film 12 by Cu plating, electrolytic Cu plating
To form Next, a dry film 13 (photosensitive resin film) is laminated on the surface of the Cu plating film 12,
This is exposed and developed to form a hole 14 for forming a via hole.
To form Thereafter, using the dry film 13 as an etching resist,
Etching is performed with an etchant such as Cl ₃ to form holes 15 for forming via holes in the Cu plating film 12.

Next, after the dry film 13 is peeled off,
Using the Cu plating film 12 as a mask for a laser, a via hole 16 is formed in the insulating resin layer 11 with a CO ₂ laser.
To form Thereafter, the Cu plating film 12 is peeled off,
Via conductors (not shown) are formed in the via holes 16 by Cu plating, and an inner conductor pattern (not shown) is formed on the insulating resin layer 11. Thereafter, a next insulating resin layer (not shown) is formed on the inner conductor pattern, and thereafter, the above-described steps are sequentially repeated to form a build-up multilayer substrate.

However, according to this method, a hole 1 for forming a via hole is formed in a Cu plating film 12 serving as a laser mask.
5 is formed by over-etching
The hole diameter of the via hole forming hole 15 of the u-plated film 12 is etched larger than the hole diameter of the hole 14 of the dry film 13. Therefore, when the via hole 16 is formed in the insulating resin layer 11 by the CO ₂ laser, not only the hole diameter of the via hole 16 becomes larger than the design value (the hole diameter of the hole 14 of the dry film 13), but also the variation in the hole diameter of the via hole 16 And the dimensional accuracy of the via hole 16 deteriorates. In general, as the wiring density increases, the dimensional accuracy of the hole diameter of the via hole 16 is required.
This is a factor that hinders an increase in wiring density.

SUMMARY OF THE INVENTION The present invention has been made in view of such circumstances, and accordingly, it is an object of the present invention to provide a multilayer circuit board capable of forming minute via holes with high dimensional accuracy using a CO ₂ laser and a method of manufacturing the same. Is to do.

[0009]

In order to achieve the above object, a method of manufacturing a multilayer circuit board according to the present invention comprises: (1) a step of forming a conductive pattern on an insulating substrate; and (2) a step of forming a conductive pattern on the insulating pattern. (3) a step of roughening the surface of the insulating resin layer, and (4) a step of forming an electroless Cu plating film on the surface of the insulating resin layer.
(5) A photosensitive resin layer is formed on the electroless Cu plating film, and the photosensitive resin layer is exposed to light so as to leave only a portion for forming a via hole, and developed to form a plating resist for forming a via hole. And (6) using the plating resist, on the electroless Cu plating film,
Forming an electrolytic Cu plating film having a hole for forming a via hole; (7) removing the plating resist; and (8) using the electrolytic Cu plating film as an etching resist to form the electroless Cu plating film. Forming a hole for forming a via hole by etching, (9)
Forming a via hole in the insulating resin layer with a CO ₂ laser using the electrolytic Cu plating film as a laser mask; and (10) the electrolytic Cu plating film and the electroless Cu plating on the insulating resin layer. And (11) forming a via conductor in the via hole and forming a conductor pattern on the insulating resin layer.

In this method, since an electrolytic Cu plating film serving as a laser mask is formed using a plating resist for forming a via hole, it is necessary to form a fine hole for forming a via hole in the electrolytic Cu plating film by etching. As a result, the problem caused by the conventional over-etching is solved, and a fine via hole forming hole can be formed in the electrolytic Cu plating film with high dimensional accuracy. Therefore, this electrolytic Cu
Using the plating film as a laser mask, CO ₂
If a via hole is formed in the insulating resin layer with a laser, a minute via hole can be formed with high dimensional accuracy.

In this case, the steps from the formation of the insulating resin layer to the formation of the via conductor and the conductor pattern may be repeated a predetermined number of times to form a multilayer. This allows
A high-density, compact build-up multilayer circuit board can be formed.

In addition, the positional relationship between the via hole and the conductor pattern under the via hole is set so that the entire bottom surface of the via hole is covered with the conductor pattern under the via hole, and the formation of the via hole in the insulating resin layer by the CO ₂ laser is performed. It may be performed until the lower conductive pattern is exposed. In this way, when forming a via hole in the insulating resin layer with a CO ₂ laser, when the depth of the via hole reaches the lower conductor pattern, the laser light is reflected by the conductor pattern, and further, the laser light is Will not invade.
This makes it possible to reliably perform laser processing until the entire bottom surface of the via hole reaches the conductor pattern, while preventing the bottom portion of the via hole from unnecessarily penetrating into the lower layer, thereby forming a via hole having a good shape. Thus, conduction between the via conductor and the conductor pattern can be ensured.

[0013]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment in which the present invention is applied to a build-up multilayer circuit board 21 used for a flip-chip type build-up type BGA (Ball Grid Array) package will be described below with reference to FIGS. explain.

First, the structure of the build-up multilayer circuit board 21 will be described with reference to FIG. The insulating substrate 22 serving as a core substrate is formed of, for example, a resin substrate of glass epoxy, polyimide or the like, and a through hole 23 is formed at a predetermined position. The conductive pattern 24 and the through-hole conductor 25 are formed on the upper and lower surfaces of the insulating substrate 22 and the inner peripheral surface of the through-hole 23 by electroless Cu plating and electrolytic Cu plating so as to be electrically connected to each other. The cavity is filled with a filling resin 26 such as epoxy.

An insulating resin layer 27 is formed on the conductor pattern 24 on both sides of the insulating substrate 22, and a via hole 28 is formed at a predetermined position of the insulating resin layer 27 by a CO ₂ laser. A conductor pattern 29 and a via conductor 30 are formed on the surface of the insulating resin layer 27 and the via hole 28 by electroless Cu plating and electrolytic Cu plating, and the conductor pattern 24 on the insulating substrate 22 and the conductor pattern on the insulating resin layer 27 are formed. 2
9 are electrically connected via a via conductor 30.
The via hole 28 and the conductor pattern 24 (or 2
The positional relationship with 9) is set such that the entire bottom surface of the via hole 28 is covered with the conductor pattern 24 (or 29) under the via hole 28. These insulating resin layers 27, conductor patterns 29, and via conductors 30 are formed in a required number of layers. Although only two layers are shown in FIG. 1, the number of laminated insulating resin layers 27 may be one or three or more.
Further, the insulating resin layer 27 may be formed only on one surface of the insulating substrate 22.

Although not shown, the lowermost via conductor on the lower surface side of the build-up multilayer circuit board 21 has Ni / Au
BGA bumps (solder balls) are formed via plating, and flip-chip bonding pads are formed on the uppermost via conductor on the upper surface side of the build-up multilayer circuit board 21.

Next, a method of manufacturing the build-up multilayer circuit board 21 having the above configuration will be described. First, the insulating substrate 2
2 is formed on the upper and lower surfaces of the insulating substrate 22 and the inner peripheral surface of the through hole 23 by electroless Cu plating using electroless Cu plating as a base, and a photomask is formed on the surface with a photosensitive resin. Then, the conductor pattern 24 and the through-hole conductor 25 are formed by a photoetching method. After that, the cavity of the through-hole conductor 25 is filled with a filling resin 26 such as epoxy to flatten it. next,
A liquid insulating resin such as an epoxy resin is applied to the surface of the insulating substrate 22 on which the conductor pattern 24 is formed by a spin coater or the like, and is heated and cured at 175 ° C. for 2 hours to form an insulating resin layer 27. I do.

Thereafter, a via hole 28 is formed in the insulating resin layer 27.
Is formed by the steps shown in FIGS. First, the surface of the insulating resin layer 27 [see FIG. 2 (1)] is roughened by treating it with potassium manganese oxide, chromic acid or the like [see FIG. 2 (2)]. Thereafter, the roughened surface of the insulating resin layer 27 is washed with water and neutralized.
Plating is performed to form an electroless Cu plating film 31 having a thickness of, for example, 1 to 3 μm (see FIG. 2C).

Next, a dry film having a film thickness (for example, 10 to 20 μm) having a thickness equal to or greater than the thickness of the electrolytic Cu plating film 32 to be applied in a later step is thermocompression-bonded to the surface of the electroless Cu plating film 31, Forming a resin layer 33 [FIG. 2 (4)]
reference]. After that, for example, 35 mJ so that only a portion of the photosensitive resin layer 33 where the via hole 28 is formed remains.
And then developed by showering with, for example, a 1% aqueous solution of sodium carbonate to remove the photosensitive resin layer 33 in portions other than the via-hole forming portion, thereby forming a plating resist 3 for forming a via-hole.
3a is formed [see FIG. 2 (5)].

Thereafter, using the plating resist 33a,
Electroless Cu plating is applied to the surface of the electroless Cu plating film 31 and has a hole 34 for forming a via hole.
An electrolytic Cu plating film 32 having a thickness of μm is formed [FIG.
(6)]. Thereafter, the plating resist 33a is peeled off with acetone or a 3% NaOH aqueous solution or the like [FIG.
(7)]. Next, using the electrolytic Cu plating film 32 as an etching resist, the electroless Cu plating film 31 is used.
Then, a hole 35 for forming a via hole is formed by etching [see FIG. 3 (8)].

Thereafter, a via hole 28 is formed at a predetermined position of the insulating resin layer 27 with a CO ₂ laser using the electrolytic Cu plating film 32 as a laser mask [FIG.
(9)]. The conditions of the CO ₂ laser to be used include a beam diameter of 250 μm and a laser output of 6 mJ, for example.
× 3 shot. The laser processing of the via hole 28 is performed until the underlying conductive pattern 24 is exposed.

In the present embodiment, the entire bottom surface of the via hole 28 is covered with the lower conductive pattern 24 in consideration of the fact that the CO ₂ laser does not pass through the Cu plating surface.
Accordingly, when the via hole 28 is formed in the insulating resin layer 33 by the CO ₂ laser, when the depth of the via hole 28 reaches the lower conductive pattern 24, the laser light is reflected by the conductive pattern 24, and the laser light is further emitted. It will not penetrate the lower layer. Thus, the laser processing is reliably performed until the entire bottom surface of the via hole 28 reaches the conductor pattern 24 while preventing the bottom of the via hole 28 from penetrating unnecessarily to the lower layer. Thereafter, the electrolytic Cu plating film 32 and the electroless Cu plating film 31, which are laser masks, are peeled off with an etching solution such as FeCl ₃ [see FIG. 3 (10)].

Next, a photosensitive resin layer (not shown) is formed by a dry film or the like on the surface of the insulating resin layer 27 in which the via hole 28 is formed, and this is exposed and developed to form a photosensitive resin layer. By removing the via conductor forming portion and the conductor pattern forming portion, a plating resist is formed. Thereafter, after performing electroless Cu plating and electrolytic Cu plating, the plating resist (photosensitive resin layer) is peeled off to form a via conductor 30 and a conductor pattern 29. After this,
When building up is repeated, the insulating resin layer 27 described above is used.
The steps from the formation of the via conductor 30 and the formation of the conductor pattern 29 are repeated until the required number of layers is obtained, thereby forming a multilayer, thereby forming the build-up multilayer circuit board 21.

After these steps are completed, if necessary, BGA bumps (solder balls) are formed on the lowermost via conductor on the lower surface side of the build-up multilayer circuit board 21 via Ni / Au plating. And build-up multilayer circuit board 2
1. A flip-chip bonding pad is formed on the uppermost via conductor on the upper surface side.

The present inventor compared and evaluated the minimum value of the hole diameter of the via hole and the variation of the hole diameter of the via hole laser processing method of the present embodiment described above and the conventional via hole laser processing method described above. A test was conducted. As a result, in the via hole laser processing method of the present embodiment, the minimum value of the hole diameter of the via hole that can be formed was 25 μm, and the variation of the hole diameter was ± 3 μm.

In contrast, in the conventional via hole laser processing method, as shown in FIG. 4, a via hole forming hole 15 is formed in a Cu plating film 12 serving as a laser mask.
Is formed by etching, and the Cu plating film 12 is used as a mask for laser. In this method, the diameter of the hole 15 for forming a via hole in the Cu plating film 12 is reduced by over-etching using an etching resist (dry film 1).
Since the etching is larger than the hole diameter of the hole 14 of 3), the minimum value of the hole diameter of the via hole that can be formed is 30 μm.
m, the variation of the pore diameter was as large as ± 10 μm. From this test result, it was confirmed that the via hole laser processing method of the present embodiment can form a via hole having a very small hole diameter and a very small variation in the hole diameter.

That is, in this embodiment, since the electrolytic Cu plating film 32 serving as a laser mask is formed using the plating resist 33a for forming a via hole,
It is not necessary to form minute via hole forming holes 35 in the u-plated film 32 by etching, the problem of conventional over-etching is solved, and minute via hole forming holes 35 are formed in the electrolytic Cu plated film 32 with high dimensional accuracy. Can be formed. Therefore, this electrolytic Cu plating film 32
Is used as a laser mask, and a via hole 28 is formed in the insulating resin layer 27 with a CO ₂ laser, whereby a minute via hole 28 can be formed with high dimensional accuracy.
As a result, the density of the build-up multilayer circuit board 21 can be increased, and the demand for miniaturization and weight reduction can be satisfied.

Although the insulating substrate 22 as the core substrate is formed of a resin substrate in the present embodiment, a metal substrate may be used. In the case of a metal substrate, the substrate surface may be used after insulating processing.

In this embodiment, a flip-chip type build-up type BGA package has been described as a package type. However, the package type is not particularly limited. For example, a PGA (Pin Grid Array) package, an MCM substrate, etc. Can be applied to various circuit boards.

[0030]

As is apparent from the above description, according to the multilayer circuit board of the first aspect of the present invention, the positional relationship between the via hole and the conductor pattern under the via hole is determined by the entire bottom surface of the via hole. A via hole was formed in the insulating resin layer with a CO ₂ laser using an electrolytic Cu plating film formed using a plating resist for forming a via hole as a mask for a laser, while setting so as to be covered with a pattern. And improvement of the dimensional accuracy of the hole diameter and depth can be realized.

Further, according to the method for manufacturing a multilayer circuit board of the present invention, since the electrolytic Cu plating film serving as a laser mask is formed by using the plating resist for forming the via hole, the minute Cu is applied to the electrolytic Cu plating film. A hole for forming a via hole can be formed with high dimensional accuracy.
By forming a via hole in the insulating resin layer with a CO ₂ laser using the plating film as a laser mask, a minute via hole can be formed with high dimensional accuracy.

Further, in the third aspect, since two or more build-up layers are formed on the insulating substrate, it is possible to effectively cope with high density and miniaturization of the multilayer circuit board.

According to a fourth aspect of the present invention, the positional relationship between the via hole and the lower conductive pattern is set such that the entire bottom surface of the via hole is covered with the lower conductive pattern, and the via hole is formed by a CO ₂ laser. As a result, a via hole having a small diameter and a good shape with little dimensional variation can be formed.

[Brief description of the drawings]

FIG. 1 is a partially enlarged longitudinal sectional view showing a structure of a build-up multilayer circuit board according to an embodiment of the present invention.

FIG. 2 is a process diagram for explaining a CO ₂ laser processing method for a via hole in one embodiment (part 1);

FIG. 3 is a process diagram (part 2) for explaining a CO ₂ laser processing method for a via hole in one embodiment.

FIG. 4 is a process chart for explaining a conventional CO ₂ laser processing method for via holes.

[Explanation of symbols]

21: build-up multilayer circuit board, 22: insulating board, 2
3 through-hole, 24 conductor pattern, 25 through-hole conductor, 26 filling resin, 27 insulating resin layer, 2
Reference numeral 8: via hole, 29: conductor pattern, 30: via conductor, 31: electroless Cu plating film, 32: electrolytic Cu plating film, 33: photosensitive resin layer, 33a: plating resist, 34, 35: holes for forming via holes .

 ──────────────────────────────────────────────────続 き Continued on the front page F term (reference) 4E068 AA03 AF01 CF02 DA11 DB01 DB10 5E346 AA12 AA15 AA43 BB01 CC32 CC54 CC58 DD03 DD23 DD24 DD33 DD47 DD48 EE31 EE33 FF01 FF13 FF14 GG15 GG17 GG18 GG22 H26 H11

Claims (4)

[Claims] 1. A laser mask comprising: a conductive pattern formed on an insulating substrate; an insulating resin layer formed on the conductive pattern; and an electrolytic Cu plating film having holes for forming via holes. In a multilayer circuit board comprising a resin layer and a via hole formed by a CO ₂ laser, the electrolytic Cu plating film is formed using a plating resist for forming a via hole, and the entire bottom surface of the via hole is a conductive pattern under the same. A multilayer circuit board, characterized by being covered with: A step of forming a conductive pattern on the insulating substrate; a step of forming an insulating resin layer on the conductive pattern; a step of roughening the surface of the insulating resin layer; Forming an electroless Cu plating film, and forming a photosensitive resin layer on the electroless Cu plating film,
Exposing and developing a portion of the photosensitive resin layer where via holes are to be formed, and developing and forming a plating resist for forming a via hole; using the plating resist, the electroless Cu plating film Forming an electrolytic Cu plating film having a hole for forming a via hole; removing the plating resist; etching the electroless Cu plating film using the electrolytic Cu plating film as an etching resist; Forming a hole for forming; forming a via hole in the insulating resin layer with a CO ₂ laser using the electrolytic Cu plating film as a laser mask; and forming the electrolytic Cu plating on the insulating resin layer. Removing a film and the electroless Cu plating film; forming a via conductor in the via hole; Method of manufacturing a multilayer circuit board which comprises forming a conductive pattern on the resin layer. 3. The method for manufacturing a multilayer circuit board according to claim 2, wherein the steps from the formation of the insulating resin layer to the formation of the via conductor and the conductor pattern are repeated a predetermined number of times. Wherein said via hole and the positional relationship between the underlying conductor pattern, the entire bottom surface of the via hole is set to be covered by the layer conductor patterns thereof, the via hole of the insulating resin layer by the CO ₂ laser 4. The method for manufacturing a multilayer circuit board according to claim 2, wherein the forming is performed until the underlying conductive pattern is exposed.