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IT1250771B - Sintetizzatore di frequenza n-frazionale ad accumulatori multipli in combinazione latch. - Google Patents

Sintetizzatore di frequenza n-frazionale ad accumulatori multipli in combinazione latch.

Info

Publication number
IT1250771B
IT1250771B ITRM910653A ITRM910653A IT1250771B IT 1250771 B IT1250771 B IT 1250771B IT RM910653 A ITRM910653 A IT RM910653A IT RM910653 A ITRM910653 A IT RM910653A IT 1250771 B IT1250771 B IT 1250771B
Authority
IT
Italy
Prior art keywords
accumulators
accumulator
delay
latch
synthesizer
Prior art date
Application number
ITRM910653A
Other languages
English (en)
Inventor
Alexander W Hietala
Duane C Rabe
Original Assignee
Motorola Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Motorola Inc filed Critical Motorola Inc
Publication of ITRM910653A0 publication Critical patent/ITRM910653A0/it
Publication of ITRM910653A1 publication Critical patent/ITRM910653A1/it
Application granted granted Critical
Publication of IT1250771B publication Critical patent/IT1250771B/it

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03C—MODULATION
    • H03C3/00—Angle modulation
    • H03C3/02—Details
    • H03C3/09—Modifications of modulator for regulating the mean frequency
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
    • H03L7/18—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop
    • H03L7/197—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop a time difference being used for locking the loop, the counter counting between numbers which are variable in time or the frequency divider dividing by a factor variable in time, e.g. for obtaining fractional frequency division
    • H03L7/1974—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop a time difference being used for locking the loop, the counter counting between numbers which are variable in time or the frequency divider dividing by a factor variable in time, e.g. for obtaining fractional frequency division for fractional frequency division
    • H03L7/1976—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop a time difference being used for locking the loop, the counter counting between numbers which are variable in time or the frequency divider dividing by a factor variable in time, e.g. for obtaining fractional frequency division for fractional frequency division using a phase accumulator for controlling the counter or frequency divider

Landscapes

  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)
  • Supply Devices, Intensifiers, Converters, And Telemotors (AREA)
  • Paints Or Removers (AREA)
  • Transmitters (AREA)

Abstract

Oggetto dell'invenzione è un sintetizzatore N-frazionale con accumulatori multipli in latch da impiegare in ricetrasmettitori radio digitali. Il parametro divisore del circuito di divisione di frequenza (103) del sintetizzatore viene fatto variare con il tempo per mezzo della somma delle sequenze digitali di uscita di riporto degli accumulatori che comportano incrementi di frequenza uguali ad una frazione della frequenza di riferimento. Gli accumulatori (615, 617) sono combinati in latch in modo tale che a seguito del verificarsi di un impulso di cadenza o di clock, i dati vengano trasferiti attraverso ciascun accumulatore uno scatto di impulso di cadenza alla volta, in modo tale che il ritardo attraverso il sistema sia uguale a quello corrispondente soltanto ad un accumulatore. Le uscite di riporto degli accumulatori (615, 617) sono accoppiate attraverso circuiti di ritardo (645, 647, 649, 631, 633) uguali ad un ritardo in meno in confronto con il numero degli accumulatori e vengono sommate (635) in modo tale che tutte le uscite di riporto degli accumulatori di ordine superiore vengano sommate per dar luogo ad una somma complessiva zero in modo da non sfalsare la desiderata regolazione frazionale del primo accumulatore.
ITRM910653A 1990-08-31 1991-08-30 Sintetizzatore di frequenza n-frazionale ad accumulatori multipli in combinazione latch. IT1250771B (it)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US07/576,342 US5070310A (en) 1990-08-31 1990-08-31 Multiple latched accumulator fractional N synthesis

Publications (3)

Publication Number Publication Date
ITRM910653A0 ITRM910653A0 (it) 1991-08-30
ITRM910653A1 ITRM910653A1 (it) 1993-03-02
IT1250771B true IT1250771B (it) 1995-04-21

Family

ID=24304043

Family Applications (1)

Application Number Title Priority Date Filing Date
ITRM910653A IT1250771B (it) 1990-08-31 1991-08-30 Sintetizzatore di frequenza n-frazionale ad accumulatori multipli in combinazione latch.

Country Status (17)

Country Link
US (1) US5070310A (it)
JP (1) JP2844389B2 (it)
KR (1) KR960001074B1 (it)
AT (1) AT402247B (it)
AU (1) AU632243B2 (it)
BR (1) BR9105891A (it)
CA (1) CA2066745C (it)
DE (2) DE4192081C2 (it)
DK (1) DK54892D0 (it)
ES (1) ES2088714B1 (it)
FR (1) FR2666464A1 (it)
GB (1) GB2255680B (it)
IE (1) IE67289B1 (it)
IT (1) IT1250771B (it)
MX (1) MX9100853A (it)
SE (1) SE469579B (it)
WO (1) WO1992004766A1 (it)

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US5777521A (en) * 1997-08-12 1998-07-07 Motorola Inc. Parallel accumulator fractional-n frequency synthesizer
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KR100346839B1 (ko) 2000-10-10 2002-08-03 삼성전자 주식회사 시그마-델타 변조기를 이용한 분수-ｎ 주파수 합성 장치및 그 방법
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US7003049B2 (en) * 2001-06-12 2006-02-21 Rf Micro Devices, Inc. Fractional-N digital modulation with analog IQ interface
US6385276B1 (en) 2001-06-12 2002-05-07 Rf Micro Devices, Inc. Dual-modulus prescaler
US6710951B1 (en) * 2001-10-31 2004-03-23 Western Digital Technologies, Inc. Phase locked loop employing a fractional frequency synthesizer as a variable oscillator
JP3901607B2 (ja) * 2002-07-23 2007-04-04 日本電気株式会社 信号処理装置及び非整数分周器並びにこれを用いたフラクショナルｎ−ｐｌｌシンセサイザ
US7437393B2 (en) 2002-07-23 2008-10-14 Nec Corporation Signal processing apparatus, non-integer divider, and fractional N-PLL synthesizer using the same
JP2004104228A (ja) * 2002-09-05 2004-04-02 Matsushita Electric Ind Co Ltd 信号処理装置および信号処理方法、デルタ・シグマ変調型分数分周ｐｌｌ周波数シンセサイザ、無線通信機器、デルタ・シグマ変調型ｄ／ａ変換器
US6952125B2 (en) * 2002-10-25 2005-10-04 Gct Semiconductor, Inc. System and method for suppressing noise in a phase-locked loop circuit
JP4064338B2 (ja) * 2003-12-10 2008-03-19 松下電器産業株式会社 デルタシグマ型分数分周ｐｌｌシンセサイザ
CN100530939C (zh) 2004-03-19 2009-08-19 松下电器产业株式会社 调频装置、包括该调频装置的发送装置及无线通信机器
US7482885B2 (en) * 2005-12-29 2009-01-27 Orca Systems, Inc. Method of frequency synthesis for fast switching
US7519349B2 (en) * 2006-02-17 2009-04-14 Orca Systems, Inc. Transceiver development in VHF/UHF/GSM/GPS/bluetooth/cordless telephones
US8443023B2 (en) * 2007-03-13 2013-05-14 Applied Micro Circuits Corporation Frequency synthesis rational division
RU2423784C2 (ru) * 2009-01-11 2011-07-10 Общество с ограниченной ответственностью Научно-производственная фирма "Радиокомпоненты" Синтезатор частот
RU2423782C1 (ru) * 2010-03-25 2011-07-10 Государственное образовательное учреждение высшего профессионального образования Марийский государственный технический университет Цифровой синтезатор многофазных сигналов
US8971455B2 (en) * 2011-12-12 2015-03-03 Texas Instruments Incorporated Near-integer channel spur mitigation in a phase-locked loop
RU2616877C1 (ru) * 2015-12-07 2017-04-18 Федеральное государственное бюджетное образовательное учреждение высшего образования "Кубанский государственный технологический университет" (ФГБОУ ВО "КубГТУ") Цифровой генератор гармонических сигналов
RU2726833C1 (ru) * 2019-10-17 2020-07-15 Федеральное государственное бюджетное образовательное учреждение высшего образования "Поволжский государственный технологический университет" Цифровой вычислительный синтезатор с подавлением перекрестных помех

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Also Published As

Publication number Publication date
CA2066745C (en) 1996-09-17
IE67289B1 (en) 1996-03-20
GB9209282D0 (en) 1992-07-08
FR2666464A1 (fr) 1992-03-06
KR960001074B1 (ko) 1996-01-18
WO1992004766A1 (en) 1992-03-19
AU8395591A (en) 1992-03-30
SE469579B (sv) 1993-07-26
DK54892A (da) 1992-04-28
JPH05502154A (ja) 1993-04-15
MX9100853A (es) 1992-04-01
DE4192081C2 (de) 1996-02-01
ITRM910653A1 (it) 1993-03-02
BR9105891A (pt) 1992-10-13
GB2255680B (en) 1994-08-03
SE9201350L (sv) 1992-06-22
DE4192081T (it) 1992-08-27
CA2066745A1 (en) 1992-03-01
ITRM910653A0 (it) 1991-08-30
ATA900691A (de) 1996-07-15
AT402247B (de) 1997-03-25
AU632243B2 (en) 1992-12-17
JP2844389B2 (ja) 1999-01-06
IE913059A1 (en) 1992-03-11
ES2088714A1 (es) 1996-08-16
US5070310A (en) 1991-12-03
ES2088714B1 (es) 1997-02-16
DK54892D0 (da) 1992-04-28
FR2666464B1 (it) 1997-02-21
SE9201350D0 (sv) 1992-04-29
KR920702570A (ko) 1992-09-04
GB2255680A (en) 1992-11-11

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TA Fee payment date (situation as of event date), data collected since 19931001

Effective date: 19960722