HK1208285B - Back side illuminated single photon avalanche diode and imaging sensor system comprising the same - Google Patents

Abstract

The subject application relates to a back side illuminated single photon avalanche diode and an imaging sensor system comprising the same. A single photon avalanche diode (SPAD) includes an n doped epitaxial layer disposed in a first semiconductor layer. A p doped epitaxial layer is above the n doped epitaxial layer on a back side of the first semiconductor layer. A multiplication junction is defined at an interface between the n doped epitaxial layer and the p doped epitaxial layer. A multiplication junction is reversed biased above a breakdown voltage such that a photon received through the back side of the first semiconductor layer triggers an avalanche multiplication process in the multiplication junction. A p- doped guard ring region is implanted in the n doped epitaxial layer surrounding the multiplication junction.

Description

Backside illuminated single photon avalanche diode and imaging sensor system comprising same

Technical Field

The present invention relates generally to photodetectors, and more specifically, the present invention is directed to imaging systems including single photon avalanche diode imaging sensors.

Background

Image sensors have become ubiquitous. It is widely used in digital still cameras, cellular telephones, security cameras, as well as in medical, automotive and other applications. The technology used to manufacture image sensors has been continuously and rapidly advancing. For example, the demand for higher resolution and lower power consumption has facilitated further miniaturization and integration of these image sensors.

One type of photodetector that may be used in image sensors or photodetectors is the Single Photon Avalanche Diode (SPAD). SPADs, also known as Geiger-mode avalanche photodiodes (GM-APDs), are solid-state photodetectors capable of detecting low intensity signals, e.g., as low as a single photon. SPAD imaging sensors are semiconductor photosensitive devices consisting of an array of SPAD regions fabricated on a silicon substrate. The SPAD region produces an output pulse when struck by a photon. The SPAD region has a p-n junction that is reverse biased above the breakdown voltage so that a single photo-generated carrier can trigger an avalanche multiplication process that causes the current at the output of the photon detection cell to quickly reach its final value. This avalanche current continues until the avalanche process is quenched by reducing the bias voltage using a quenching element. The intensity of the photon signals received by the image sensor is obtained by counting the number of these output pulses within a time window.

One of the challenges faced in sensing photons is achieving high blue detection efficiency with backside illuminated (BSI) SPADs. For example, in BSI image sensors, the back surface may include implants having defects that require laser annealing. These defects can render SPAD devices made by these techniques unable to sustain the required electric field. In addition, SPAD devices having these defects can be noisy and therefore suffer from poor performance.

Disclosure of Invention

One embodiment of the present application relates to a Single Photon Avalanche Diode (SPAD). The SPAD comprises: an n-doped epitaxial layer disposed in the first semiconductor layer; a p-doped epitaxial layer formed over the n-doped epitaxial layer on a backside of the first semiconductor layer; a multiplication junction defined at an interface between the n-doped epitaxial layer and the p-doped epitaxial layer, wherein multiplication junction is reverse biased above a breakdown voltage such that photons received through the backside of the first semiconductor layer trigger an avalanche multiplication process in the multiplication junction; and a p-doped guard ring region implanted in the n-doped epitaxial layer surrounding the multiplication junction.

Another embodiment of the present application relates to an imaging sensor system. The imaging sensor system includes: a first semiconductor layer of a first wafer; a Single Photon Avalanche Diode (SPAD) imaging array comprising a plurality of pixels formed in the first semiconductor layer, wherein each pixel comprises a SPAD comprising: an n-doped epitaxial layer disposed in the first semiconductor layer; a p-doped epitaxial layer formed over the n-doped epitaxial layer on a backside of the first semiconductor layer; a multiplication junction defined at an interface between the n-doped epitaxial layer and the p-doped epitaxial layer, wherein multiplication junction is reverse biased above a breakdown voltage such that photons received through the backside of the first semiconductor layer trigger an avalanche multiplication process in the multiplication junction; a p-doped guard ring region implanted in the n-doped epitaxial layer surrounding the multiplication junction; a second semiconductor layer bonded to a second wafer of the first wafer; a plurality of digital counters formed in the second semiconductor layer and electrically coupled to the SPAD imaging array, wherein each of the plurality of digital counters is coupled to count output pulses generated by a respective one of the plurality of pixels.

Drawings

Non-limiting and non-exhaustive embodiments of the present invention are described with reference to the following figures, wherein like reference numerals refer to like parts throughout the various views unless otherwise specified.

Figure 1 is an exploded view of one example of a stacked semiconductor wafer with integrated circuit dies of an example Single Photon Avalanche Diode (SPAD) imaging sensor system according to the teachings of this disclosure.

FIG. 2 is a circuit diagram illustrating one example of a stacked-chip SPAD imaging sensor system including quenching elements according to the teachings of the invention.

Figure 3A is a cross-sectional view of one example of an integrated circuit system including a SPAD imaging sensor system with stacked device wafers according to the teachings of this disclosure.

Figure 3B is a cross-sectional view of one example of an integrated circuit system including a SPAD imaging sensor system having three stacked device wafers according to the teachings of this disclosure.

Figure 4 is a block diagram showing one example of an integrated circuit system with an example SPAD imaging sensor system according to the teachings of this disclosure.

Corresponding reference characters indicate corresponding parts throughout the several views of the drawings. Skilled artisans will appreciate that elements in the figures are illustrated for simplicity and clarity and have not necessarily been drawn to scale. For example, the dimensions of some of the elements in the figures may be exaggerated relative to other elements to help improve understanding of various embodiments of the present invention. Additionally, common but well-understood elements that are useful or necessary in a commercially feasible embodiment are often not depicted in order to facilitate a less obstructed view of these various embodiments of the present invention.

Detailed Description

In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present invention. However, it will be apparent to one skilled in the art that the specific details need not be employed to practice the present invention. In other instances, well-known materials or methods have not been described in detail in order to avoid obscuring the present invention.

Reference throughout this specification to "one embodiment," "an embodiment," "one example," or "an example" means that a particular feature, structure, or characteristic described in connection with the embodiment or example is included in at least one embodiment of the present invention. Thus, the appearances of the phrases "in one embodiment," "in an embodiment," "one example" or "an example" in various places throughout this specification are not necessarily all referring to the same embodiment or example. Furthermore, the particular features, structures, or characteristics may be combined in any suitable combination and/or sub-combination in one or more embodiments or examples. The particular features, structures, or characteristics may be included in integrated circuits, electronic circuits, combinational logic circuits, or other suitable components that provide the described functionality. Additionally, it should be appreciated that the figures provided herewith are for purposes of explanation to persons skilled in the art and that the drawings are not necessarily drawn to scale.

As will be discussed, an exemplary Single Photon Avalanche Diode (SPAD) imaging sensor system according to the teachings of this disclosure includes a SPAD imaging array in which each SPAD is adapted to be illuminated from a backside and includes a thin p-epitaxial layer formed on the backside over a thicker n-epitaxial layer to define a multiplication junction for each SPAD according to the teachings of this disclosure. By forming a thin P-epitaxial layer over the backside, it is no longer necessary to form the backside P + layer by implantation, which can result in implant damage induced traps in the multiplication junction. Forming the p-epitaxial layer on the backside according to the teachings of the present invention also avoids using laser annealing to try to repair implant damage, but also results in the junction being deeper. Furthermore, according to the teachings of the present invention, with the p-epitaxial layer formed on the backside, very low noise is now achieved, which improves the performance of the exemplary SPAD.

To illustrate, FIG. 1 is an exploded view of stacked device wafers 100 and 100' that are bonded together to form one example of an integrated circuit system 102 according to the teachings of this disclosure. The device wafers 100 and 100' may comprise silicon, gallium arsenide, or other suitable semiconductor materials. In the illustrated example, device wafer 100 includes semiconductor die 111-119, while device wafer 100' includes corresponding semiconductor die (view is obscured in FIG. 1). As will be discussed in more detail below, in some examples, each die 111 and 119 of the device wafer 100 may include a backside illuminated SPAD array that includes a thin p-epitaxial layer formed on the backside over a thicker n-epitaxial layer to define multiplication junctions, while each corresponding die of the device wafer 100' with CMOS circuitry includes an array of digital counters and associated readout electronics fabricated, for example, using standard CMOS processes. The placement of the digital counters on the separate bottom device wafer 100' allows for extremely high fill factors in the SPAD array on the top device wafer 100. Furthermore, because the device wafer 100 is formed separately from the device wafer 100', custom fabrication processes may be utilized to optimize the formation of SPAD regions in a SPAD array on the device wafer 100 while maintaining conventional CMOS processes in forming CMOS circuitry on the device wafer 100', in accordance with the teachings of the present invention.

FIG. 2 is a circuit diagram illustrating one example of a stacked SPAD imaging sensor system including quenching elements according to the teachings of this disclosure. It should be noted that the PIXEL circuit (e.g., PIXEL) illustrated in fig. 2₁、PIXEL₂、…PIXEL_N) Is one possible example of a SPAD pixel circuit architecture for implementing each pixel with an imaging array. In the example depicted in FIG. 2, the PIXEL PIXEL is₁To PIXEL_NIllustrated as arranged in a single row. However, in other examples, it should be appreciated that the pixels of the imaging array may be arranged in a single column or in a two-dimensional array of columns and rows.

As shown in the examples, each example pixel includes a coupling to a respective quenching element (e.g., quenching element Q) disposed in a top chip of a stacked chip system₁-Q_N) SPAD (e.g., SPAD)₁-SPAD_N). In the illustrated example, it should be noted that each SPAD includes a thin p-epitaxial layer formed on the backside over a thicker n-epitaxial layer to design the multiplication junction, in accordance with the teachings of the present disclosure. In various examples, it should also be noted that coupling to each respective SPAD is in accordance with the teachings of this disclosure₁-SPAD_NExemplary quenching element Q₁-Q_NMay be included in the top chip or the bottom chip. It should also be appreciated that exemplary quenching element Q can be implemented using passive or active quenching elements in accordance with the teachings of the present invention₁-Q_N。

As shown in the example, there are N numbers of SPADs, N numbers of quenching elements, and N numbers of digital counters (e.g., digital counters 1-N). In the depicted example, the digital counters 1-N are implemented using CMOS circuitry disposed on a bottom chip of a stacked chip system fabricated using standard CMOS processes and are electrically coupled to receive output pulses 202 generated by respective SPADs in response to received photons. Digital counters 1-N may be enabled to count the number of output pulses 202 generated by each respective SPAD during a time window and output a digital signal 204 representative of the count. Although the example depicted in fig. 2 illustrates a direct connection between the pixel circuit and the digital counter, any connection between the pixel circuit and the digital counter may be utilized in accordance with the teachings of this disclosure, including by means of AC coupling. Further, any known SPAD bias polarity and/or orientation may be implemented. In one example, each digital counter includes an amplifier to amplify received output pulses 202. Alternatively or in addition to digital counters, timing circuitry may be placed in each pixel/column/array to time the arrival of incident photons.

In operation, via above each SPAD₁-SPAD_NBias voltage V of breakdown voltage_BIASTo reverse bias each SPAD₁-SPAD_N. Triggering at each SPAD in response to a single photogenerated carrier₁-SPAD_NCauses an avalanche multiplication process of the avalanche current at the output. This avalanche current is responsive across a quenching element (e.g., Q)₁-Q_N) The resulting voltage drop, which causes the bias voltage across the SPAD to drop, self-quenches. After quenching of the avalanche current, the voltage across the SPAD is restored above the bias voltage and then the SPAD is ready to be triggered again. Each SPAD₁-SPAD_NAre received by respective digital counters 1-N, toThe corresponding digital counter increments its count in response thereto.

Conventional SPAD designs incorporating SPADs on the same chip as CMOS digital counters made using standard CMOS processes suffer from reduced fill factor on the imaging plane due to the area occupied by the CMOS circuitry itself. Thus, one advantage of implementing a stacked chip structure according to the teachings of this disclosure is that, in the case of SPADs on a top chip and CMOS circuitry on a separate bottom chip, there is no need to reduce the fill factor of the SPAD imaging array on the top chip to provide space to accommodate CMOS circuitry on the same chip, according to the teachings of this disclosure.

It should be noted that the circuit diagram of fig. 2 is provided herewith for explanatory purposes and some circuit elements, such as passive components, e.g., resistors and capacitors, and active components, e.g., transistors, are not shown in detail so as not to obscure the teachings of the present invention. For example, the illustrated pixel circuit of fig. 2 may generate an output pulse that requires amplification prior to sensing by the input of a digital counter. In another example, quenching element Q₁With SPAD₁The connection at the node between will be at a high voltage, which may require AC coupling.

Figure 3A is a cross-sectional view of a portion of one example of an integrated circuit system 300A including a SPAD imaging sensor system with stacked device wafers according to the teachings of this disclosure. Integrated circuit system 300A is one possible implementation of a portion of the exemplary integrated circuit system illustrated in fig. 1-2 above. The illustrated example of an integrated circuit system 300A shown in fig. 3A includes a first device wafer 304, a second device wafer 306, and a bonding interface 307 where the first device wafer 304 is bonded to the second device wafer 306. The first device wafer 304 includes a first semiconductor layer 310 and a first interconnect layer 312, while the second device wafer 306 is shown to include a second semiconductor layer 314 and a second interconnect layer 316. In this example, semiconductor layer 310 is shown to include a SPAD imaging array that includes SPAD region 302, SPAD region 302 being one of a plurality of SPAD regions formed in semiconductor layer 310, in accordance with the teachings of this disclosure. In various examples, each of the plurality of SPAD regions of the SPAD imaging array formed in semiconductor layer 310 is substantially similar to SPAD region 302, but is not illustrated in detail so as not to obscure the teachings of the present disclosure. In one example, a SPAD imaging array including SPAD regions 302 is adapted for illumination from the backside, formed near the front side of semiconductor layer 310 and may be arranged in a plurality of rows and columns in accordance with the teachings of this disclosure.

In the depicted example, the second device wafer 306 is a CMOS logic chip fabricated using standard CMOS processes and including a semiconductor layer 314, the semiconductor layer 314 shown including a digital counter 308, the digital counter 308 being one of the digital counters formed in the semiconductor layer 314, in accordance with the teachings of the present disclosure. In various examples, each of the plurality of digital counters formed in the semiconductor layer 314 is substantially similar to the digital counter 308, but is not illustrated in detail so as not to obscure the teachings of the present disclosure. In the example, each digital counter is formed near the front side of the semiconductor layer 314 and is coupled to a respective SPAD region. For example, as shown in the depicted example, the digital counters 308 are coupled to the respective SPAD regions 302 by way of metal traces 309, 310, 317, and 318 and vias 329 and 330. In other words, in the depicted example, each SPAD region is coupled to its own respective CMOS circuitry (e.g., SPAD region 302 is coupled to its own CMOS circuitry, i.e., digital counter 308). In one example, other circuitry can be formed in the second semiconductor layer 314 and coupled to the respective SPAD regions via metal traces. Digital or analog circuitry, such as timing circuitry, may be used for applications such as time-of-flight.

In one example, vias 329 and 330 are micro through silicon vias (μ TSVs) disposed in oxide layer 328. In one example, the metal traces 309, 310, 317, and 318 can include redistribution layers (RDLs) comprising thin films (e.g., aluminum, copper, etc.) for rerouting and redistributing electrical connections between each of the plurality of SPAD areas (e.g., SPAD area 302) and a respective one of the plurality of digital counters (e.g., digital counter 308). In one example, the μ TSVs 329 and 330 can include a conductive material (e.g., copper, polysilicon, etc.) deposited therein.

In one example, semiconductor layer 310 and semiconductor layer 314 may comprise epitaxially grown silicon layers. In one example, semiconductor layer 310 is n-doped epitaxially grown silicon. As shown in the example depicted in figure 3A, the SPAD region 302 includes a thin p-doped epitaxial layer 322 formed over the backside of a thicker n-doped epitaxial layer of the first semiconductor layer 310, in accordance with the teachings of the present disclosure. In one example, the p-doped epitaxial layer 322 has a thickness of less than approximately 500nm, and the thicker n-doped epitaxially grown silicon layer of the first semiconductor layer 310 has a thickness of less than approximately 3 μm.

As shown in the example, the multiplication junction 321 is defined at a pn junction defined at the interface between the n-doped epitaxial layer 310 and the p-doped epitaxial layer 322. In one example, the SPAD multiplication junction 321 has a width less than approximately 100nm and it has a doping profile that is well controllable by the epitaxial layer doping profile. For example, in one example, the p-doped epitaxial layer 322 has a graded doping profile in order to optimize SPAD performance in accordance with the teachings of this disclosure. In one example, the multiplication junction 321 is reverse biased above the breakdown voltage such that photons received through the backside of the first semiconductor layer 310 trigger an avalanche multiplication process in the multiplication junction 321, in accordance with the teachings of this disclosure.

As shown in the example depicted in figure 3A, a p-doped guard ring region 320 is implanted in the n-doped epitaxial layer 310 surrounding the multiplication junctions 321 to provide isolation for the SPAD 302, in accordance with the teachings of the present disclosure. As shown in the example, a p + doped contact region 324 is implanted within the p-doped guard ring region 320. In the example, the p + doped contact region 324 has a higher doping concentration than the p-doped guard ring region 320. As such, the p + doped contact region 324 is coupled to provide contact from the front side of the first semiconductor layer 310 to the p-doped epitaxial layer 322, through the metal trace 317, via 329, and metal trace 309 to, for example, the digital counter 308, while the guard ring region 320 provides isolation, in accordance with the teachings of the present invention.

In the example, an n + doped contact region 326 is disposed in the n-doped epitaxial layer on the front side of the first semiconductor layer 310, as shown. As such, the n + doped contact region 326 is coupled to provide contact from the front side of the first semiconductor layer 310 to the n-doped epitaxial layer of the first semiconductor layer 310, through the metal trace 319, the via 330, and the metal trace 310 to, for example, the digital counter 308, in accordance with the teachings of this disclosure.

As illustrated in the depicted example of fig. 3A, the multiplication junction 321 between the n-doped epitaxial layer 310 and the p-doped epitaxial layer 322 is adapted to be illuminated with photons through the backside of the first semiconductor layer 310, in accordance with the teachings of the present disclosure. In this example, a shallow p-doped epitaxial layer 322 on the backside of the first semiconductor layer 310 provides improved high blue sensitivity while maintaining good junction characteristics and low noise according to the teachings of this disclosure. In another example, the polarity of the doped regions of the integrated circuit system 300A may be reversed. For example, the epitaxial layer 310 and the contact region 326 may be p-doped and p + doped, respectively, and the guard ring 320, the epitaxial layer 322, and the contact region 324 may be n-doped, and n + doped, respectively.

Figure 3B is a cross-sectional view of an integrated circuit system 300B having stacked device dies 304, 306, and 340, according to an embodiment of the invention. Integrated circuit system 300B is one possible implementation of a portion of integrated circuit system 102 of fig. 1. The illustrated example of integrated circuit system 300B includes a first device die 304, a second device die 306, a third device die 340, and bonding interfaces 307 and 344. The first device wafer 304 and the second device wafer 306 are bonded and operate as discussed above. However, integrated circuit system 300B includes an additional third wafer 340 bonded to second device wafer 306. As shown, the third wafer 340 includes a third semiconductor layer 342 and semiconductor devices 346 formed in or on the third device wafer 340. In one embodiment, device 346 includes storage, such as Random Access Memory (RAM), to act as frame storage to enable high speed burst imaging capabilities. In this example, the device 346 may be coupled to receive and store the output of a digital counter included in the second semiconductor layer 314.

Figure 4 is a block diagram showing one example of an integrated circuit system with an example SPAD imaging sensor system 400 according to the teachings of this disclosure. The SPAD imaging sensor system 400 can be one example implementation of portions of the example stacked integrated circuit system illustrated in figures 1-3 above. The illustrated embodiment of the SPAD imaging sensor system 400 shown in fig. 4 includes a SPAD imaging array 405, high speed readout circuitry 410, functional logic 415, and control circuitry 420.

As shown in the depicted example, the imaging array 405 is a two-dimensional ("2D") array of backside illuminated imaging sensors or pixels (e.g., pixels P1, P2 …, Pn). In one example, each pixel includes a SPAD region adapted for illumination from the back side and including a thin p-epitaxial layer formed on the back side over a thicker n-epitaxial layer to define a multiplication junction for each SPAD region in accordance with the teachings of this disclosure. As illustrated in the depicted example, each pixel is arranged into a row (e.g., row R1-Ry) and a column (e.g., column C1-Cx) to acquire image data of a person, place, or object, which can then be used to render a 2D image of the person, place, or object. The imaging array 405 may also be used in a timed mode to give a "temporal image" of the scene, which may be used for range information in time-of-flight applications or for fluorescence lifetime for medical applications.

The output pulses generated by the SPAD region of the imaging array 405 are read out by the high speed readout circuitry 410 and transferred to the functional logic 415. The readout circuitry 410 includes at least one digital counter for each of the SPAD regions and may also include amplification circuitry and/or quenching circuitry. Function logic 415 may simply store the image data in memory or even manipulate the image data by applying post-image effects (e.g., crop, rotate, remove red eye, adjust brightness, adjust contrast, or otherwise). The control circuitry 420 is coupled to the imaging array 405 and/or the readout circuitry 410 to control the operating characteristics of the imaging array 405. For example, the control circuit 420 may simultaneously enable each of the digital counters included in the high speed readout circuit 410 over a window of time in order to implement a global shutter operation. Thus, the embodiments of SPAD stacked-chip image sensors discussed herein provide imaging that is both high speed and low light sensitivity, which is typically not achievable with conventional sensor architectures.

The above description of illustrated examples of the invention, including what is described in the summary, is not intended to be exhaustive or to be limited to the precise forms disclosed. While specific embodiments of, and examples for, the invention are described herein for illustrative purposes, various equivalent modifications can be made without departing from the broader spirit and scope of the invention.

These modifications can be made to the examples of the invention in light of the above detailed description. The terms used in the following claims should not be construed to limit the invention to the specific embodiments disclosed in the specification and the claims. Rather, the scope is to be determined entirely by the following claims, which are to be construed in accordance with established doctrines of claim interpretation. The specification and drawings are, accordingly, to be regarded in an illustrative rather than a restrictive sense.

Claims (18)

1. A single photon avalanche diode SPAD, comprising:

an n-doped epitaxial layer disposed in the first semiconductor layer;

a p-doped epitaxial layer formed over the n-doped epitaxial layer on a back side of the first semiconductor layer, wherein the p-doped epitaxial layer covers the entire back side of the first semiconductor layer;

a multiplication junction defined at an interface between the n-doped epitaxial layer and the p-doped epitaxial layer, wherein multiplication junction is reverse biased above a breakdown voltage such that photons received through the backside of the first semiconductor layer trigger an avalanche multiplication process in the multiplication junction; and

a p-doped guard ring region implanted in the n-doped epitaxial layer surrounding the multiplication junction, wherein the p-doped epitaxial layer covers the entire p-doped guard ring region from the backside of the first semiconductor layer.

2. The SPAD of claim 1, further comprising an n + doped contact region disposed in the n-doped epitaxial layer, wherein the n + doped contact region is coupled to provide contact to the n-doped epitaxial layer from a front side of the first semiconductor layer.

3. The SPAD of claim 1, further comprising a p + doped contact region implanted within the p-doped guard ring region, wherein the p + doped contact region is coupled to provide contact to the p-doped epitaxial layer from a front side of the first semiconductor layer.

4. The SPAD of claim 3, wherein the p + doped contact region has a higher doping concentration than the p-doped guard ring region.

5. The SPAD of claim 1, wherein the p-doped epitaxial layer has a graded doping profile.

6. An imaging sensor system, comprising:

a first semiconductor layer of a first wafer;

a single photon avalanche diode, SPAD, imaging array comprising a plurality of pixels formed in the first semiconductor layer, wherein each pixel comprises a SPAD comprising:

an n-doped epitaxial layer disposed in the first semiconductor layer;

a p-doped epitaxial layer formed over the n-doped epitaxial layer on a back side of the first semiconductor layer, wherein the p-doped epitaxial layer covers the entire back side of the first semiconductor layer;

a multiplication junction defined at an interface between the n-doped epitaxial layer and the p-doped epitaxial layer, wherein multiplication junction is reverse biased above a breakdown voltage such that photons received through the backside of the first semiconductor layer trigger an avalanche multiplication process in the multiplication junction;

a p-doped guard ring region implanted in the n-doped epitaxial layer surrounding the multiplication junction, wherein the p-doped epitaxial layer covers the entire p-doped guard ring region from the backside of the first semiconductor layer;

a second semiconductor layer bonded to a second wafer of the first wafer;

a plurality of digital counters formed in the second semiconductor layer and electrically coupled to the SPAD imaging array, wherein each of the plurality of digital counters is coupled to count output pulses generated by a respective one of the plurality of pixels.

7. The imaging sensor system of claim 6, wherein each SPAD further comprises an n + doped contact region disposed in the n-doped epitaxial layer, wherein the n + doped contact region is coupled to provide contact to the n-doped epitaxial layer from a front side of the first semiconductor layer.

8. The imaging sensor system of claim 6, wherein each SPAD further comprises a p + doped contact region implanted within the p-doped guard ring region, wherein the p + doped contact region is coupled to provide contact to the p-doped epitaxial layer from a front side of the first semiconductor layer.

9. The imaging sensor system of claim 8, wherein the p + doped contact region has a higher doping concentration than the p-doped guard ring region.

10. The imaging sensor system of claim 6, wherein the p-doped epitaxial layer has a graded doping profile.

11. The imaging sensor system of claim 6, wherein each of the plurality of digital counters formed in the second semiconductor layer comprises a Complementary Metal Oxide Semiconductor (CMOS) circuit disposed in the second semiconductor layer of the second wafer.

12. The imaging sensor system of claim 6, wherein the plurality of pixels includes a N number of pixels, wherein the plurality of digital counters includes at least a N number of digital counters, and wherein each of the N number of digital counters is coupled to a respective one of the plurality of pixels.

13. The imaging sensor system of claim 6, further comprising:

a first interconnect layer disposed on a front side of the first semiconductor layer; and

a second interconnect layer disposed on the second semiconductor layer, wherein the first wafer is bonded to the second wafer at a bonding interface between the first interconnect layer and the second interconnect layer.

14. The imaging sensor system of claim 13, wherein the first interconnect layer includes a first oxide, the second interconnect layer includes a second oxide, and wherein the bonding interface includes an interface between the first oxide and the second oxide.

15. The imaging sensor system of claim 14, wherein the first interconnect layer comprises a plurality of vias, wherein each of the plurality of vias is coupled to a respective pixel of the SPAD imaging array to communicate the output pulse to the second interconnect layer at the bonding interface.

16. The imaging sensor system of claim 6, wherein each pixel comprises a quenching element coupled to a respective SPAD to quench an avalanche of the respective SPAD by reducing a bias voltage.

17. The imaging sensor system of claim 6, further comprising control circuitry formed in the second semiconductor layer and coupled to the SPAD imaging array to control operation of the SPAD imaging array.

18. The imaging sensor system of claim 17, further comprising functional logic formed in the second semiconductor layer and coupled to the plurality of digital counters to store data read out from the SPAD imaging array.