HK1218347B - Back side illuminated image sensor with guard ring region reflecting structure - Google Patents

Description

Back-illuminated image sensor with guard ring area reflective structure

Technical Field

The present invention relates generally to photodetectors, and more particularly, the present invention is directed to imaging systems including single photon avalanche diode imaging sensors.

Background Art

Image sensors have become ubiquitous. They are widely used in digital still cameras, cellular phones, surveillance cameras, as well as in medical, automotive, and other applications. The technology used to manufacture image sensors, and in particular complementary metal oxide semiconductor (CMOS) image sensors (CIS), continues to advance significantly. For example, the demand for high resolution and low power consumption has driven the further miniaturization and integration of these image sensors.

Two application areas where size and image quality are particularly important are medical imaging and automotive applications. For these applications, image sensor chips must typically provide high-quality images in the visible spectrum with improved sensitivity in the infrared and near-infrared parts of the spectrum.

Summary of the Invention

One aspect of an embodiment of the present invention relates to a photon detector comprising: a single-photon avalanche diode (SPAD) disposed near the front side of a first semiconductor layer, wherein the SPAD includes a multiplication junction defined in the first semiconductor layer at an interface between an n-doped layer and a p-doped layer of the SPAD, wherein the multiplication junction is reverse biased above a breakdown voltage so that light guided into the SPAD through the back side of the first semiconductor layer triggers an avalanche multiplication process in the multiplication junction; a guard ring disposed near the SPAD in a guard ring region in the first semiconductor layer, wherein the guard ring surrounds the SPAD to isolate the SPAD in the first semiconductor; and a guard ring region reflective structure disposed near the guard ring and near the front side of the first semiconductor layer in the guard ring region so that light that bypasses the SPAD and is guided into the guard ring region through the back side of the first semiconductor layer is redirected by the guard ring region reflective structure back into the first semiconductor layer and into the SPAD.

Another aspect of an embodiment of the present invention relates to an imaging sensor system comprising: a pixel array having a plurality of pixel cells disposed in a first semiconductor layer, wherein each of the plurality of pixel cells comprises: a single-photon avalanche diode (SPAD) disposed proximate to a front side of the first semiconductor layer, wherein the SPAD comprises a multiplication junction defined in the first semiconductor layer at an interface between an n-doped layer and a p-doped layer of the SPAD, wherein the multiplication junction is reverse biased above a breakdown voltage such that light guided into the SPAD through a back side of the first semiconductor layer triggers an avalanche multiplication process in the multiplication junction; and a guard ring disposed in the first semiconductor layer. a guard ring region disposed close to the SPAD in a guard ring area, wherein the guard ring surrounds the SPAD to isolate the SPAD in the first semiconductor layer; and a guard ring region reflective structure disposed in the guard ring area close to the guard ring and close to the front side of the first semiconductor layer, so that light that bypasses the SPAD and is guided into the guard ring area through the back side of the first semiconductor layer is redirected by the guard ring region reflective structure back into the first semiconductor layer and into the SPAD; a control circuit coupled to the pixel array to control the operation of the pixel array; and a readout circuit coupled to the pixel array to read out image data from the plurality of pixel units.

BRIEF DESCRIPTION OF THE DRAWINGS

Non-limiting and non-exhaustive embodiments of the present invention are described with reference to the following figures, wherein like reference numerals refer to like parts throughout the various views unless otherwise specified.

1 is an exploded view of one example of a stacked semiconductor device wafer with integrated circuit die of an example single photon avalanche diode (SPAD) imaging sensor system in accordance with the teachings of the present invention.

2 is a circuit diagram illustrating one example of a stacked chip system including a photon detector having a SPAD coupled to a quenching element and a counter circuit in accordance with the teachings of the present invention.

Figure 3 is a cross-sectional view of an example of a photon detector implemented in a semiconductor device wafer of a stacked chip system according to the teachings of the present invention, wherein the stacked chip system includes a SPAD surrounded by a guard ring and an example guard ring area reflective structure plus an example SPAD area reflective structure included in a metal layer of the semiconductor.

4 is a bottom/top view of one example of a guard ring area reflective structure plus an example SPAD area reflective structure included in a metal layer of a semiconductor device wafer of a stacked chip system in accordance with the teachings of the present invention.

5 is a block diagram showing one example of an integrated circuit system with an example SPAD imaging sensor system in accordance with the teachings of the present invention.

Throughout the several views of the drawings, corresponding reference symbols indicate corresponding components. Those skilled in the art will appreciate that the elements in the figures are illustrated for simplicity and clarity and are not necessarily drawn to scale. For example, the dimensions of some elements in the figures may be exaggerated relative to other elements to help improve understanding of the various embodiments of the present invention. Furthermore, common but well-understood elements that are useful or necessary in commercially feasible embodiments are not depicted to facilitate a less obstructed view of these various embodiments of the present invention.

DETAILED DESCRIPTION

In the following description, many specific details are set forth to provide a thorough understanding of the present invention. However, it will be apparent to one of ordinary skill in the art that specific details are not required to practice the present invention. In other instances, well-known materials or methods are not described in detail to avoid obscuring the present invention.

References throughout this specification to "one embodiment," "an embodiment," "an example," or "an instance" mean that a particular feature, structure, or characteristic described in connection with the embodiment or instance is included in at least one embodiment of the present invention. Thus, the phrases "in one embodiment," "in an embodiment," "an example," or "an instance" appearing throughout this specification are not necessarily all referring to the same embodiment or instance. Furthermore, in one or more embodiments or instances, the particular features, structures, or characteristics may be combined in any suitable combinations and/or subcombinations. The particular features, structures, or characteristics may be included in integrated circuits, electronic circuits, combinational logic circuits, or other suitable components that provide the described functionality. In addition, it should be understood that the figures provided herein are for explanation purposes to persons of ordinary skill in the art and are not necessarily drawn to scale.

In a typical image sensor, a significant portion of the incident infrared or near-infrared light can propagate through the semiconductor material (e.g., silicon) of the image sensor without being absorbed. To help increase the amount of infrared or near-infrared light absorbed, thicker silicon is typically required. However, there is a trade-off because the semiconductor material of a typical image sensor is typically thinned to improve visible light performance, which degrades the infrared or near-infrared performance of the image sensor. An additional challenge faced by back-illuminated systems with photon detectors that include single-photon avalanche diodes (SPADs) is that the fill factor of a SPAD imaging system is not 100% due to the guard ring surrounding the SPAD occupying some of the available area in the semiconductor layer of the imaging sensor. The guard ring area is not as light-sensitive as the high-field p/n+ junction of the SPAD and has worse timing resolution than the high-field p/n+ junction of the SPAD.

Therefore, as will be described below, according to the teachings of the present invention, an example stacked chip imaging sensor system according to the teachings of the present invention is characterized by a back-illuminated SPAD having a guard ring area reflective structure, which is arranged in the guard ring area and the metal layer close to the guard ring surrounding the SPAD on the front side of the semiconductor layer, so that light that bypasses the SPAD and is guided into the guard ring area through the back side of the semiconductor layer is redirected by the guard ring area reflective structure back into the semiconductor layer and into the SPAD to be absorbed by the SPAD.

For illustration, FIG1 is an exploded view of stacked device wafers 100 and 100′ that are joined together to form one example of a stacked-chip integrated circuit imaging sensor system 102 according to the teachings of the present invention. Device wafers 100 and 100′ may comprise silicon, gallium arsenide, or other suitable semiconductor materials. In the illustrated example, device wafer 100 comprises semiconductor chips 111-119, while device wafer 100′ comprises corresponding semiconductor chips (hidden from view in FIG1 ). As will be discussed in greater detail below, in some examples, each chip 111-119 of device wafer 100 may be a pixel die comprising a pixel array of back-illuminated SPADs, wherein each SPAD is surrounded by a guard ring, while each corresponding chip of device wafer 100′ may be an application-specific integrated circuit (ASIC) die having CMOS circuitry including, for example, an array of digital counter circuits and associated readout electronics fabricated using a standard CMOS process. The placement of the counter circuitry on a separate bottom device wafer 100' allows for a very high fill factor in the SPAD pixel array on the top device wafer 100. Furthermore, in accordance with the teachings of the present invention, because device wafer 100 is formed separately from device wafer 100', a customized manufacturing process can be used to optimize the formation of the SPAD region in the SPAD pixel array on device wafer 100, while conventional CMOS processes can be retained when forming the CMOS circuitry on device wafer 100'.

FIG2 is a circuit diagram illustrating one example of a stacked chip integrated circuit imaging sensor system 202 according to the teachings of the present invention, the stacked chip integrated circuit imaging sensor system 202 including a pixel array (including a photon detector having a SPAD coupled to a quenching element) and a counter circuit. It should be noted that the pixel circuits illustrated in FIG2 (e.g., PIXEL ₁ , PIXEL ₂ , ... PIXEL _N ) are one possible example of a SPAD pixel circuit architecture for implementing each pixel using a pixel array. In the example depicted in FIG2, pixels PIXEL ₁ through PIXEL _N are illustrated as being arranged in a single row. However, in other examples, it should be understood that the pixels of the pixel array may be arranged into a single column or into a two-dimensional array of columns and rows.

As shown in the example, each example pixel includes a SPAD (e.g., SPAD ₁ through SPAD _N ) coupled to a respective quenching element (e.g., quenching elements Q ₁ through Q _N ) disposed in the top wafer 200 of the stacked chip system. In the illustrated example, and as will be discussed in further detail below, it should be noted that each SPAD is illuminated through the backside of the semiconductor layer and is surrounded by a guard ring in the semiconductor layer to isolate the SPAD. In the example, a guard ring region reflective structure is disposed proximate to the guard ring in the metal layer in accordance with the teachings of the present invention to deflect incident light into the SPAD region for absorption. In various examples, it should also be noted that the example quenching elements Q ₁ through Q _N coupled to each respective SPAD ₁ through SPAD _N can be included in either the top wafer 200 or the bottom chip 200 ′ in accordance with the teachings of the present invention. It should also be understood that the example quenching elements Q ₁ through Q _N can be implemented using either passive or active quenching elements in accordance with the teachings of the present invention.

As shown in the example, there are N SPADs, N quenching elements, and N counter circuits (e.g., counter circuits 1 through N). In the depicted example, counter circuits 1 through N are implemented using CMOS circuits fabricated using a standard CMOS process using a stacked chip system, disposed on a bottom wafer 200', and are electrically coupled to receive output pulses 204 generated by the respective SPADs in response to received photons included in incident light. Counter circuits 1 through N can be enabled to count the number of output pulses 204 generated by each respective SPAD during a time window and output a digital signal 206 representing the count. While the example depicted in FIG2 illustrates a direct connection between the pixel circuit and the counter circuit, any connection between the pixel circuit and the counter circuit (including via AC coupling) may be used in accordance with the present teachings. Furthermore, any known SPAD bias polarity and/or orientation may be implemented. In one example, each counter circuit includes an amplifier to amplify the received output pulses 204. Alternatively, or in addition to the counter circuits, a timing circuit may be placed in each pixel/column/array to determine the arrival time of the incident photons.

In the illustrated example, each SPAD ₁ to SPAD _N is reverse biased by a bias voltage V _BIAS that is higher than the breakdown voltage of each SPAD ₁ to SPAD _N. In response to a single photogenerated carrier from incident light, an avalanche multiplication process is triggered that causes an avalanche current at the output of each SPAD ₁ to SPAD _N. This avalanche current self-quenches in response to the voltage drop generated across the quenching element (e.g., Q ₁ to Q _N ), which causes the bias voltage across the SPAD to drop. After quenching the avalanche current, the voltage across the SPAD recovers to above the bias voltage, and the SPAD is then ready to be triggered again. The generated output pulse 204 of each SPAD ₁ to SPAD _N is received by the corresponding counter circuit 1 to N, which increments its count in response to the output pulse 204.

Conventional SPAD designs that incorporate SPADs on the same chip as a CMOS digital counter fabricated using a standard CMOS process are constrained by a reduced fill factor at the imaging plane due to the area occupied by the CMOS circuitry itself. Thus, one advantage of implementing a stacked chip structure in accordance with the teachings of the present invention is that, in accordance with the teachings of the present invention, with the SPADs on the top chip and the CMOS circuitry on a separate bottom chip, there is no need to reduce the fill factor of the SPAD imaging array on the top chip in order to provide space to accommodate the CMOS circuitry on the same chip.

It should be noted that the circuit diagram of FIG2 is provided here for explanatory purposes, and some circuit elements, such as passive components (e.g., resistors and capacitors) and active components (e.g., transistors), are not shown in detail so as not to obscure the teachings of the present invention. For example, the illustrated pixel circuit of FIG2 may generate an output pulse that requires amplification before being sensed by the input of a digital counter. In another example, the connection at the node between quenching element _Q1 and SPAD ₁ will be at a high voltage, which may require AC coupling.

FIG3 is a cross-sectional view of an example of a portion of a semiconductor device wafer 300 of a stacked chip system 302 in accordance with the teachings of the present invention. It should be understood that the stacked chip system 302 and semiconductor device wafer 300 of FIG3 can be an example of an implementation of the stacked chip system 102 and semiconductor device wafer 100 of FIG1 and/or the stacked chip system 202 and semiconductor device wafer 200 of FIG2 , and that similarly named and numbered elements referenced below are coupled and function similarly as described above. Thus, in one example, the semiconductor device wafer 300 of FIG3 is stacked with another semiconductor device wafer including, for example, readout circuitry, and the semiconductor device wafer 300 and the other semiconductor device wafer including, for example, readout circuitry are coupled together in the stacked chip system. It should also be noted that various circuit elements of the stacked chip system 202 shown in FIG2 (e.g., the example quenching elements _Q1 through _QN and/or counter circuits 1 through N of FIG2 ) are not shown in detail in FIG3 so as not to obscure the teachings of the present invention.

Returning to the example depicted in FIG3 , the example photon detector 308 is illustrated as including a SPAD 310 disposed in a SPAD region 328 of a semiconductor device wafer 300. As shown, the SPAD 310 is disposed proximate to the front side 324 of a semiconductor layer 318 of the semiconductor device wafer 300 of the stacked chip system 302. In one example, the semiconductor layer 318 comprises a thinned silicon layer. The SPAD 310 includes a multiplication junction 316 defined in the semiconductor layer 318 at the interface between the n-doped layer 314 and the p-doped layer 312 of the SPAD 310. In the example, the multiplication junction 316 is reverse biased above the breakdown voltage, so that light 344 (which is guided into the SPAD 310 through the back side 322 of the semiconductor layer 318) triggers an avalanche multiplication process in the multiplication junction 316. In one example, the light 344 comprises infrared or near-infrared light.

3 also shows a guard ring 320 disposed in a guard ring region 326 of the semiconductor device wafer 300. As shown, the guard ring 320 is disposed proximate to the SPAD 310 in the first semiconductor layer 318 and surrounds the SPAD 310 to isolate the SPAD 310 in the semiconductor layer 318. In the example, the guard ring 320 extends through the semiconductor layer 318 from the front side 324 to the back side 322.

3 also shows that guard region reflective structure 330 is disposed below or proximate to guard ring 320 in guard region 326. As shown in the example, guard region reflective structure 330 is disposed proximate to front side 324 of semiconductor layer 318, in accordance with the teachings of the present invention, so that light 346, which bypasses SPAD 310 and is directed into guard region 326 through back side 322 of semiconductor layer 318, is redirected by guard region reflective structure 330 back into semiconductor layer 318 and into SPAD 310. In one example, light 346 includes infrared or near-infrared light.

3 shows the presence of a SPAD region reflective structure 332 disposed below or proximate to SPAD 310 in SPAD region 328. As shown in the example, SPAD region reflective structure 332 is proximate to front side 324 of semiconductor layer 318 such that light 344 that is directed into semiconductor layer 318 through back side 322 of semiconductor layer 318 and passes through SPAD 310 without being absorbed is reflected by SPAD region reflective structure 332 back into semiconductor layer 318 and back into SPAD 310 in accordance with the teachings of the present invention.

As shown in the depicted example, guard ring reflective structure 330 and SPAD region reflective structure 332 are implemented using metal layers M1, M2, M3, and M4 in oxide material 334 of semiconductor device wafer 300 near front side 324 of semiconductor layer 318. Specifically, the example shows guard ring reflective structure 330 implemented using multiple metal layers M1, M2, and M3 to redirect light 346 received in guard ring region 326 back into semiconductor layer 318 and back into SPAD 310. It should be understood that in other examples, guard ring reflective structure 330 may include a greater or lesser number of metal layers M1, M2, M3, and M4, as long as light 346 received in guard ring region 326 that bypasses SPAD 310 is redirected back into semiconductor layer 318 and back into SPAD 310, in accordance with the teachings of the present invention. 3 also shows that the SPAD region reflective structure 332 is implemented using one metal layer M4 in the oxide material 334 of the semiconductor device wafer 300 near the front side 324 of the semiconductor layer 318. Thus, the SPAD region reflective structure 332 redirects light 344 that has propagated through the SPAD 310 without being absorbed back into the semiconductor layer 318 and into the SPAD 310.

3 , in accordance with the teachings of the present invention, the guard region reflective structure 330 is not coplanar with the SPAD region reflective structure 332 so that light 344 (entering the SPAD region 328) and light 346 (entering the guard region 326) are redirected into the SPAD 310. For example, as shown in the illustrated example, the plurality of metal layers M1, M2, and M3 of the guard region reflective structure 330 are arranged in an inverted (e.g., right-side-up, depending on one's perspective) flat-topped pyramid shape within the oxide material 334. In the example, the metal layer M4 of the SPAD region reflective structure 332 is the "top" of the pyramidal structure, while the sides of the pyramidal structure form the guard region reflective structure 330. Of course, it should be understood that according to the teachings of the present invention, other suitable non-coplanar three-dimensional structures (for example, dome structures or similar structures) can be formed in the metal layers M1, M2, M3, M4, etc. of the semiconductor chip 300 to implement the ring area reflection structure 330 and the SPAD area reflection structure 332 to redirect light 346 and light 344.

FIG4 is a bottom/top view of one example of a guard ring region reflective structure 430 plus an example SPAD region reflective structure 432 included in a metal layer of a semiconductor device wafer of a stacked chip system in accordance with the teachings of the present invention. It should be understood that the guard ring region reflective structure 430 plus the example SPAD region reflective structure 432 of FIG4 can be one example of the guard ring region reflective structure 330 plus the example SPAD region reflective structure 332 of FIG3 , and that similarly named and numbered elements referenced below couple and function similarly as described above.

As shown in the depicted example, the SPAD region reflective structure 432 of FIG4 is implemented using a single metal layer M4, and the guard ring region reflective structure 430 is implemented using multiple metal layers M1, M2, and M3. In this example, the multiple metal layers M1, M2, M3, and M4 are disposed in oxide material 434 proximate to the semiconductor layer containing the SPAD. In this example, the SPAD region reflective structure 432 is disposed in the SPAD region directly below the SPAD to redirect any light that passes through the SPAD without being absorbed back into the SPAD. In this example, the guard ring region reflective structure 430 is disposed in the guard ring region surrounding the SPAD to redirect light that bypasses the SPAD and enters the guard ring region surrounding the SPAD back into the SPAD in accordance with the teachings of the present invention.

FIG5 is a block diagram showing one example of a stacked-chip integrated circuit imaging sensor system 502 in accordance with the teachings of the present invention. It should be understood that the stacked-chip system 502 of FIG5 can be one example of an implementation of the stacked-chip system 102 of FIG1 and/or the stacked-chip system 202 of FIG2 and/or the stacked-chip system 302 of FIG3, and that similarly named and numbered elements referenced below are coupled and function similarly as described above. As shown in the example depicted in FIG5, the stacked-chip integrated circuit imaging sensor system 502 includes a pixel array 536 coupled to control circuitry 542 and readout circuitry 538, which is coupled to function logic 540.

In one example, pixel array 536 is a two-dimensional (2D) array of pixel cells (e.g., pixel cells P1, P2, ..., Pn). In one example, each pixel cell includes a photon detector having a SPAD surrounded by a guard having a guard region reflector structure, as discussed above. For example, pixel cells P1, P2, ..., Pn in pixel array 536 may be examples of PIXEL ₁ , PIXEL ₂ , ..., PIXEL _N in FIG. 2 , and similarly named and numbered elements referenced below are coupled and function similarly as described above. As illustrated, each pixel cell is arranged in rows (e.g., rows R1 to Ry) and columns (e.g., columns C1 to Cx) to acquire image data of a person, place, object, etc., which can then be used to render a 2D image of the person, place, object, etc. In another example, pixel array 536 can also be used in a time-sequential mode to provide a "time image" of a scene, which can be used for distance information in time-of-flight applications or fluorescence lifetime for user medical applications.

The output pulses generated by the SPADs of the pixel array 536 are read out by the high readout circuit 538 and passed to the function logic 540. In one example, the readout circuit 538 includes at least one counter circuit for each of the SPADs in the pixel array 536 and may also include an amplification circuit and/or a quenching circuit. The function logic 540 may simply store the image data in memory or even manipulate the image data by applying post-image effects (e.g., cropping, rotating, adjusting brightness, adjusting contrast, or other). The control circuit 542 is coupled to the pixel array 536 and/or the readout circuit 538 to control the operational pixel array 536. For example, the control circuit 542 may simultaneously enable each of the counter circuits included in the readout circuit 538 within a time window to implement a global shutter operation. Thus, the examples of the SPAD stacked chip image sensors discussed herein provide high-speed and low-light-sensitivity imaging, which is typically not achievable using conventional sensor architectures.

In one example, imaging sensor system 502 illustrated in FIG5 can be implemented in a stacked chip approach. For example, in accordance with the teachings of the present invention, in one example, pixel array 536 can be included in a pixel die, while readout circuitry 538, function logic 540, and control circuitry 542 can be included in a separate ASIC die, as illustrated in FIG5. In this example, the pixel die and the ASIC die are stacked and coupled together during manufacturing to implement an imaging sensor system in accordance with the teachings of the present invention.

The above description of the illustrated examples of the present invention (including what is described in the Abstract) is not intended to be exhaustive or to limit the present invention to the precise forms disclosed. Although specific embodiments and examples of the present invention are described herein for illustrative purposes, various equivalent modifications are possible without departing from the broader spirit and scope of the present invention.

These modifications may be made to examples of the present invention in light of the above detailed description. The terms used in the appended claims should not be construed to limit the invention to the specific embodiments disclosed in the specification and claims. Rather, the scope is to be determined entirely by the appended claims, which are to be construed according to established rules of claim interpretation. The specification and drawings are accordingly to be regarded as illustrative rather than restrictive.

Claims (18)

1. A photon detector, comprising: A single-photon avalanche diode (SPAD) is disposed close to the front side of a first semiconductor layer, wherein the SPAD contains a multiplication junction defined in the first semiconductor layer at the interface between an n-doped layer and a p-doped layer of the SPAD, wherein the multiplication junction is reverse biased above a breakdown voltage such that light guided into the SPAD through the back side of the first semiconductor layer triggers an avalanche multiplication process in the multiplication junction. A guard ring is disposed close to the SPAD in a guard ring region in the first semiconductor layer, wherein the guard ring surrounds the SPAD to isolate the SPAD in the first semiconductor layer; A reflective structure in the guard ring region, positioned close to the guard ring and close to the front side of the first semiconductor layer, such that light that bypasses the SPAD and is guided through the back side of the first semiconductor layer into the guard ring region is redirected by the reflective structure back into the first semiconductor layer and into the SPAD; and SPAD region reflective structure, wherein the SPAD region reflective structure is disposed close to the SPAD and close to the front side of the first semiconductor layer, such that light passing through the SPAD is guided through the back side of the first semiconductor layer into the first semiconductor layer and reflected back by the SPAD region reflective structure into the first semiconductor layer and back into the SPAD, wherein the guard ring region reflective structure is not coplanar with the SPAD region reflective structure. 2. The photon detector according to claim 1, wherein the protective ring region reflective structure comprises a plurality of metal layers disposed in an oxide material disposed near the front side of the first semiconductor layer. 3. The photon detector of claim 2, wherein the SPAD region reflective structure is comprised of one of the plurality of metal layers disposed in the oxide material disposed near the front side of the first semiconductor layer. 4. The photon detector of claim 3, wherein the plurality of metal layers of the reflective structure in the guard ring region are arranged in a flat-topped pyramid shape in the oxide material disposed near the front side of the first semiconductor layer. 5. The photon detector according to claim 3, wherein the protective ring region reflective structure is included in a first, second, and third of the plurality of metal layers, and wherein the SPAD region reflective structure is included in a fourth of the plurality of metal layers. 6. The photon detector of claim 1, wherein the first semiconductor layer comprises thinned silicon. 7. The photon detector of claim 1, wherein the light comprises near-infrared light. 8. The photon detector of claim 1, wherein the first semiconductor layer is contained in a first semiconductor device wafer, wherein the first semiconductor device wafer is stacked with a second semiconductor device wafer containing readout circuitry, and wherein the first and second semiconductor device wafers are coupled together in a stacked chip system. 9. An imaging sensor system comprising: A pixel array having a plurality of pixel units disposed in a first semiconductor layer, wherein each of the plurality of pixel units comprises: A single-photon avalanche diode (SPAD) is disposed close to the front side of a first semiconductor layer, wherein the SPAD contains a multiplication junction defined in the first semiconductor layer at the interface between an n-doped layer and a p-doped layer of the SPAD, wherein the multiplication junction is reverse biased above a breakdown voltage such that light guided into the SPAD through the back side of the first semiconductor layer triggers an avalanche multiplication process in the multiplication junction. A guard ring is disposed close to the SPAD in a guard ring region in the first semiconductor layer, wherein the guard ring surrounds the SPAD to isolate the SPAD in the first semiconductor layer; A reflective structure in the guard ring region, positioned close to the guard ring and close to the front side of the first semiconductor layer, such that light that bypasses the SPAD and is guided through the back side of the first semiconductor layer into the guard ring region is redirected by the reflective structure back into the first semiconductor layer and into the SPAD; and SPAD region reflective structure, wherein the SPAD region reflective structure is disposed close to the SPAD and close to the front side of the first semiconductor layer, such that light passing through the SPAD and guided into the first semiconductor layer through the back side of the first semiconductor layer is reflected back into the first semiconductor layer and reflected into the SPAD by the SPAD region reflective structure, wherein the guard ring region reflective structure and the SPAD region reflective structure are not coplanar. Control circuitry coupled to the pixel array to control the operation of the pixel array; and A readout circuit is coupled to the pixel array to read out image data from the plurality of pixel units. 10. The imaging sensor system of claim 9, further comprising functional logic coupled to the readout circuit for storing image data read from the plurality of pixel units. 11. The imaging sensor system of claim 9, wherein the readout circuitry includes a plurality of counter circuits electrically coupled to the pixel array, wherein each of the plurality of counter circuits is coupled to count output pulses generated by a corresponding one of the plurality of pixel units. 12. The imaging sensor system of claim 11, wherein the first semiconductor layer is contained in a first semiconductor device wafer, and wherein the readout circuit is contained in a second semiconductor layer, the second semiconductor layer being contained in a second semiconductor device wafer, wherein the first semiconductor device wafer is stacked with and coupled to the second semiconductor device wafer in a stacked chip system. 13. The imaging sensor system of claim 9, wherein the reflective structure of the protective ring region is comprised of a plurality of metal layers disposed in an oxide material disposed near the front side of the first semiconductor layer. 14. The imaging sensor system of claim 13, wherein the SPAD region reflective structure is comprised of one of a plurality of metal layers disposed in an oxide material disposed near the front side of the first semiconductor layer. 15. The imaging sensor system of claim 14, wherein the plurality of metal layers of the reflective structure in the protective ring region are arranged in a flat-topped pyramid shape in the oxide material disposed near the front side of the first semiconductor layer. 16. The imaging sensor system of claim 14, wherein the protective ring region reflective structure is included in a first, second, and third of the plurality of metal layers, and wherein the SPAD region reflective structure is included in a fourth of the plurality of metal layers. 17. The imaging sensor system of claim 9, wherein the first semiconductor layer comprises thinned silicon. 18. The imaging sensor system of claim 9, wherein the light comprises near-infrared light.