HK1206150B - Image sensor and method of operating the same - Google Patents

Abstract

The invention relates to an image sensor and a method of operating the same. An image sensor includes a pixel array including a plurality of pixel cells each including a floating diffusion node, a photosensitive element coupled to selectively transfer image charge to the floating diffusion node, and a feedback coupling capacitor coupled between the floating diffusion node and an output line. A bit line is coupled to selectively readout image data output from each one of a group of the plurality of pixel cells. An integrator is capacitively coupled to the bit line. The integrator is coupled to output an output signal on the output line in response to the image data. The output signal on the output line is capacitively coupled to the floating diffusion node through the feedback coupling capacitor to suppress a potential swing at the floating diffusion node of each one of the group of the plurality of pixel cells in response to the output signal.

Description

Image sensor and method of operating the same

Technical Field

The present invention generally relates to image sensors. More particularly, embodiments of the invention relate to circuits that read out image data from image sensor pixel cells with low supply voltages.

Background

Image sensors have become ubiquitous. They are widely used in digital cameras, cellular phones, security cameras, as well as medical, automotive and other applications. The technology used to fabricate image sensors, and in particular, metal oxide semiconductor ("CMOS") image sensors, has continued to advance rapidly. For example, the demand for higher resolution and lower power consumption has facilitated further miniaturization and integration of these image sensors.

In a conventional CMOS active pixel sensor, image charge is transferred from a photosensitive device (e.g., a photodiode) and converted to a voltage signal within the pixel cell on a floating diffusion node. When the potential at the floating diffusion is higher than the pinned voltage of the photosensitive device (e.g.,V_PIN) When the image charge is transferred from the photosensitive device to the floating diffusion efficiently. The sum of the floating diffusion voltage swing and the pinning voltage typically limits the supply voltage of the active pixel sensor to a minimum of 2.5 volts to 3 volts. However, as the need for further miniaturization of active pixel sensors increases, there is a continuing need for active pixel sensors having supply voltages of less than 2.5 volts to 3 volts.

Disclosure of Invention

In one embodiment, the present application provides an image sensor comprising: a pixel array comprising a plurality of pixel cells, wherein each of the plurality of pixel cells comprises: a floating diffusion node; a photosensitive element coupled to selectively transfer image charge to the floating diffusion node; and a feedback coupling capacitor coupled between the floating diffusion node and an output line; a bit line coupled to selectively read out image data output from each of the groups of the plurality of pixel cells; and an integrator capacitively coupled to the bit line, wherein the integrator is coupled to output an output signal on the output line in response to the image data, wherein the output signal on the output line is capacitively coupled to the floating diffusion node through the feedback coupling capacitor to suppress potential swings at the floating diffusion node for each of the group of the plurality of pixel cells in response to the output signal.

In another embodiment, the present application provides an imaging system comprising: a pixel array comprising a plurality of pixel cells, wherein each of the plurality of pixel cells comprises: a floating diffusion ("FD") node; a photosensitive element coupled to selectively transfer image charge to the floating diffusion node; and a feedback coupling capacitor coupled between the floating diffusion node and an output line; control circuitry coupled to the pixel array to control operation of the pixel array; and readout circuitry including an integrator capacitively coupled to a bit line to selectively readout image data output from each of a group of the plurality of pixel cells, wherein the integrator is coupled to output an output signal on the output line in response to the image data, wherein the output signal on the output line is capacitively coupled to the floating diffusion node through the feedback coupling capacitor to suppress potential swing at the floating diffusion node for each of the group of the plurality of pixel cells in response to the output signal.

In yet another embodiment, the present application provides a method of operating an image sensor, the method comprising: resetting a photosensitive element and a floating diffusion node in an image sensor pixel cell; accumulating image charge in the photosensitive element; transferring the image charge from the photosensitive element to the floating diffusion node; generating image data on a bit line in response to the image charge at the floating diffusion node; integrating the image data on the bit lines with an integrator in response to the image data to produce an output signal on an output line of the integrator; and suppressing potential swing at the floating diffusion node with capacitive feedback coupling between the output line and the floating diffusion node.

Drawings

Non-limiting and non-exhaustive embodiments of the present invention are described with reference to the following figures, wherein like reference numerals refer to like parts throughout the various views unless otherwise specified.

Figure 1 is a schematic diagram illustrating one example of an image sensor having a readout architecture that suppresses potential swing at a floating diffusion node, according to the teachings of this disclosure.

Figure 2 is a block diagram illustrating an example imaging system including a readout architecture that suppresses potential swings at floating diffusion nodes of pixel cells in a pixel array, according to the teachings of this disclosure.

Figure 3 illustrates a timing diagram of signals in an exemplary readout architecture that suppresses potential swings at floating diffusion nodes of a pixel array, according to the teachings of this disclosure.

Corresponding reference characters indicate corresponding components throughout the several views. Skilled artisans will appreciate that elements in the figures are illustrated for simplicity and clarity and have not necessarily been drawn to scale. For example, the dimensions of some of the elements in the figures may be exaggerated relative to other elements to help improve understanding of various embodiments of the present invention. Also, common but well-understood elements that are useful or necessary in a commercially feasible embodiment are often not depicted in order to facilitate a less obstructed view of these various embodiments of the present invention.

Detailed Description

In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present invention. However, it will be apparent to one skilled in the art that the specific details need not be used to practice the invention. In other instances, well-known materials or methods have not been described in detail in order to avoid obscuring the present invention.

Reference throughout this specification to "one embodiment," "an embodiment," "one example," or "an example" means that a particular feature, structure, or characteristic described in connection with the embodiment or example is included in at least one embodiment of the present invention. Thus, appearances of the phrases "in one embodiment," "in an embodiment," "one example" or "an example" in various places throughout this specification are not necessarily all referring to the same embodiment or example. Furthermore, the particular features, structures, or characteristics may be combined in any suitable combination and/or sub-combination in one or more embodiments or examples. The particular features, structures, or characteristics may be included in integrated circuits, electronic circuits, combinational logic circuits, or other suitable components that provide the described functionality. Additionally, it should be understood that the drawings provided herein are for explanation purposes to persons skilled in the art and that the drawings are not necessarily drawn to scale.

An example in accordance with the teachings of this disclosure describes a readout architecture that suppresses potential swing at a floating diffusion node of a pixel array in accordance with the teachings of this disclosure. As will be shown, in various examples, the column-level integrator is coupled to integral image data that is output from each pixel cell on a bitline. In one example, according to the teachings of this disclosure, the integrator drives a positive voltage step on the output of the integrator in response to the downward potential at the floating diffusion node, which thus supplies supply charge to the floating diffusion node through a feedback capacitor. In one example, the charge supplied from the output of the integrator through the feedback capacitor helps to maintain a substantially constant voltage on the floating diffusion node, which is greater than the voltage on the photosensitive element. According to the teachings of this disclosure, by suppressing the voltage swing to maintain a substantially constant voltage on the floating diffusion node, the pixel can therefore operate at a lower supply voltage.

To illustrate, FIG. 1 is a schematic diagram illustrating one example of an image sensor 100 having a readout architecture that suppresses potential swing at a floating diffusion node, according to the teachings of this disclosure. In the depicted example, image sensor 100 includes a plurality of pixel cells 102 arranged in a pixel array. In the depicted example, pixel cell 102 is illustrated as a four transistor (4T) pixel cell. It should be appreciated that pixel cell 100 is one possible example of a pixel circuit architecture for implementing each pixel cell within image sensor 100. However, it should be understood that other examples in accordance with the teachings of this disclosure are not necessarily limited to 4T pixel architectures. Persons of ordinary skill in the art having benefit of the present disclosure will appreciate that the present teachings also apply to 3T designs, 5T designs, and other pixel architectures according to the teachings of the present disclosure.

In the example depicted in FIG. 1, pixel cell 102 includes: a photosensitive element, which may also be referred to as a Photodiode (PD)104 to accumulate image charge; a transfer transistor T1106; a reset transistor T2108; a Floating Diffusion (FD) node 110; an amplifier transistor, illustrated as a Source Follower (SF) transistor T3112; and a row select transistor T4114. Feedback coupling capacitor C_FB116 are capacitively coupled between the floating diffusion node FD110 and the output line 120. During operation, transfer transistor T1106 receives a transfer signal TX that selectively transfers image charge accumulated in photosensitive element PD104 to floating diffusion FD node 110.

As shown in the illustrated example, a reset transistor T2108 is coupled between a supply voltage AVDD and the floating diffusion node FD110 to reset a level in the pixel cell 102 in response to a reset signal RST (e.g., to discharge or charge the floating diffusion node FD110 and the photosensitive element PD104 to a preset voltage). Floating diffusion node FD110 is coupled to control the gate of amplifier transistor SF T3112. The amplifier transistor SF T3112 is coupled between a supply voltage AVDD and a row select transistor RST 4114. The amplifier transistor SF T3112 operates as a source follower amplifier, thereby providing a high impedance connection to the floating diffusion node FD 110. The row select transistor RS T4114 selectively couples the image data output of the pixel cell 102 to the readout column bit line 118 in response to a row select signal RS. In the illustrated example, bit lines 118 are coupled to selectively read out image data from columns of a plurality of pixel cells 102 in image sensor 100.

The example depicted in FIG. 1 also illustrates an integrator 122 at the column level, which passes through an input coupling capacitor C_IN126 are selectively coupled to the bit lines 118 as shown. As shown in the example, the output of the integrator 122 is coupled to the output line 120, the output line 120 passing through a feedback coupling capacitor C_FB116 are capacitively coupled to the floating diffusion node FD 110. In the illustrated example, with input coupling capacitor C_INThe capacitive coupling provided by 126 supports different DC voltage levels between the input of the integrator 122 and the bit line 118 while allowing AC signals or high frequency signals to be on the bit line 118 and the bit line 118The input of integrator 122. Similarly, by means of a feedback coupling capacitor C_FBThe capacitive coupling provided by 116 supports different DC voltage levels between floating diffusive node FD110 and output line 120 while allowing AC signals or high frequency signals to pass between floating diffusive node FD110 and output line 120.

In one example, a current source 130 having a high internal impedance is coupled to the bit line 118 to sink current to ground, as shown. In the example, a RESET switch 128 is also coupled to the integrator 122, as shown, which is coupled to a RESET level of the integrator 122 in response to a RESET _ AMP signal, as shown. In the illustrated example, the integrator 122 includes an operational amplifier 124 coupled as an integrator. Thus, the inverting input of the operational amplifier 124 is coupled to the input coupling capacitor C_IN126 and the non-inverting input of operational amplifier 124 is coupled to ground as shown. In one example, the operational amplifier 124 may be implemented as a single-branch common-source amplifier to reduce die size and power consumption.

In operation, integrator 122 is coupled in response to passing through input coupling capacitor C_IN126 output an output signal on output line 120 from the integration of the image data received on bit line 118. As shown in the example depicted in fig. 1, through a feedback coupling capacitor C_FB116 feed back the output signal on output line 120 to pixel cell 102. Specifically, in one example, the operational amplifier 124 of the integrator 122 drives a positive voltage step on the output line 120 in response to the downward potential at the floating diffusion node FD110, which passes through the feedback coupling capacitor C_FB116 supply charge to floating diffusion node FD 110. Thus, the open loop gain of operational amplifier 124 is used to suppress the downward voltage swing on floating diffusion node FD110 due to the transfer of image charge from photosensitive element PD to floating diffusion node FD 110. In other words, according to the teachings of this disclosure, the open loop gain of the operational amplifier 124 is coupled to drive a positive voltage level on the output line 120 in response to transferring image charge from the photosensitive element FD104 to the floating diffusion node FD110Jump over to couple capacitor C through feedback_FB116 supply charge to floating diffusion node FD110, maintaining a substantially constant voltage at floating diffusion node FD110 above the voltage at photosensitive element FD 104. Thus, in one example, a lower supply voltage may be used for AVDD, such as about 1.8 volts, in accordance with the teachings of this disclosure, as the voltage at floating diffusion node FD110 is maintained at a substantially constant voltage with integrator 122 as shown.

In one example, the output signal on output line 120 is also coupled to be converted from analog to digital with a/D converter 132. In one example, the output signal level on output line 120 is also coupled to be sampled and held with sample and hold circuit 134 as shown. In one example, as discussed in more detail below, the output value from the pixel cell 102 may be determined by taking the difference between the sampled output level value of the output signal after transferring the image charge to the floating diffusion node FD110 and the sampled output level of the output signal after reset.

Figure 2 is a block diagram illustrating an example imaging system 200 including a readout architecture that suppresses potential swings at floating diffusion nodes of pixel cells in a pixel array, according to the teachings of this disclosure. As shown in the depicted example, the imaging system 200 includes a pixel array 202 coupled to control circuitry 238 and readout circuitry 236, the readout circuitry 236 coupled to functional logic 240.

In one example, pixel array 202 is a two-dimensional (2D) array of imaging sensors or pixel cells (e.g., pixel cells P1, P2 … Pn). In one example, each pixel cell is a CMOS imaging pixel. It should be noted that pixel cells P1, P2 … Pn in pixel array 202 may be examples of pixel cell 102 of FIG. 1, and similarly named and numbered elements referenced below are similarly coupled and function as described above. As illustrated, each pixel cell is arranged into rows (e.g., rows R1-Ry) and columns (e.g., columns C1-Cx) to acquire image data of a person, place, object, etc., which can then be used to render a 2D image of the person, place, object, etc.

In one example, after each pixel cell has accumulated its image data or image charge, the image data is read out by readout circuitry 236 through readout column bit lines 218 and then transferred to functional logic 240. In one example, readout circuitry 236 may include an integrator coupled to each column C1-Cx that provides feedback through output line 220, as shown. It should be noted that the integrator coupled to each column C1-Cx and each of output lines 220 may be an example of integrator 122 and output line 120 of fig. 1. Referring back to fig. 2, in various examples, readout circuitry 236 may also include additional amplification circuitry, additional analog-to-digital (ADC) conversion circuitry, or other circuitry. Function logic 240 may simply store the image data or even manipulate the image data by applying a post-image effect (e.g., crop, rotate, remove red-eye, adjust brightness, adjust contrast, or otherwise). In one example, readout circuitry 236 may readout a row of image data at a time along readout column bit lines 218 (illustrated), or may readout the image data using a variety of other techniques (not illustrated), such as a serial readout of all pixels or a simultaneous full parallel readout.

In one example, control circuitry 238 is coupled to pixel array 202 to control operating characteristics of pixel array 202. For example, the control circuit 238 may generate a shutter signal for controlling image acquisition. In one example, the shutter signal is a global shutter signal for simultaneously enabling all pixels within pixel array 202 to simultaneously capture their respective image data during a single acquisition window. In another example, the shutter signal is a rolling shutter signal such that each row, column, or group of pixels is sequentially enabled during successive acquisition windows.

Figure 3 illustrates a timing diagram of signals in an exemplary readout architecture that suppresses potential swings at floating diffusion nodes of a pixel array, according to the teachings of this disclosure. It should be understood that the example signals illustrated in FIG. 3 illustrate various waveforms of signals associated with the example image sensor 100 shown in FIG. 1, and that similarly named and numbered elements below are coupled and function as described above. As shown in the example, the reset occurs at time T0. In the example depicted in fig. 3, the row select signal RS314, the RESET signal RST308, and the RESET integrator signal RESET _ AMP328 are asserted during the RESET. Thus, the floating diffusion node voltage or potential 310 is set to a voltage near the supply voltage AVDD, or the voltage or potential on the output line 320 is set to a voltage near ground, as shown. In one example, it should be noted that photosensitive device PD104 may be reset separately prior to time T0 by asserting both reset signal RST308 and transmission signal TX306 to reset the image charge level in the photosensitive elements (not shown).

In one example, after the RESET at T0 is complete, the RESET signal RST308, the RESET integrator signal RESET _ AMP328, and the transmission signal TX306 are deasserted. The voltage at the floating diffusion potential 310 and the potential on the output line 320 have been reset as shown. At this point, in one example, an analog-to-digital operation 332 may occur, and a first sample of the level at output line 320 may be obtained with sample and hold circuit 134. In the illustrated example, the first sample is indicated with a SHR334A event, the SHR334A event indicating that the first sample of the output signal level at the output line has been obtained after reset. During this time, the transfer signal TX306 is de-asserted and the photosensitive device PD104 may also accumulate image charge.

At time T1, transfer signal TX306 is then asserted and the image charge accumulated in photosensitive device PD104 is then transferred to floating diffusion node FD 110. In the case of transferring image charge to floating diffusion node FD110, as shown in FD potential 310, the potential on floating diffusion node FD110 begins to swing downward at time T1. However, the downward swing that begins to occur in FD potential 310 at time T1 is passed through bit line 118 and input capacitor C by integrator 122_IN126, which causes the output signal on output line 320 to rise, as shown. As a result, the integrator 122 drives a positive voltage step on the output line 120, which is through the feedback coupling capacitor C_FB116 supply charge to the floating diffusion node FD110,this suppresses the downward voltage swing on floating diffusion node FD 110. Thus, the open loop gain of operational amplifier 124 is coupled to maintain a substantially constant voltage at floating diffusion node FD110, as shown.

During this time, after the transfer signal TX306 has been de-asserted, another analog-to-digital operation 332 may occur and a second sampling of the output line 320 may be made with the sample and hold circuit 134. In the illustrated example, the second sample is indicated with a SHS334B event, which indicates that a second sample of the output signal value on output line 320 has been obtained. In one example, the output value of the pixel may be derived by finding the difference between the second sample and the first sample (i.e., output value = SHS-SHR).

The above description of illustrated examples of the invention, including what is described in the abstract, is not intended to be exhaustive or to be limited to the precise forms disclosed. While specific embodiments of, and examples for, the invention are described herein for illustrative purposes, various equivalent modifications are possible without departing from the broader spirit and scope of the invention.

These modifications can be made to the examples of the invention in light of the above detailed description. The terms used in the following claims should not be construed to limit the invention to the specific embodiments disclosed in the specification and the claims. Rather, the scope is to be determined entirely by the following claims, which are to be construed in accordance with established doctrines of claim interpretation. The specification and drawings are, accordingly, to be regarded in an illustrative rather than a restrictive sense.

Claims (24)

1. An image sensor, comprising:

a pixel array comprising a plurality of pixel cells, wherein each of the plurality of pixel cells comprises:

a floating diffusion node;

a photosensitive element coupled to selectively transfer image charge to the floating diffusion node; and

a feedback coupling capacitor coupled between the floating diffusion node and an output line;

a bit line coupled to selectively read out image data output from each of the groups of the plurality of pixel cells; and

an integrator capacitively coupled to the bit lines, wherein the integrator is coupled to output an output signal on the output lines in response to the image data, wherein the output signal on the output line is capacitively coupled to the floating diffusion node through the feedback coupling capacitor, to inhibit potential swings at the floating diffusion node for each of the groups of the plurality of pixel cells in response to the output signal, wherein the integrator comprises an operational amplifier coupled as an integrator, and wherein a first input of the integrator comprises an inverting input of the operational amplifier, wherein an open loop gain of the operational amplifier is coupled to drive a positive voltage step on the output line to supply charge to the floating diffusion node through a feedback capacitor, maintaining the voltage at the floating diffusion node above the voltage at the photosensitive element.

2. The image sensor of claim 1, wherein the group of the plurality of pixel cells includes columns of the pixel array.

3. The image sensor of claim 1, further comprising an input coupling capacitor coupled between a first input of the integrator and the bit line such that the bit line is capacitively coupled to the first input of the integrator.

4. The image sensor of claim 3, wherein the input coupling capacitor is coupled to support different DC voltage levels between the bit line and the first input of the integrator.

5. The image sensor of claim 1, further comprising a current source coupled between the inverting input of the operational amplifier and a ground terminal, wherein the current source is coupled to sink current to the ground terminal.

6. The image sensor of claim 1, further comprising an analog-to-digital converter coupled to the output line to generate a digital signal in response to an analog signal on the output line.

7. The image sensor of claim 1, further comprising a sample and hold circuit coupled to the output line to sample and hold the output signal on the output line.

8. The image sensor of claim 7, wherein the sample and hold circuit is coupled to output a first sample of the output line after reset, and wherein the sample and hold circuit is further coupled to output a second sample of the output line in response to the image data, wherein an output value of each of the plurality of pixel cells is responsive to a difference between the second sample and the first sample.

9. The image sensor of claim 1, wherein each of the plurality of pixel cells further includes a reset transistor coupled between the floating diffusion node and a supply voltage to selectively reset the image charge in the floating diffusion node and the photosensitive element.

10. The image sensor of claim 1, wherein each of the plurality of pixel cells further includes a transfer transistor coupled between the photosensitive element and the floating diffusion node to selectively transfer the image charge from the photosensitive element to the floating diffusion node.

11. The image sensor of claim 1, wherein each of the plurality of pixel cells further includes an amplifier coupled to the floating diffusion node to generate the image data in response to the image charge at the floating diffusion node.

12. The image sensor of claim 11, wherein each of the plurality of pixel cells further includes a select transistor coupled between the amplifier and the bit line to selectively transfer the image data from the amplifier to the bit line.

13. An imaging system, comprising:

a pixel array comprising a plurality of pixel cells, wherein each of the plurality of pixel cells comprises:

a floating diffusion "FD" node;

a photosensitive element coupled to selectively transfer image charge to the floating diffusion node; and

a feedback coupling capacitor coupled between the floating diffusion node and an output line;

control circuitry coupled to the pixel array to control operation of the pixel array; and

readout circuitry including an integrator coupled to a bit line via an input coupling capacitor to selectively readout image data output from each of the groups of the plurality of pixel cells, wherein the integrator is coupled to output an output signal on the output line in response to the image data, wherein the output signal on the output line is capacitively coupled to the floating diffusion node by the feedback coupling capacitor to suppress potential swing at the floating diffusion node for each of the groups of the plurality of pixel cells in response to the output signal, wherein the input coupling capacitor is coupled to support different DC voltage levels between the bit line and an input of the integrator, wherein the integrator is coupled to drive a positive voltage step on the output line to supply charge to the floating diffusion node by a feedback capacitor, maintaining the voltage at the floating diffusion node above the voltage at the photosensitive element.

14. The imaging system of claim 13, wherein the group of the plurality of pixel cells includes a column of the pixel array, wherein the integrator is one of a plurality of integrators included in the readout circuit.

15. The imaging system of claim 13, wherein the input coupling capacitor is coupled between the input of the integrator and the bit line such that the bit line is capacitively coupled to the input of the integrator.

16. The imaging system of claim 13, further comprising functional logic coupled to the readout circuitry to store the image data read out from the plurality of pixel cells.

17. A method of operating an image sensor, the method comprising:

resetting a photosensitive element and a floating diffusion node in an image sensor pixel cell;

accumulating image charge in the photosensitive element;

transferring the image charge from the photosensitive element to the floating diffusion node;

generating image data on a bit line in response to the image charge at the floating diffusion node;

integrating the image data on the bit lines with an integrator in response to the image data to produce an output signal on an output line of the integrator; and

suppressing potential swings at the floating diffusion node with a capacitive feedback coupling between the output line and the floating diffusion node, wherein suppressing the potential swings at the floating diffusion node with the capacitive feedback coupling between the output line and the floating diffusion node comprises: a positive voltage step is driven on the output line with the integrator to supply charge to the floating diffusion node through a feedback capacitor to maintain the voltage at the floating diffusion node above the voltage at the photosensitive element.

18. The method of claim 17, further comprising resetting the integrator while resetting the photosensitive element and the floating diffusion node in the image sensor pixel cell.

19. The method of claim 17, further comprising generating a first sample of the output signal on the output line after resetting the photosensitive element and the floating diffusion node in the image sensor pixel cell and before transferring the image charge from the photosensitive element to the floating diffusion node.

20. The method of claim 19, further comprising generating a second sample of the output signal on the output line after integrating the image data on the bit line with the integrator to generate the output signal on the output line of the integrator in response to the image data.

21. The method of claim 20, further comprising generating an output value in response to a difference between the second sample of the output signal and the first sample of the output signal.

22. The method of claim 17, further comprising converting an analog value of the output signal to a digital value of the output signal.

23. The method of claim 17, further comprising amplifying the image charge at the floating diffusion node with an amplifier transistor to generate the image data on the bit line.

24. The method of claim 17, further comprising supporting different DC voltages between the bit line and an input of the integrator with a capacitive coupling between the bit line and the input of the integrator.