HK1225543B - Ramp generator for low noise image sensor - Google Patents

Description

Ramp generator for low-noise image sensors

Technical Field

The present invention generally relates to image sensors. More specifically, embodiments of the present invention relate to circuitry for reading image data from image sensor pixel cells.

Background Art

Image sensors have become ubiquitous. They are widely used in digital cameras, cellular phones, surveillance cameras, as well as in medical, automotive, and other applications. The technology used to manufacture image sensors, and in particular complementary metal oxide semiconductor (CMOS) image sensors, continues to advance significantly. For example, the demand for high resolution and low power consumption is driving the further miniaturization and integration of CMOS image sensors.

In CMOS image sensors, performance factors such as horizontal noise (h-noise), circuit power supply rejection ratio (PSRR), power consumption, and the like have become key parameters that have been sought to improve in recent years. Because human vision is particularly sensitive to horizontal banding/noise in images, significant efforts have been made to reduce this type of noise. Specifically, with the most common image sensor readout architecture, the column-by-column analog-to-digital converter tends to generate a large amount of horizontal noise because the ramp generator is a row-by-row signal. Therefore, any noise in the ramp generator ramp output results in varying row-by-row readout performance. Similarly, due to the nature of single-ended ramp generators, the power supply rejection ratio (PSRR) is also an important factor to consider. Insufficient PSRR will result in horizontal banding in the image due to ripples in the analog power supply.

Another issue with image sensor chips is analog power consumption. The typical analog power supply for state-of-the-art image sensors is about 2.8V. This high analog VDD voltage is necessary in order for the pixels to output full-well signals. However, in the case of generating image pixels in a more aggressive manner, smaller-sized pixels also have lower full-well requirements. Therefore, compared to previous image pixels, a pixel output range of about 1V, about 500mV, or even lower is sufficient. In these cases with lower pixel output ranges, lower analog VDD supply voltages are a trend in future image sensor designs that greatly reduce power consumption. Therefore, the readout circuit also needs to adapt to this lower analog VDD supply voltage trend while still maintaining the same low noise performance.

Summary of the Invention

One embodiment of the present invention relates to a readout circuit for use in an image sensor, comprising: a sense amplifier circuit coupled to a bit line to sense analog image data from a pixel cell of the image sensor; an analog-to-digital converter coupled to the sense amplifier circuit to convert the analog image data into digital image data; a ramp generator circuit coupled to generate a first ramp signal, wherein the analog-to-digital converter is coupled to generate the digital image data in response to the analog image data and the first ramp signal; and a first capacitive voltage divider coupled to the ramp generator, wherein the first capacitive voltage divider is coupled to reduce an output voltage swing of the first ramp signal coupled to be received by the analog-to-digital converter to reduce noise in the first ramp signal.

Another embodiment of the present invention relates to an imaging system comprising: a pixel array including a plurality of pixel cells organized into a plurality of rows and columns for capturing image data; a control circuit coupled to the pixel array to control operation of the pixel array; and a readout circuit coupled to the pixel array to read out the image data from the pixel cells, the readout circuit comprising: a sense amplifier circuit coupled to a bit line to sense analog image data from the pixel array; an analog-to-digital converter coupled to the sense amplifier circuit to convert the analog image data into digital image data; a ramp generator circuit coupled to generate a first ramp signal, wherein the analog-to-digital converter is coupled to generate the digital image data in response to the analog image data and the first ramp signal; and a first capacitive voltage divider coupled to the ramp generator, wherein the first capacitive voltage divider is coupled to reduce an output voltage swing of the first ramp signal coupled to be received by the analog-to-digital converter to reduce noise in the first ramp signal.

BRIEF DESCRIPTION OF THE DRAWINGS

Non-limiting and non-exhaustive embodiments of the present invention are described with reference to the following figures, wherein like reference numerals refer to like parts throughout the various views unless otherwise specified.

1 is a block diagram illustrating an example imaging system including a pixel array having pixel cells and a readout circuit with a ramp generator for achieving low noise in accordance with the teachings of the present invention.

2 is a schematic diagram illustrating one example of a pixel cell coupled to a readout circuit including a ramp generator for achieving low noise in accordance with the teachings of the present invention.

3 is a schematic diagram illustrating greater detail of one example of a ramp generator included in a readout circuit with low noise in accordance with the teachings of the present invention.

4 is a schematic diagram illustrating greater details of another example of a ramp generator included in a readout circuit with low noise in accordance with the teachings of the present invention.

5 illustrates a timing diagram of signals in an example ramp generator included in a readout circuit with low noise in accordance with the teachings of the present invention.

Throughout the several views of the drawings, corresponding reference characters indicate corresponding components. Those skilled in the art will appreciate that the elements in the drawings are illustrated for simplicity and clarity and are not necessarily drawn to scale. For example, the dimensions of some elements in the drawings may be exaggerated relative to other elements to help improve understanding of the various embodiments of the present invention. Furthermore, common and well-understood elements that are useful or necessary in commercially feasible embodiments are generally not depicted to facilitate easier viewing of these various embodiments of the present invention.

DETAILED DESCRIPTION

In the following description, many specific details are set forth in order to provide a thorough understanding of the present invention. However, it will be apparent to one of ordinary skill in the art that it is not necessary to adopt these specific details to practice the present invention. In other cases, well-known materials or methods have not yet been described in detail to avoid obscuring the present invention.

References throughout this specification to "one embodiment," "an embodiment," "an example," or "an instance" mean that a particular feature, structure, or characteristic described in connection with the embodiment or example is included in at least one embodiment of the present invention. Thus, the appearances of the phrases "in one example," "in an embodiment," "an example," or "an instance" in various places throughout this specification are not necessarily all referring to the same embodiment or example. Furthermore, in one or more embodiments or examples, the particular features, structures, or characteristics may be combined in any suitable combinations and/or subcombinations. The particular features, structures, or characteristics may be included in an integrated circuit, an electronic circuit, a combinational logic circuit, or other suitable components that provide the described functionality. In addition, it should be understood that the figures provided herein are for explanation purposes to persons of ordinary skill in the art and that the figures are not necessarily drawn to scale.

An example according to the teachings of the present invention describes a ramp generator coupled to provide a ramp signal for an analog-to-digital converter. In one example, the ramp generator has a relatively large output voltage swing on an output ramp signal received by a capacitive voltage divider to reduce noise. The output voltage swing of the ramp signal is reduced by the capacitive voltage divider. In one example, the ramp generator provides a differential ramp output having two output ramp signals. In this example, the two output ramp signals are complementary signals having relatively large output voltage swings. In this example, a capacitive voltage divider is coupled to each differential ramp output of the ramp generator to reduce noise. The output voltage swing of each ramp signal is reduced by a corresponding capacitive voltage divider to reduce the output voltage swing.

For illustration, FIG1 is a block diagram illustrating an example imaging system according to the teachings of the present invention, including a pixel array having pixel cells and readout circuitry for improving the power supply rejection ratio in the bit lines. Specifically, FIG1 depicts one example of an image sensing system 100 according to the teachings of the present invention, including readout circuitry 104 having a ramp generator with low noise. As shown in the depicted example, imaging system 100 includes a pixel array 102 coupled to control circuitry 108 and readout circuitry 104, which is coupled to function logic 106.

In one example, pixel array 102 is a two-dimensional (2D) array of imaging sensors or pixel cells (e.g., pixel cells P1, P2, P3, ..., Pn). In one example, each pixel cell is a CMOS imaging pixel. As illustrated, each pixel cell is arranged in rows (e.g., rows R1 through Ry) and columns (e.g., columns C1 through Cx) to acquire image data of a person, place, object, etc., which can then be used to reproduce a 2D image of the person, place, object, etc.

In one example, after each pixel cell has accumulated its image data or image charge, the image data is read out by readout circuitry 104 via column bit lines 110 and then transferred to function logic 106. As will be shown, in various examples, readout circuitry 104 may also include amplification circuitry, sampling circuitry, analog-to-digital converter circuitry, ramp generator circuitry, or other circuitry. Function logic 106 may simply store the image data or even manipulate the image data by applying post-processing image effects (e.g., cropping, rotation, red-eye removal, brightness adjustment, contrast adjustment, or other). In one example, readout circuitry 104 may read out image data one row at a time along readout column bit lines 110 (illustrated) or may use various other techniques (not illustrated) to read out image data, such as serial readout or fully parallel readout of all pixels simultaneously.

In one example, control circuitry 108 is coupled to pixel array 102 to control operational characteristics of pixel array 102. For example, control circuitry 108 may generate a shutter signal for controlling image acquisition. In one example, the shutter signal is a global shutter signal that simultaneously enables all pixels within pixel array 102 to simultaneously capture their respective image data during a single acquisition window. In another example, the shutter signal is a rolling shutter signal that sequentially enables each row, column, or group of pixels during successive acquisition windows.

FIG2 is a schematic diagram illustrating an example of a pixel cell coupled to a readout circuit including a ramp generator coupled to an analog-to-digital converter with low noise according to the teachings of the present invention. Specifically, FIG2 shows a schematic diagram of an example of a pixel cell 212 of a pixel array 202 coupled to a column of a readout circuit 204 having a readout architecture with low noise according to the teachings of the present invention. It should be noted that the pixel cell 212, pixel array 202, and readout circuit 204 of FIG2 can be the example pixel cells P1, P2, ... Pn, pixel array 102, and readout circuit 104 of FIG1, and that similarly named and numbered elements referenced below are therefore coupled and function similarly as described above.

2 , pixel cell 212 is illustrated as a four-transistor (4T) pixel cell. It should be understood that pixel cell 212 is one possible example of a pixel circuit architecture for implementing each pixel cell within pixel array 202. However, it should be understood that other examples according to the teachings of the present invention are not necessarily limited to a 4T pixel architecture. Those of ordinary skill in the art having the benefit of the present disclosure will understand that the present teachings may also be applicable to 3T designs, 5T designs, and various other pixel cell architectures according to the teachings of the present invention.

2 , pixel cell 212 includes a photosensitive element (which may also be referred to as a photodiode (PD) 214 for accumulating image charge), a transfer transistor T1 216, a reset transistor T2 218, a floating diffusion (FD) node 222, an amplifier transistor (which is also illustrated as a source follower (SF) transistor T3 224), and a row select transistor T4 226. During operation, transfer transistor T1 216 receives a transfer signal TX, which selectively transfers image charge accumulated in photosensitive element PD 214 to floating diffusion FD node 222.

As shown in the illustrated example, reset transistor T2 218 is coupled between supply voltage AVDD 220 and floating diffusion node FD 222 to reset the voltage level in pixel cell 212 (e.g., discharge or charge floating diffusion node FD 222 and photosensitive element PD 214 to a preset voltage) in response to reset signal RST. Floating diffusion node FD 222 is coupled to control the gate of amplifier transistor SF T3 224. Amplifier transistor SF T3 224 is coupled between supply voltage AVDD 220 and row select transistor RS T4 226. Amplifier transistor SF T3 224 operates as a source follower amplifier providing a high impedance connection to floating diffusion node FD 222. Row select transistor RS T4 226 selectively couples the image data output of pixel cell 212 to readout column bit line 210 in response to row select signal RS. In the illustrated example, bit line 210 is coupled to selectively read out image data from a column of pixel array 202. Pixel cells arranged in the same column may share the same bit line.

2 also illustrates a column of readout circuitry 204 that includes sense amplifier circuitry 228 coupled to bit lines 210 to read out image data from pixel cells 212 of pixel array 202. In one example, image data sensed using sense amplifier circuitry 228 may be sampled and then output to analog-to-digital converter 230, which converts the sensed analog image data received from sense amplifier circuitry 228 into digital image data 238.

In one example, in accordance with the teachings of the present invention, the analog-to-digital converter 230 is also coupled to receive RAMP_SIGNAL 234 from the ramp generator circuit 232 via a capacitive voltage divider 236. In one example, the output voltage swing of RAMP_SIGNAL 234 is relatively large and therefore has low noise. In one example, in accordance with the teachings of the present invention, the capacitive voltage divider 236 is coupled to the ramp generator circuit 232 to reduce the voltage swing of RAMP_SIGNAL 234 and further reduce noise. The analog-to-digital converter 230 outputs a digital image data 238 signal after the conversion process is complete in response to the RAMP_SIGNAL 234 signal and the analog image data signal received from the sense amplifier circuit 228. In one example, the digital image data 238 can then be received by the function logic 106 as shown in FIG.

In another example, the ramp generator circuit 232 has another ramp output, and therefore has two ramp outputs, including a first RAMP_SIGNAL 234 and an optional second RAMP_SIGNAL' 240. In this example, the first RAMP_SIGNAL 234 and the second RAMP_SIGNAL' 240 are complementary signals that provide a differential output with a relatively large output voltage swing with low noise. In the example with the optional second RAMP_SIGNAL' 240, according to the teachings of the present invention, a corresponding optional second capacitive voltage divider 242 is coupled to the ramp generator circuit 232 to reduce the voltage swing of the second RAMP_SIGNAL' 240 and further reduce noise. As shown in FIG. 2, the optional second RAMP_SIGNAL' 240 and the second capacitive voltage divider 242 are illustrated with dashed lines. Thus, the analog-to-digital converter 230 outputs a digital image data 238 signal after the conversion process is complete in response to the first RAMP_SIGNAL 234 signal, the second RAMP_SIGNAL′ 240 signal, and the analog image data signal received from the sense amplifier circuit 228. In one example, the digital image data 238 can then be received by the function logic 106 as shown in FIG.

FIG3 is a schematic diagram illustrating in greater detail one example of a ramp generator circuit 332 included in a readout circuit 304 with low noise in accordance with the teachings of the present invention. It should be noted that the ramp generator circuit 332 of FIG3 and the elements included in the readout circuit 304 may be examples of the ramp generator circuit 232 and the readout circuit 204 of FIG2 , and that similarly named and numbered elements referenced below are therefore coupled and function similarly to the elements described above.

As shown in the depicted example, readout circuitry 304 includes a sense amplifier circuit 328 coupled to bit line 310 to sense analog image data from pixel cell 312 of the image sensor. In one example, sense amplifier circuit 328 is coupled to sense image data from pixel cell 312 through input coupling capacitor Cin 346 as shown. The example depicted in FIG3 illustrates current source 344 coupled to sink current I1 from bit line 310. Amplifier transistor SF 324 of pixel cell 312 is coupled to amplify image data on floating diffusion node FD 322 to produce analog image data on bit line 310 that is sensed by sense amplifier circuit 328. Reset switch 318 in pixel cell 312 is coupled to reset the image charge on floating diffusion node FD 322 in response to a reset RST signal.

In the depicted example, the sense amplifier circuit 328 includes a single-input/single-output amplifier SA1 348. In the example, the single input terminal is capacitively coupled to the output terminal of the amplifier SA1 348 via a capacitor C5 350. Additionally, the single input terminal is further coupled to the output terminal of the amplifier SA1 348 via a voltage equalization switch EQ 352. In the example, the output of the sense amplifier is switched via a switch SP0 354.

As shown in the illustrated example, the analog-to-digital converter 330 is coupled to the sense amplifier circuit 328 to convert analog image data received from the sense amplifier circuit 328 into digital image data. In the example, the analog-to-digital converter 330 includes a first operational amplifier 364 having a non-inverting input terminal coupled to first and second capacitors C1 356 and C2 358 of a first capacitive voltage divider 336, which will be described in further detail below. In the example, the first operational amplifier 364 further includes an inverting input terminal that is coupled to the output terminal of the first operational amplifier 364 via capacitor C6 366. Additionally, the inverting input terminal of the first operational amplifier 364 is further coupled to the output terminal of the first operational amplifier 364 via an analog-to-digital converter equalizing switch AZ1 368, as shown. In the example, the inverting input terminal of the first operational amplifier 364 is also capacitively coupled to a first reference voltage (e.g., ground) via capacitor C7 370.

3 also illustrates a ramp generator circuit 332 coupled to generate a first RAMP_SIGNAL 334 coupled to be received by the analog-to-digital converter 330 through a first capacitive voltage divider 336. In the example, the first capacitive voltage divider 336 includes a first capacitor C1 356 coupled to a second capacitor C2 358. In the example, the first capacitor C1 356 is coupled between the ramp generator circuit 332 and the non-inverting input terminal of the first operational amplifier 364 of the analog-to-digital converter 330. The second capacitor C2 358 is coupled between the non-inverting input terminal of the first operational amplifier 364 and a first reference voltage terminal (e.g., ground). Thus, the analog-to-digital converter 330 is coupled to generate digital image data in response to the analog image data from the sense amplifier circuit 328 and the first RAMP_SIGNAL 334 received from the ramp generator circuit 332 through the first capacitive voltage divider 336.

3 , the ramp generator circuit 332 generates a single ramp output RAMP_SIGNAL 334 from the output terminal of a second operational amplifier 372, which has an inverting input terminal capacitively coupled to the output terminal of the second operational amplifier 372 through a capacitor Cint 374. Additionally, the inverting input terminal is also coupled to the output terminal of the second operational amplifier 372 through a first ramp generator voltage-scaling switch S1 376, which is also coupled to receive a current I_INTEG from a current source 384. In the example, the second operational amplifier 372 further includes a non-inverting input terminal coupled to a second reference voltage terminal to receive a voltage VRN 378. In one example, the voltage VRN 378 is sampled onto a capacitor C8 380 via the switch in response to a SAMP_VRN signal 382.

In operation, RAMP_SIGNAL 334 has a relatively large output voltage and therefore low noise. In accordance with the teachings of the present invention, a first capacitive voltage divider 336 is coupled to reduce the output voltage swing of the first RAMP_SIGNAL 334 coupled to be received by the analog-to-digital converter 330 to further reduce noise in the first RAMP_SIGNAL 334. For example, the voltage at the node between capacitor C1 356 and capacitor C2 358 (which is coupled to the non-inverting input terminal of the first operational amplifier 364) can be determined as follows:

(Equation 1)

Where V is the voltage at the node between capacitor C1 356 and capacitor C2 358 , C1 is the capacitance value of capacitor C1 356 , C2 is the capacitance value of capacitor C2 358 , and RAMP_SIGNAL is the voltage of RAMP_SIGNAL 334 .

FIG4 is a schematic diagram illustrating in greater detail another example of a ramp generator circuit 432 included in a readout circuit 404 having low noise in accordance with the teachings of the present invention. It should be noted that the readout circuit 404 of FIG4 shares many similarities with the readout circuit 304 of FIG3 . For example, similar to the readout circuit 304 of FIG3 , the readout circuit of FIG4 also includes a sense amplifier circuit 428 coupled to a bit line 410 for sensing analog image data from a pixel cell 412 of an image sensor. An analog-to-digital converter 430 is coupled to the sense amplifier circuit 428 to convert the analog image data from the pixel cell 412 into digital image data. The ramp generator circuit 432 is coupled to generate a first ramp signal RAMP_SIGNAL 434, such that the analog-to-digital converter 430 is coupled to generate digital image data in response to the analog image data from the pixel cell 412 and the first RAMP_SIGNAL 434. Additionally, a first capacitive voltage divider 436 comprising a first capacitor C1 456 and a second capacitor C2 458 is coupled to the ramp generator circuit 432. Furthermore, the first capacitive voltage divider 436 is coupled to reduce the output voltage swing of the first RAMP_SIGNAL 434 coupled to be received by the analog-to-digital converter 430 to reduce noise in the first RAMP_SIGNAL 434. Thus, it should be understood that the elements in the readout circuit 404 of FIG. 4 referenced below are coupled and function similarly to the similarly named and numbered elements of the readout circuit 304 of FIG. 3 described above.

One difference between the readout circuit 404 of FIG. 4 and the readout circuit 304 of FIG. 3 is that the ramp generator circuit 432 of FIG. 4 has a differential ramp output including two ramp outputs, a first RAMP_SIGNAL 434 and a second RAMP_SIGNAL′ 440. In the example, the first RAMP_SIGNAL 434 and the second RAMP_SIGNAL′ 440 are complementary signals with relatively large output voltage swings and, therefore, low noise. In the example depicted in FIG. 4 , a corresponding optional second capacitive voltage divider 442 is also coupled to the ramp generator circuit 432 to reduce the voltage swing of the second RAMP_SIGNAL′ 440 and further reduce noise, in accordance with the teachings of the present invention.

4 , the second capacitive voltage divider 442 includes a third capacitor C3 460 coupled to a fourth capacitor C4 462. The third capacitor C3 460 is coupled between the ramp generator circuit 432 and the inverting input terminal of the first operational amplifier 464 of the analog-to-digital converter 430. The fourth capacitor C4 462 is coupled between the inverting input terminal of the first operational amplifier 464 and a first reference voltage terminal (e.g., ground). The first RAMP_SIGNAL 434 from the ramp generator circuit 432 is coupled to the non-inverting terminal of the first operational amplifier 464 of FIG. 4 in a manner similar to the way the first RAMP_SIGNAL 334 from the ramp generator circuit 332 is coupled to the non-inverting terminal of the first operational amplifier 364 of FIG. 3 . 4 is coupled to generate digital image data in response to analog image data received through sense amplifier circuit 428, first RAMP_SIGNAL 434 and second RAMP_SIGNAL′ 440 from ramp generator circuit 432.

4 , the ramp generator circuit 432 includes a differential output operational amplifier 472 having a first inverting output terminal coupled to generate a first RAMP_SIGNAL 434 and a second non-inverting output terminal for generating a second RAMP_SIGNAL′ 440. In the example, the first RAMP_SIGNAL 434 and the second RAMP_SIGNAL′ 440 form a differential output having complementary signals. As shown in the example, the differential output operational amplifier 472 also includes a non-inverting input terminal and an inverting input terminal.

In the example, the non-inverting input terminal of the differential output operational amplifier 472 is capacitively coupled to the inverting output terminal of the differential output operational amplifier 472 through a capacitor Cint 474. Additionally, the non-inverting input terminal is coupled to the inverting output terminal of the differential output operational amplifier 472 through a first differential output operational amplifier voltage equalizing switch S1 476. In the example, the non-inverting input terminal is further coupled to the I_INTEG current source 484 through a switch S3 492. In the example, the non-inverting input terminal is further capacitively coupled through a capacitor Cp 499 to receive the CVDN1 489 signal through a switch S2 496. In the example, the non-inverting input terminal is further capacitively coupled through a capacitor Ccvdn 495 to receive the CVDN 491 signal.

In the example, the inverting input terminal of the differential output operational amplifier 472 is capacitively coupled to the non-inverting output terminal of the differential output operational amplifier 472 via capacitor Cint 486. Additionally, the inverting input terminal is coupled to the non-inverting output terminal of the differential output operational amplifier 472 via a second differential output operational amplifier voltage equalization switch S1 488. In the example, the inverting input terminal is further coupled to the I_INTEG current source 490 via switch S3 494. In the example, the inverting input terminal is further capacitively coupled via capacitor Cp 497 to receive the CVDN1 489 signal via switch S2 498. In the example, the inverting input terminal is further capacitively coupled via capacitor Ccvdn 493 to receive the CVDN 491 signal. In one example, the relationship between the capacitance values of Cp, Cint, and Ccvdn is:

Cp = Cint = 10 × CCvdn (Equation 2)

It should be appreciated that the example ramp generator circuit 432 of FIG. 4 , with first and second capacitive voltage dividers 436 and 442, respectively, provides a fully differential ramp output that can be implemented to further improve dynamic range. For example, the fully differential ramp generator example depicted in FIG. 4 can double the dynamic range compared to the single-ended ramp generator example. Furthermore, according to the teachings of the present invention, as power supply output voltage continues to decrease with technological advancements, the fully differential ramp generator 432, with first and second capacitive voltage dividers 436 and 442, respectively, provides sufficient gain and bandwidth compared to the single-ended ramp generator example, while also providing improved power supply rejection ratio and common mode rejection ratio performance to provide sufficient drive capability through the class AB output stage while maintaining noise performance comparable to that of a single-ended ramp generator.

FIG5 illustrates an example timing diagram 587 explaining the relationship of signals in the example ramp generator circuit 432 included in the readout circuit 404 of FIG4 with low noise in accordance with the teachings of the present invention. Thus, it should be understood that the signals and elements described in FIG5 referenced below are coupled and function in the same manner as the similarly named and numbered elements of the readout circuit 404 of FIG4 referenced above.

5 , at time T0 , signal S1 576 transitions from a low value to a high value, which turns on first and second differential output operational amplifier equalizing switches S1 476 and S1 488 and resets and/or initializes first RAMP_SIGNAL 534 and second RAMP_SIGNAL′ 540 .

At time T1, signal S1 576 transitions from a high value back to a low value, signal S2 596 is at a high value, signal S3 592 is at a low value, signal CVDN 591 is at a low value, and signal CVDN1 589 transitions from a low value to a high value. Thus, the non-inverting and inverting input terminals of the differential output operational amplifier 472 are capacitively coupled to the high value CVDN1 through the capacitor having a value Cp. Thus, the complementary first RAMP_SIGNAL 534 and second RAMP_SIGNAL′ 540 signals begin to precharge, as shown in FIG5 . In the illustrated example, it should be understood that signal S2 596 remains at a high value to complete precharging the complementary first RAMP_SIGNAL 534 and second RAMP_SIGNAL′ 540 signals before the reset RST signal 418 of the pixel cell 412 goes low.

At time T2, precharging of the complementary first RAMP_SIGNAL 534 and second RAMP_SIGNAL′ 540 signals is complete, and signal S2 596 may therefore transition from a high value to a low value, while signal CVDN 591 remains at a low value and signal CVDN1 589 remains at a high value. At this point, the complementary first RAMP_SIGNAL 534 and second RAMP_SIGNAL′ 540 remain at their respective precharge levels, as shown.

At time T3, signal CVDN 591 transitions from a low value to a high value. Consequently, the non-inverting and inverting input terminals of differential output operational amplifier 472 are capacitively coupled to the high value CVDN through capacitance having a value Ccvdn. Consequently, the complementary first RAMP_SIGNAL 534 and second RAMP_SIGNAL′ 540 signals are now adjusted to their starting ramp voltage levels, as shown in FIG5 .

At time T4, signal S3 592 transitions from a low level to a high level, which couples the I_INTEG current source 484 to the non-inverting terminal and the I_INTEG current source 490 to the non-inverting and inverting terminals, respectively, of the differential output operational amplifier 472. Thus, the complementary first RAMP_SIGNAL 534 and second RAMP_SIGNAL′ 540 begin ramping at time T4, as shown in FIG5 .

The above description of illustrated embodiments of the present invention (including what is described in the Abstract) is not intended to be exhaustive or to limit the present invention to the precise forms disclosed. Although specific embodiments and examples of the present invention are described herein for illustrative purposes, various equivalent modifications are possible without departing from the broader spirit and scope of the present invention.

These modifications may be made to examples of the invention in light of the above detailed description. The terms used in the appended claims should not be construed to limit the invention to the specific embodiments disclosed in the specification and claims. Rather, the scope is to be determined entirely by the appended claims, which are to be interpreted in accordance with established doctrines of claim interpretation. The specification and drawings are, therefore, to be regarded as illustrative rather than restrictive.

Claims (17)

1. A readout circuit for use in an image sensor, comprising: A sensing amplifier circuit coupled to a bit line to sense analog image data from the pixel units of the image sensor; An analog-to-digital converter coupled to the sensing amplifier circuit to convert the analog image data into digital image data; A ramp generator circuit, coupled to generate a first ramp signal and a second ramp signal, such that the first ramp signal and the second ramp signal form a differential ramp output of the ramp generator circuit, wherein the first ramp signal and the second ramp signal are complementary signals, and wherein the analog-to-digital converter is coupled to generate digital image data in response to the analog image data, the first ramp signal, and the second ramp signal; and A first capacitive voltage divider is coupled to the ramp generator circuit, wherein the first capacitive voltage divider is coupled to reduce the output voltage swing of the first ramp signal coupled to be received by the analog-to-digital converter in order to reduce noise in the first ramp signal. 2. The readout circuit of claim 1, wherein the first capacitive voltage divider includes a first capacitor coupled to a second capacitor, wherein the first capacitor is coupled between the ramp generator circuit and a first input terminal of the analog-to-digital converter, and wherein the second capacitor is coupled between the first input terminal of the analog-to-digital converter and a first reference voltage terminal. 3. The readout circuit of claim 2, wherein the analog-to-digital converter includes a first operational amplifier having a first input terminal coupled to the first and second capacitors of the first capacitive voltage divider, wherein the first operational amplifier further includes a second input terminal capacitively coupled to an output terminal of the first operational amplifier, and wherein the second input terminal of the first operational amplifier is further coupled to the output terminal of the first operational amplifier via an analog-to-digital converter voltage equalization switch. 4. The readout circuit of claim 3, wherein the ramp generator circuit includes a second operational amplifier having a first input terminal capacitively coupled to the output terminal of the second operational amplifier, wherein the first input terminal of the second operational amplifier is further coupled to the output terminal of the second operational amplifier via a first ramp generator equalization switch, and wherein the second operational amplifier further includes a second input terminal coupled to a second reference voltage terminal. 5. The readout circuit of claim 1, further comprising a second capacitive voltage divider coupled to the ramp generator circuit, wherein the second capacitive voltage divider is coupled to reduce the output voltage swing of the second ramp signal coupled to be received by the analog-to-digital converter to reduce noise in the second ramp signal. 6. The readout circuit of claim 5, wherein the second capacitive voltage divider includes a third capacitor coupled to the fourth capacitor, wherein the third capacitor is coupled between the ramp generator circuit and the second terminal of the analog-to-digital converter, and wherein the fourth capacitor is coupled between the second terminal of the analog-to-digital converter and the first reference voltage terminal. 7. The readout circuit of claim 6, wherein the ramp generator circuit includes a differential output operational amplifier having a first output terminal coupled to generate the first ramp signal, and wherein the differential output operational amplifier further includes a second output terminal coupled to generate the second ramp signal. 8. The readout circuit according to claim 7, wherein the differential output operational amplifier further includes a first input terminal capacitively coupled to the first output terminal of the differential output operational amplifier, wherein the first input terminal of the differential output operational amplifier is further coupled to the first output terminal of the differential output operational amplifier via a first differential output operational amplifier equalization switch, wherein the differential output operational amplifier further includes a second input terminal capacitively coupled to the second output terminal of the differential output operational amplifier, wherein the second input terminal of the differential output operational amplifier is further coupled to the second output terminal of the differential output operational amplifier via a second differential output operational amplifier equalization switch. 9. An imaging system comprising: A pixel array, which contains multiple pixel units organized into multiple rows and columns for capturing image data; Control circuitry coupled to the pixel array to control the operation of the pixel array; and A readout circuit coupled to the pixel array to read the image data from the pixel units, the readout circuit comprising: A sensing amplifier circuit coupled to a bit line to sense analog image data from a pixel array; An analog-to-digital converter coupled to the sensing amplifier circuit to convert the analog image data into digital image data; A ramp generator circuit, coupled to generate a first ramp signal and a second ramp signal, such that the first ramp signal and the second ramp signal form a differential ramp output of the ramp generator circuit, wherein the first ramp signal and the second ramp signal are complementary signals, and wherein the analog-to-digital converter is coupled to generate digital image data in response to the analog image data, the first ramp signal, and the second ramp signal; and A first capacitive voltage divider is coupled to the ramp generator circuit, wherein the first capacitive voltage divider is coupled to reduce the output voltage swing of the first ramp signal coupled to be received by the analog-to-digital converter in order to reduce noise in the first ramp signal. 10. The imaging system of claim 9, further comprising a functional logic module coupled to the readout circuit to store the image data read from the plurality of pixel units. 11. The imaging system of claim 9, wherein the first capacitive voltage divider includes a first capacitor coupled to a second capacitor, wherein the first capacitor is coupled between the ramp generator circuit and a first input terminal of the analog-to-digital converter, and wherein the second capacitor is coupled between the first input terminal of the analog-to-digital converter and a first reference voltage terminal. 12. The imaging system of claim 11, wherein the analog-to-digital converter includes a first operational amplifier having a first input terminal coupled to the first and second capacitors of the first capacitive voltage divider, wherein the first operational amplifier further includes a second input terminal capacitively coupled to an output terminal of the first operational amplifier, and wherein the second input terminal of the first operational amplifier is further coupled to the output terminal of the first operational amplifier via an analog-to-digital converter voltage equalization switch. 13. The imaging system of claim 12, wherein the ramp generator circuit includes a second operational amplifier having a first input terminal capacitively coupled to an output terminal of the second operational amplifier, wherein the first input terminal of the second operational amplifier is further coupled to the output terminal of the second operational amplifier via a first ramp generator equalization switch, and wherein the second operational amplifier further includes a second input terminal coupled to a second reference voltage terminal. 14. The imaging system of claim 9, further comprising a second capacitive voltage divider coupled to the ramp generator circuit, wherein the second capacitive voltage divider is coupled to reduce the output voltage swing of the second ramp signal coupled to be received by the analog-to-digital converter to reduce noise in the second ramp signal. 15. The imaging system of claim 14, wherein the second capacitive voltage divider includes a third capacitor coupled to a fourth capacitor, wherein the third capacitor is coupled between the ramp generator circuit and a second terminal of the analog-to-digital converter, and wherein the fourth capacitor is coupled between the second terminal of the analog-to-digital converter and a first reference voltage terminal. 16. The imaging system of claim 15, wherein the ramp generator circuit includes a differential output operational amplifier having a first output terminal coupled to generate the first ramp signal, and wherein the differential output operational amplifier further includes a second output terminal coupled to generate the second ramp signal. 17. The imaging system of claim 16, wherein the differential output operational amplifier further includes a first input terminal capacitively coupled to the first output terminal of the differential output operational amplifier, wherein the first input terminal of the differential output operational amplifier is further coupled to the first output terminal of the differential output operational amplifier via a first differential output operational amplifier equalization switch, wherein the differential output operational amplifier further includes a second input terminal capacitively coupled to the second output terminal of the differential output operational amplifier, wherein the second input terminal of the differential output operational amplifier is further coupled to the second output terminal of the differential output operational amplifier via a second differential output operational amplifier equalization switch.