HK1131696B - Semiconductor component and method of manufacture - Google Patents

Description

Semiconductor component and method for manufacturing the same

Technical Field

The present invention relates generally to semiconductor components, and more particularly to power switching semiconductor components.

Background

Metal oxide semiconductor field effect transistors ("MOSFETs") are a common type of power switching device. The MOSFET device includes a source region, a drain region, a channel region extending between the source region and the drain region, and a gate structure disposed adjacent to the channel region. The gate structure includes a conductive gate electrode layer disposed adjacent to the channel region and separated from the channel region by a thin dielectric layer. When a voltage of sufficient strength is applied to the gate structure to place the MOSFET device in an on-state, a conductive channel region is formed between the source and drain regions, thereby allowing current to flow through the device. When the voltage applied to the gate is insufficient to cause channel formation, no current flows and the MOSFET device is in an off state.

Today's market for high voltage power switches is mainly driven by two main factors: breakdown voltage ("BVdss") and on-resistance ("Rdson"). Minimum breakdown voltage is required for a particular application and in practice designers are often able to meet BVdss specifications. However, this is often at the cost of Rdson. This performance trade-off is a major design challenge for manufacturers and users of high voltage power switching devices. Another challenge arises because power MOSFET devices have an inherent P-N diode between a P-type conductivity body region and an N-type conductivity epitaxial region. The intrinsic P-N diode turns on under certain operating conditions and stores charge across the P-N junction. When a sudden reverse bias is applied to the P-N diode, the stored charge produces a negative current until the charge is completely depleted. The time for the charge to drain is called the reverse recovery time ("Trr") and this time delays the switching speed of the power MOSFET device. In addition, the stored charge ("Qrr") also causes a loss in the switching voltage level due to the peak reverse recovery current ("Irr") and reverse recovery time.

It would therefore be advantageous to have a semiconductor component with a lower Rdson while having a higher breakdown voltage and lower switching losses, i.e. low Qrr losses, and a method of manufacturing such a semiconductor component. For semiconductor components, cost-effective manufacturing is more advantageous.

Disclosure of Invention

Mainly, the present invention provides a semiconductor component comprising a field plate and a semiconductor device, such as a field effect transistor or a trench field effect transistor (trench field effect transistor), a vertical power field effect transistor, a power field effect transistor, or a combination thereof. It should be noted that a power field effect transistor is also referred to as a vertical power device, and a vertical field effect transistor is also referred to as a power device. According to an embodiment, a semiconductor component includes at least one trench formed in a semiconductor material including an epitaxial material disposed on a semiconductor substrate. The at least one trench has a first portion and a second portion, wherein the first portion of the field plate is fabricated in the first portion of the at least one trench and the second portion of the field plate is fabricated in the second portion of the at least one trench. A gate structure is fabricated in the second portion of the trench, wherein the gate oxide is made of a portion of the epitaxial layer.

According to another embodiment, a gate structure is fabricated in the second portion of the trench, wherein the gate oxide is made of a portion of the epitaxial layer. A gate electrode is formed laterally adjacent the gate oxide, wherein the gate electrode is separated from portions of the field plate by a dielectric material in the first and second portions of the trench.

Drawings

The present invention will be better understood from the following detailed description taken in conjunction with the accompanying drawings, in which like reference numerals identify like elements, and in which:

FIG. 1 is a cross-sectional view of a semiconductor component according to an embodiment of the present invention at an early stage of fabrication;

FIG. 2 is a cross-sectional view of the semiconductor component of FIG. 1 at a later stage of fabrication;

FIG. 3 is a cross-sectional view of the semiconductor component of FIG. 2 at a later stage of fabrication;

FIG. 4 is a cross-sectional view of the semiconductor component of FIG. 3 at a later stage of manufacture;

FIG. 5 is a cross-sectional view of the semiconductor component of FIG. 4 at a later stage of manufacture;

FIG. 6 is a cross-sectional view of the semiconductor component of FIG. 5 at a later stage of manufacture;

FIG. 7 is a cross-sectional view of the semiconductor component of FIG. 6 at a later stage of manufacture;

FIG. 8 is a cross-sectional view of the semiconductor component of FIG. 7 at a later stage of manufacture;

fig. 9 is a longitudinal sectional view of the semiconductor component of fig. 8;

FIG. 10 is a cross-sectional view of the semiconductor component of FIG. 9 at a later stage of fabrication;

FIG. 11 is a cross-sectional view of the semiconductor component of FIG. 10 at a later stage of manufacture;

fig. 12 is a longitudinal cross-sectional view of the semiconductor component of fig. 11 at an earlier stage of fabrication;

FIG. 13 is a cross-sectional view of the semiconductor component of FIG. 12 at a later stage of fabrication;

FIG. 14 is a cross-sectional view of the semiconductor component of FIG. 13 at a later stage of manufacture;

fig. 15 is a cross-sectional view of the semiconductor component of fig. 14 at a later stage of manufacture;

fig. 16 is a cross-sectional view of the semiconductor component of fig. 15 at a later stage of manufacture.

Detailed Description

Fig. 1 is a cross-sectional view of a portion of a semiconductor component 10 during fabrication according to an embodiment of the present invention. Shown in fig. 1 is a semiconductor material 12 having opposed surfaces 14 and 16. Surface 14 is also referred to as a front or top surface and surface 16 is also referred to as a bottom or back surface. According to an embodiment, semiconductor material 12 includes an epitaxial layer 20 disposed on a semiconductor substrate 18. Preferably, substrate 18 is silicon heavily doped with an N-type dopant or impurity material, while epitaxial layer 20 is silicon lightly doped with an N-type dopant. The substrate layer 18 may have a resistivity of less than about 0.01 ohm-centimeters ("Ω -cm"), while the epitaxial layer 20 may have a resistivity of greater than about 0.1 Ω -cm. Substrate layer 18 provides a low resistance conductive path for current flowing through the power transistor and provides a low resistance electrical connection to a bottom drain conductor (drain conductor), a top drain conductor, or both conductors formed on bottom surface 16 of semiconductor material 12. A region or layer doped with an N-type dopant is referred to as a region having N-type conductivity or an N conductivity type, and a region or layer doped with a P-type dopant is referred to as a region having P-type conductivity or a P conductivity type.

A layer of dielectric material 26 is formed on epitaxial layer 20 or from epitaxial layer 20. According to an embodiment, the material of dielectric layer 26 is about 200 angstroms (a) thick) To aboutOf (4) silicon dioxide. Techniques for forming silicon dioxide layer 26 are well known to those skilled in the art. An implant mask (not shown) is formed over dielectric layer 26. By way of example, the implantation mask is a photoresist having an opening that exposes a portion of dielectric layer 26. A P-type conductivity dopant layer (not shown) is formed in epitaxial layer 20. The dopant layer may be formed by implanting an impurity material such as, for example, boron into epitaxial layer 26. Boron may be present at about 1.0 × 10¹³Ions per square centimeter (ions/cm)²) To about 1.0X 10¹⁴Ion/cm²And implanted at an implant energy of about 100 kilo electron volts (keV) to about 400 keV. The technique of forming the dopant layer is not limited to the implantation technique. The mask structure is removed.

A protective layer 28 is formed over dielectric layer 26. The protective layer 28 may be about thickTo aboutSilicon nitride of (2). According to an embodiment, dielectric layer 26 has a thickness of aboutAnd protective layer 28 has a thickness of about 1,000Is measured. Preferably, the materials of layers 26 and 28 are selected such that protective layer 28 limits oxygen diffusion and thus prevents oxidation of the underlying layers. Although the protective layer 28 is shown as a single layer of material, it may be a multi-layer structure of different material types. The epitaxial layer 20 is annealed by heating to a temperature of from about 1,000 degrees celsius (c) to about 1, 200 c. Annealing the epitaxial layer 20 drives the impurity material of the dopant layer to form doped regions 30. A thickness of aboutTo aboutIs formed on the protective layer 28. By way of example, the semiconductor material of layer 32 is about thickOf polycrystalline silicon.

Referring now to fig. 2, a photoresist layer is patterned on the polysilicon layer 32 to form a mask structure 34 having an opening 36 that exposes a portion of the polysilicon layer 32. The mask structure 34 is also referred to as a mask. Trenches 38 and 39 having sidewalls 41 and 43, respectively, and bottoms 45 and 47 are formed in epitaxial layer 20 by removing the exposed portions of polysilicon layer 32, the portions of protective layer 28 and dielectric layer 26 under the exposed portions of polysilicon layer 32, and the portions of epitaxial layer 20 under the exposed portions of polysilicon layer 32. These portions of layers 32, 28, 26, and 20 may be removed using an anisotropic etching technique such as, for example, reactive ion etching. Although trenches 38 and 39 are shown as terminating in epitaxial layer 20, this is not a limitation of the present invention. For example, trenches 38 and 39 may extend into substrate 18. The etching technique and the number of trenches formed in epitaxial layer 20 are not limitations of the present invention. Masking structure 34 is removed.

Referring now to FIG. 3, the thickness is aboutTo aboutOn the polysilicon layer 32, andformed along the sidewalls 41 and 43 and bottoms 45 and 47 of each of the grooves 38 and 39. A thickness of aboutTo aboutIs formed on the sacrificial layer 40. Thus, dielectric material 42 is formed laterally adjacent sidewalls 41 and 43 and vertically adjacent bottoms 45 and 47. The dielectric material 42 may be formed or deposited by decomposition of tetraethylorthosilicate (tetraethylorthosilicate). The dielectric layer formed in this way is also referred to as TEOS layer. Dielectric layer 42 is annealed by heating to a temperature of about 500 c to about 1,500 c. A thickness of aboutTo aboutSuch as, for example, a TEOS layer, is formed on dielectric layer 42. As with dielectric layer 42, dielectric layer 44 is formed laterally adjacent sidewalls 41 and 43 and vertically adjacent bottoms 45 and 47. Doped layers 46 of semiconductor material such as, for example, a dopant or impurity material concentration of about 1.0 x 10¹⁹Atoms per cubic centimeter (atom/cm)³) To about 5X 10²⁰Atom/cm³And has a thickness of aboutToIs formed on dielectric layer 44. According to an embodiment of the present invention, the sacrificial layer 40 has a thickness of aboutDielectric layer 42 and dielectric layer 44 each have a thickness of aboutAnd polysilicon layer 46 has a thickness of aboutThickness of (2) and concentration of about 1X 10²⁰Atom/cm³Doped with an impurity material of N-type conductivity. Thus, the semiconductor layer 46 is in contact with the trench38 and 39 between adjacent dielectric materials at sidewalls 41 and 43.

Referring now to fig. 4, the polysilicon layer 46 is etched using a blanket polysilicon etch back process (blanket polysilicon etchback process) leaving portions 50 and 52 of the polysilicon layer 46 in the trenches 38 and 39, respectively.

Referring now to fig. 5, dielectric layers 44, 42 and 40 are anisotropically etched using, for example, reactive ion etching to expose remaining portions of polysilicon layer 32. After the reactive ion etch, portions 54, 56, and 58 of dielectric layers 44, 42, and 40, respectively, remain in trenches 38, and portions 60, 62, and 64 of dielectric layers 44, 42, and 40, respectively, remain in trenches 39. Thus, the anisotropic etch of dielectric layers 44, 42, and 40 removes sub-portions of dielectric layers 44, 42, and 40.

Referring now to fig. 6, portions 50 and 52 of polysilicon layer 46 and the remaining portion of polysilicon layer 32, i.e., the exposed portion of polysilicon layer 32, are removed using, for example, an anisotropic reactive ion etch. After the anisotropic reactive ion etch, sub-portions 50A and 52A of polysilicon portions 50 and 52 remain in trenches 38 and 39, respectively, and portions 70 and 72 of epitaxial layer 20 adjacent trenches 38 and 39 are exposed.

Referring now to FIG. 7, the thickness is aboutTo aboutIs formed over protective layer 28, dielectric portions 54-58 and 60-64, exposed portions 70 and 72 of epitaxial layer 20, and sub-portions 50A and 52A of polysilicon portions 50 and 52. The sacrificial oxide layer is removed using an etching solution comprising, for example, ten parts hydrofluoric acid to one part water. Removal of the sacrificial oxide exposes portions 70 and 72 of epitaxial layer 20. A thickness of aboutTo aboutOf the dielectric material layer 76 consisting of portions including the sidewalls 41 and 43Exposed portions 70 and 72 of epitaxial layer 20 are formed. The dielectric material layer 76 is thus formed by portions of the sidewalls 41 and 43. According to an embodiment of the present invention, the dielectric layer 76 is an oxide layer that functions as a gate oxide of the semiconductor component 10. Conductive materials such as, for example, dopant or impurity materials at a concentration of about 1X 10¹⁹Atom/cm³To about 5X 10²⁰Atom/cm³And has a thickness of aboutTo aboutIs formed on gate oxide 76 and on exposed portions of dielectric portions 54-58 and 60-64 and protective layer 28. According to an embodiment of the invention, conductive layer 78 is about thickAnd the impurity material concentration is about 1 x 10²⁰Atom/cm³The polysilicon layer of (a).

Optionally, a refractory metal layer 80 such as, for example, tungsten or tungsten silicide is conformally deposited on the polysilicon layer 78. It should be understood that the type of silicide is not a limitation of the present invention. For example, other suitable silicides include titanium silicide (TiSi), platinum silicide (PtSi), cobalt silicide (CoSi)₂) Or the like. A thickness of aboutTo aboutAnd a dopant concentration of about 1 x 10¹⁹Atom/cm³To about 2X 10²⁰Atom/cm³Is formed on the tungsten silicide layer 80. Polysilicon layer 78, silicide layer 80, and polysilicon layer 82 are referred to as conductive layer 84 or gate connection structure.

A thickness of aboutTo aboutIs formed on conductive layer 84. By way of example only, the following may be mentioned,dielectric layer 86 is about thickSilicon dioxide formed by wet oxidation of polysilicon layer 82 of conductive layer 84. A photoresist layer is patterned on oxide layer 86 to form a masking structure 88 having an opening 90 that exposes a portion of oxide layer 86. Masking structure 88 is also referred to as a mask.

Referring now to fig. 8, the exposed portions of oxide layer 86 are anisotropically etched and the portions of conductive layer 84 underlying the exposed portions of oxide layer 86 are anisotropically etched using, for example, reactive ion etching to reopen portions of trenches 38 and 39. After the anisotropic etch, portions 92 and 94 of oxide layer 86 remain in trenches 38 and 39, portions 100 and 102 of conductive layer 84 remain between oxide portion 92 and gate oxide 76 and between oxide portion 94 and gate oxide 76, respectively, and gaps 104 and 106 are formed on conductive layer portions 100 and 102, between oxide portion 92 and gate oxide 76, and between oxide portion 94 and gate oxide 76. A portion 108 of conductive layer 84 remains over a portion of protective layer 28. The portion 108 has sidewalls 110 and functions as a gate contact portion of the semiconductor component 10. Masking structure 88 is removed. Portions 92 and 94 function as dielectric barriers with opposing sides, while portions 100 and 102 function as gate conductors or gate electrodes. Gate oxide layer 76 and gate conductor 100 in trench 38 form gate structure 101. Similarly, gate oxide layer 76 and gate conductor 102 in trench 39 form gate structure 103.

Fig. 9 is a longitudinal cross-sectional view of fig. 8 along the length of trench 38 and shows a portion of gate structure 101 and polysilicon portion 50A within trench 38. Fig. 9 also shows that the gate electrode 101 is electrically connected to the conductor 84.

Referring now to FIG. 10, the thickness is aboutTo aboutOn dielectric barriers 92 and 94 of oxide layer 86, gate conductor 100 and 102 and conductive layer portions 50A and 52A in trenches 38 and 39 and between dielectric barrier 92 and gate oxide 76 and between dielectric barrier 94 and gate oxide 76. A thickness of aboutTo aboutSuch as, for example, a TEOS layer, is formed on dielectric layer 116. Dielectric layer 116 is also referred to as a pad oxide layer. By way of example, dielectric layer 116 has a thickness of aboutAnd TEOS layer 118 has a thickness of aboutIs measured.

Referring now to fig. 11, dielectric layers 118 and 116 are anisotropically etched, e.g., using a reactive ion etch, to form spacers 120 adjacent portion 92 of oxide layer 86, spacers 122 in gap 104 (shown in fig. 8), spacers 124 adjacent portion 94 of oxide layer 86, spacers 126 in gap 106 (shown in fig. 8), and spacers 128 adjacent sidewalls 110. Spacers 120 and 124 are laterally adjacent to the sides of dielectric barriers 92 and 94. In addition, spacers are formed at the ends of the slots 38 and 39. Spacers 129 are shown in fig. 12. Doped layers 130 of semiconductor material such as, for example, a dopant or impurity material concentration of about 1 x 10¹⁹Atom/cm³To about 5X 10²⁰Atom/cm³And has a thickness of aboutTo aboutIs formed on exposed portions of protective layer 28, gate contact portion 108 of conductive layer 84, spacers 128, and spacers 124 and 126. According to an embodiment of the present invention, the polysilicon layer 130 has an approximate thicknessAnd about 1X 10²⁰Atom/cm³Concentration of impurity material。

Fig. 12 is a longitudinal sectional view of fig. 11 before the semiconductor layer 130 is formed. Like fig. 9, the longitudinal cross-sectional view of fig. 12 is taken along the length of trench 38 and shows polysilicon portion 50A within trench 38 and a portion of gate structure 101. Figure 12 further shows oxide spacers 129 covering portions of gate structure 101 near the ends of trenches 38. It should be noted that the gate structure 103 in the trench 39 has a similar structure to the gate structure 101.

Referring now to fig. 13, polysilicon layer 130 is anisotropically etched using, for example, reactive ion etching, leaving doped polysilicon plugs 130A and 130B over portions 50A and 52A of conductive layer 84 in trenches 38 and 39, respectively. Plugs 130A and 130B are also referred to as conductive plugs. It should be noted that portions 50A and 130A cooperate to form field plate 55 in trench 38, while portions 52A and 130B cooperate to form field plate 57 in trench 39. It should further be noted that portions 50A and 52A are at the lower portions of slots 38 and 39, respectively, and portions 130A and 130B are at the upper portions of slots 38 and 39, respectively. Preferably, the exposed portions of the protective layer 28 are removed using anisotropic dry etching. Thus, a doped layer 138 of N-type conductivity is formed in the portion of epitaxial layer 20 not protected by protective layer 28, i.e., in the region of epitaxial layer 20 underlying the portion of dielectric layer 26 from which protective layer 28 was removed. According to an embodiment, the doped layer is passed through at about 1 × 10¹⁴Atom/cm²To about 5X 10¹⁶Atom/cm²And an implant energy of about 20keV to about 500keV is implanted with an N-type conductivity impurity material, such as, for example, phosphorus or arsenic, to form source regions 138. Source region 138 extends from surface 14 into epitaxial layer 20 a vertical distance that is less than the vertical distance trenches 38 and 39 extend into epitaxial layer 20.

Referring now to fig. 14, a layer of dielectric material 140 is formed over the exposed portions of dielectric layer 26, gate contact portion 108, spacers 128, and doped polysilicon plugs 130A and 130B. Dielectric layer 140 is commonly referred to as an interlayer dielectric ("ILD 0") layer. A photoresist layer is formed over ILD0 layer 140 and patterned to form a masking structure 142 having openings 144, 145, 146, 148, 149, and 150, wherein openings 144 and 145 expose portions of ILD0 layer 140 over polysilicon plugs 130A and 130B, opening 146 exposes portions of ILD0 layer 140 between trenches 38 and 39, opening 148 exposes portions of ILD0 layer 140 adjacent trench 38, opening 149 exposes portions of ILD0 layer 140 between trench 39 and spacer 128, and opening 150 exposes portions of ILD0 layer 140 over gate contact 108.

Referring now to fig. 15, the portions of ILD0 layer 140 exposed by openings 144-146 and 148-150 are anisotropically etched using a timed wet etch (timed etch) containing, for example, a dilute hydrofluoric acid solution to form tapered openings 154, 155, 156, 158, 159, and 160 in ILD0 layer 140. The portions of ILD0 layer 140 exposed by tapered openings 154-156 and 158-160 are anisotropically etched using, for example, reactive ion etching to form openings 164, 165, 166, 168, 169, and 170. Openings 164 and 165 extend into polysilicon slots 130A and 130B, opening 166 extends into the portion of epitaxial layer 20 between trenches 38 and 39, opening 168 extends into the portion of epitaxial layer 20 adjacent trench 38, opening 169 extends into the portion of epitaxial layer 20 between trench 39 and spacer 128, and opening 170 extends into a sub-portion of gate contact 108. An impurity material of P-type conductivity such as, for example, boron or indium, may be implanted into the polysilicon plugs 130A and 130B, the exposed portions of the epitaxial layer 20, and the exposed sub-portions of the gate contact portion 108. The impurity material implanted through openings 166, 168 and 169 form contact enhancement regions 176, 178 and 179, respectively. By way of example, the impurity material may be at about 1 × 10¹⁴Atom/cm²To about 5X 10¹⁶Atom/cm²And an implantation energy of about 10keV to about 100keV is implanted. Masking structure 142 is removed and epitaxial layer 20 is annealed using a rapid thermal anneal technique.

Referring now to fig. 16, a refractory metal layer (not shown) is conformally deposited over polysilicon plugs 130A and 130B, the exposed portions of epitaxial layer 20, the exposed regions of portion 108 of conductive layer 84, and over dielectric layer 140. By way of example, the refractory metal is about 100 a thickTo about 1,000Titanium (ii) of (i). The refractory metal is heated to a temperature of about 350 c to about 700 c. The heat treatment reacts the titanium with the silicon to form titanium silicide in all areas where the titanium is in contact with the silicon or polysilicon. Thus, titanium silicide layers 180 and 182 are formed from polysilicon plugs 130A and 130B, titanium silicide layer 184 is formed from the portion of epitaxial layer 20 between trenches 38 and 39, titanium silicide layer 186 is formed from the portion of epitaxial layer 20 adjacent to contact enhancement region 178, titanium silicide layer 189 is formed from the portion of epitaxial layer 20 adjacent to contact enhancement region 179, and titanium silicide layer 190 is formed from a sub-portion of gate contact 108.

A barrier layer is formed in contact with titanium silicide layers 180, 182, 184, 186, 189, and 190 and formed over ILD layer 140. Suitable materials for use as a barrier layer include titanium nitride, titanium tungsten, or the like. A metal layer, such as, for example, aluminum, is formed in contact with the barrier layer. A photoresist layer (not shown) is formed on the metal layer and patterned to expose portions of the metal layer. The exposed portions of the metal layer and portions of the barrier layer underlying the exposed portions of the metal layer are etched to form an electrical conductor. More specifically, silicide layers 180, 182, 184, 186, and 189 cooperate with portions 200, 202, 204, 206, and 208 of the barrier layer and a portion 210 of the metal layer to form a source contact, and silicide layer 190, a portion 212 of the barrier layer, and another portion 214 of the metal layer cooperate to form a gate contact. The source contact and the field plate contact share a common metallization system and may be referred to as a source electrode or contact structure 216. Conductor 218 is formed in contact with surface 16 and functions as the drain contact for power FET 10. Although bottom-side drain contact is shown in fig. 16, the present invention is not limited in this regard. For example, the drain electrode may be formed from the top side. Suitable metallization systems for conductor 218 include gold alloys, titanium-nickel-gold, titanium-nickel-silver, or the like. It should be further understood that the type of semiconductor device fabricated from semiconductor material 12 is not limited to a power FET or a trench FET.

Although preferred embodiments and methods have been disclosed herein, it will be apparent to those skilled in the art from this disclosure that changes or modifications can be made to the above-described embodiments and methods without departing from the spirit and scope of the invention. For example, the mask or mask structure may comprise a single mask or mask structure formed with a plurality of openings, or may be a plurality of masks or mask structures separated by one or more openings. In addition, the semiconductor device may be a vertical device or a lateral device. The present invention is intended to be limited only to the extent required by the appended claims and the rules and principles of applicable law.

Claims (10)

1. A method for manufacturing a semiconductor component, comprising the steps of:

providing a first semiconductor material having opposing first and second surfaces;

forming at least one trench in the first semiconductor material, the at least one trench having at least one sidewall;

forming a dielectric material in the at least one trench;

forming a second semiconductor material in the at least one trench, the dielectric material being between the second semiconductor material and the at least one sidewall of the at least one trench;

forming a portion of a gate structure within the at least one trench; and

forming a third semiconductor material within the at least one trench, the third semiconductor material being electrically isolated from the portion of the gate structure.

2. The method of claim 1, wherein the at least one sidewall comprises a first sidewall and a second sidewall, and wherein the step of forming a dielectric material in the at least one trench comprises forming a first portion of the dielectric material adjacent the first sidewall and forming a second portion of the dielectric material adjacent the second sidewall, and the step of forming a second semiconductor material in the at least one trench comprises forming the second semiconductor material between the first and second portions of the dielectric material.

3. The method of claim 2, further comprising the steps of:

removing a portion of the second semiconductor material between the first and second portions of the dielectric material to form a first conductive structure; and

removing sub-portions of the first and second portions of the dielectric material.

4. The method of claim 3, further comprising the steps of:

forming a dielectric material from portions of the first and second sidewalls of the at least one trench by oxidizing portions of the first semiconductor material exposed by the at least one trench;

forming a gate electrode adjacent the dielectric material formed by the first and second sidewalls of the at least one trench by depositing a conductive material adjacent the dielectric material formed by portions of the first and second sidewalls of the at least one trench;

forming a layer of dielectric material on the conductive material and removing portions of the layer of dielectric material to form first and second dielectric barriers laterally spaced apart from the first and second sidewalls of the at least one trench, wherein the first and second dielectric barriers have first and second sides; and

removing a portion of the conductive material between the first side of the first dielectric barrier and the first sidewall and removing a portion of the conductive material between the first side of the second dielectric barrier and the second sidewall.

5. The method of claim 4, further comprising the steps of:

a first dielectric material formed between the first dielectric barrier and the first sidewall;

a second dielectric material formed between the second dielectric barrier and the second sidewall;

forming a third dielectric material laterally adjacent to the second side of the first dielectric barrier;

forming a fourth dielectric material laterally adjacent to the second side of the second dielectric barrier; and

a conductive plug formed between the second sides of the first and second dielectric barriers and on the conductive structure.

6. A method for manufacturing a semiconductor component, comprising the steps of:

providing a semiconductor substrate having a first conductivity type;

forming an epitaxial layer having the first conductivity type and a first resistivity on the semiconductor substrate, the epitaxial layer having a major surface;

forming a trench in the epitaxial layer, the trench having first and second sidewalls and a second trench region above the first trench region;

forming a field plate in the first trench region;

forming a gate dielectric adjacent to the first sidewall in the second trench region;

forming a gate electrode in the second trench region, the gate electrode being adjacent to the gate dielectric;

forming a dielectric material adjacent to the gate electrode; and

forming a conductive plug in the second trench region, the conductive plug being electrically coupled to the field plate and electrically isolated from the gate electrode.

7. The method of claim 6, wherein the step of forming a field plate in the first region comprises forming a dielectric material adjacent the first and second sidewalls and forming the field plate adjacent the dielectric material, wherein the dielectric material electrically isolates the field plate from the first and second sidewalls.

8. The method of claim 7, further comprising the steps of:

forming a doped region in the epitaxial layer, the doped region extending from the surface into the epitaxial layer a distance less than a distance the trench extends into the epitaxial layer; and

and forming a gate connection structure on the epitaxial layer.

9. A semiconductor component, comprising:

a semiconductor substrate having a first conductivity type;

an epitaxial layer on the semiconductor substrate having the first conductivity type and a first resistivity, the epitaxial layer having a main surface;

a trench extending into the epitaxial layer from the major surface, the trench having a first sidewall and a second sidewall;

a conductive material within the first portion of the trench, the conductive material being spaced apart from the first and second sidewalls by a dielectric material;

a gate oxide adjacent to said first and second sidewalls of said second portion of said trench;

a gate electrode adjacent to the gate oxide;

a dielectric spacer within the second portion of the trench, the dielectric spacer adjacent to the gate electrode; and

additional conductive material spaced apart from the gate electrode by the dielectric spacer within the second portion of the trench.

10. The semiconductor component of claim 9, further comprising:

a gate contact over a portion of the epitaxial layer; and

a contact structure electrically coupled to the additional conductive material and the epitaxial layer.