HK1144492B - Semiconductor component and method of manufacture - Google Patents

Description

Semiconductor device and method of manufacturing the same

Technical Field

The present invention relates generally to semiconductor components and, more particularly, to power switching semiconductor components having edge termination structures.

Background

Metal oxide semiconductor field effect transistors ("MOSFETs") are a common type of power switching device. The MOSFET device includes a source region, a drain region, a channel region extending between the source region and the drain region, and a gate structure disposed adjacent to the channel region. The gate structure includes a conductive gate electrode layer disposed adjacent to and separated from the channel region by a thin dielectric layer. When a sufficiently strong voltage is applied to the gate structure to place the MOSFET device in an on-state, a conductive channel region is formed between the source and drain regions, allowing current to flow through the device. When the voltage applied to the gate is insufficient to cause channel formation, current does not flow and the MOSFET device is in an off state.

The current market for high voltage power switches is driven by two main parameters: breakdown voltage ("BVdss") and on-state resistance ("Rdson"). For certain applications, a minimum breakdown voltage is required, and in practice, designers are often able to meet BVdss specifications. However, this is often at the expense of Rdson. This tradeoff in performance is a major design challenge for manufacturers and users of high voltage power switching devices. Manufacturers of these devices often introduce termination structures such as thick field oxide along with diffused field limiting rings and channel stop regions to reduce device leakage, reduce unwanted parasitic effects, and enhance device breakdown performance. These methods solve the problem of maximum electric field relaxation of planar junctions. Each termination method has advantages and disadvantages, and designers attempt to minimize the negative aspects of the method while utilizing the positive aspects. Among these methods, the field limiting ring is the least costly one in terms of semiconductor device manufacturing investment, since the field limiting ring can often be formed using the same diffusion step used to form the PN junction of the main device. These guard rings reduce the electric field curvature while relying on the drift region to block a large amount of voltage.

Another method for reducing the maximum electric field of a planar junction is charge balancing, in which a charge balancing structure is formed in the drift region of the device in order to maintain a substantially uniform electric field within the drift region to increase the breakdown voltage of the device. A drawback of this approach is that the edge termination structure in the charge balance device occupies a large area to achieve charge balance at the interface between the active region and the termination region.

It would therefore be advantageous to have a semiconductor element and a method for manufacturing the semiconductor element having a termination structure that provides a higher breakdown voltage and facilitates the ability to maintain a high avalanche current at the interface between the active region and the termination region. It is further advantageous to manufacture the semiconductor component in a cost-effective manner.

Drawings

The invention will be better understood from a reading of the following detailed description taken in conjunction with the drawings in which like reference designators refer to like elements and in which:

fig. 1 is a cross-sectional view of a semiconductor component at an early stage of fabrication in accordance with an embodiment of the present invention;

fig. 2 is a cross-sectional view of the semiconductor element of fig. 1 at a later stage of fabrication;

fig. 3 is a cross-sectional view of the semiconductor element of fig. 2 at a later stage of fabrication;

fig. 4 is a cross-sectional view of the semiconductor element of fig. 3 at a later stage of fabrication;

fig. 5 is a cross-sectional view of the semiconductor element of fig. 4 at a later stage of fabrication;

fig. 6 is a cross-sectional view of the semiconductor element of fig. 5 at a later stage of fabrication;

fig. 7 is a cross-sectional view of the semiconductor element of fig. 6 at a later stage of fabrication;

fig. 8 is a cross-sectional view of the semiconductor element of fig. 7 at a later stage of fabrication;

fig. 9 is a cross-sectional view of the semiconductor element of fig. 8 at a later stage of fabrication;

fig. 10 is a cross-sectional view of the semiconductor element of fig. 9 at a later stage of fabrication;

fig. 11 is a cross-sectional view of the semiconductor element of fig. 10 at a later stage of fabrication;

fig. 12 is a cross-sectional view of the semiconductor element of fig. 11 at a later stage of fabrication;

fig. 13 is a cross-sectional view of the semiconductor element of fig. 12 at a later stage of fabrication;

FIG. 14 is a top view of the semiconductor device of FIGS. 5-13 during fabrication showing conductive material in the trenches electrically coupled together;

fig. 15 is a cross-sectional view of a semiconductor component during fabrication in accordance with another embodiment of the present invention; and

fig. 16 is a cross-sectional view of the semiconductor element of fig. 15 at a later stage of fabrication.

For simplicity of illustration and ease of understanding, elements in the various figures are not necessarily drawn to scale unless explicitly so stated. In some instances, well-known methods, procedures, components, and circuits have not been described in detail so as not to obscure the present disclosure. The following detailed description is merely exemplary in nature and is not intended to limit the disclosure of the present document and the use of the disclosed embodiments. Furthermore, there is no intention to be bound by any expressed or implied theory presented in the preceding paragraphs, including the title, technical field, background, or abstract.

Detailed Description

In general, the present invention provides a semiconductor component that may include a semiconductor device such as a field effect transistor, a trench field effect transistor, a vertical power field effect transistor, a power field effect transistor, or the like, integrated with an edge termination structure that includes a trench. It should be noted that the power fet may also be referred to as a vertical power device and the vertical fet may also be referred to as a power device. The semiconductor elements include semiconductor devices such as transistors fabricated or constructed of semiconductor materials, trench-based edge termination structures, and the like. The portion of semiconductor material used to fabricate the semiconductor device may be referred to as the semiconductor device region or device region and the portion of semiconductor material used to fabricate the trench-based edge termination structure may be referred to as the termination region or edge termination region. It should be noted that the field effect semiconductor device may be a top side drain contact device or a bottom side drain contact device. In semiconductor devices having top-side drain contacts or bottom-side drain contacts, the drain contacts may be made as regions of semiconductor material outside the semiconductor device region. This region may be referred to as a drain contact region.

In accordance with an embodiment of the present invention, the edge termination structure includes a trench having sidewalls and a bottom surface. A layer of dielectric material, such as oxide, is formed on the bottom surface and the portion of the sidewall adjacent the bottom surface, and an electrode is formed over the dielectric layer. A layer of dielectric material is formed over the electrode, over the dielectric material adjacent the bottom surface, and over the sidewalls of the mouth or opening adjacent the trench and an edge termination electrode is formed over the dielectric material. The electrode closer to the bottom surface is referred to as the source electrode because it is coupled to the source electrode of the semiconductor device, and the electrode closer to the opening of the trench is referred to as the floating electrode because it is electrically kept floating.

In accordance with another embodiment of the present invention, the edge termination structure includes at least two trenches, wherein each trench has a bottom surface and sidewalls. A source electrode and a floating electrode are formed in one of the trenches. In another trench, a layer of dielectric material is formed over the floor and sidewalls and over a portion of the surface of the semiconductor material, and an electrode is formed over the dielectric material and preferably electrically coupled to the semiconductor material.

Fig. 1 is a cross-sectional view of a portion of a semiconductor component 10 during fabrication in accordance with an embodiment of the present invention. Shown in fig. 1 is a semiconductor material 12 having opposing surfaces 14 and 16. Surface 14 is also referred to as a front or top surface and is located on a top side of semiconductor material 12, while surface 16 is also referred to as a bottom or back surface and is located on a bottom side of semiconductor material 12. In accordance with an embodiment of the present invention, semiconductor material 12 includes an epitaxial layer 20 disposed on a semiconductor substrate 18. Preferably, substrate 18 is silicon heavily doped with an N-type dopant or impurity material, while epitaxial layer 20 is silicon lightly doped with an N-type dopant. In an example of a semiconductor device having a 30 volt breakdown voltage, the resistivity of the substrate layer 18 may be less than about 0.01 ohm-centimeters ("Ω -cm") and preferably less than about 0.005 Ω -cm, while the resistivity of the epitaxial layer 20 may be greater than about 0.1 Ω -cm and preferably greater than about 0.2 Ω -cm. Substrate layer 18 provides a low resistance conductive path for current flowing through the power transistor and a low resistance electrical connection to a top drain conductor that may be formed on top surface 14 of substrate 12, a bottom drain conductor that may be formed on bottom surface 16, or both. It should be understood that the semiconductor material 12 is not limited to being an epitaxial layer on a semiconductor substrate. For example, semiconductor material 12 may be a semiconductor substrate. A region or layer doped with N-type dopants is referred to as having N-type conductivity or N-type conductivity and a region or layer doped with P-type dopants is referred to as having P-type conductivity or P-type conductivity.

Formed on epitaxial layer 20 or formed from epitaxial layer 20 to have a thickness of about 1,000 angstromsTo aboutA layer of dielectric material 22 of a thickness in the range. In accordance with an embodiment of the present invention, dielectric layer 22 is of a material having a dielectric constant of aboutA thickness of low temperature oxide ("LTO"). The type of dielectric material is not a limitation of the present invention. A layer of photoresist is patterned over oxide layer 22 to form masking structure 24 having masking members 26 and openings 28 that expose portions of oxide layer 22. The masking structure 24 is also referred to as a mask or an etch mask.

Referring now to fig. 2, the exposed portions of oxide layer 22 and the portions of epitaxial layer 20 underlying the exposed portions of oxide layer 22 are removed to form trenches 30, 36, 42, and 48 extending from surface 14 into epitaxial layer 20. Trenches 30 and 36 are formed in semiconductor device region 35 and trenches 42 and 48 are formed in termination or edge termination region 49. Thus, trenches 30 and 36 are referred to as device trenches and trenches 42 and 48 are referred to as termination trenches. Preferably, trenches 30 and 42 are equidistant from trench 36, i.e., the lateral distance between trenches 30 and 36 is substantially the same as the lateral distance between trenches 36 and 42. Trench 30 has sidewalls 32 and a floor 34, trench 36 has sidewalls 38 and a floor 40, trench 42 has sidewalls 44 and a floor 46, and trench 48 has sidewalls 50 and a floor 52. Preferably, trenches 30, 36, 42, and 48 are formed using an anisotropic etch, such as an anisotropic reactive ion etch ("RIE"). Sidewalls 32, 38, 44, and 50 may serve as vertical surfaces while bottom surfaces 34, 40, 46, and 52 may serve as horizontal surfaces. For clarity, the side walls 32, 38, 44, and 50 have been shown as being substantially perpendicular to the bottom surfaces 34, 40, 46, and 52. However, it should be understood that in practice, the floors 34, 40, 46, and 52, i.e., the bottoms of the trenches, may be rounded, while the sidewalls 32, 38, 44, and 50 may be slightly tapered. Although trenches 30, 36, 42, and 48 are shown as ending in an epitaxial layer, this is not a limitation of the present invention. For example, trenches 30, 36, 42, and 48 may end at substrate 18, or they may extend into substrate 18. The etching technique and the number of trenches formed in epitaxial layer 20 are not limitations of the present invention.

Referring now to FIG. 3, the sidewalls 32, 38, 44, and 50, or upper surfaces thereof, and the bottom surfaces 34, 40, 46, and 52, or upper surfaces thereof, are formed with a thickness of aboutTo aboutA sacrificial dielectric layer 54 of a thickness within a range. Preferably, the dielectric layer 54 is formed by thermal oxidation in a dry ambient. Dielectric layer 54 surrounds the bottom and top corners of trenches 30, 36, 42, and 48, removes any damage from sidewalls 32, 38, 44, and 50 and from floors 34, 40, 46, and 52 due to RIE processing, provides a high quality surface for subsequent oxidation steps, and widens trenches 30, 36, 42, and 48.

Referring now to fig. 4, sacrificial oxide layer 54 and oxide layer 22 are stripped from epitaxial layer 20The rest part. Formed on surface 14, sidewalls 32, 38, 44, and 50, and bottom surfaces 34, 40, 46, and 52, has a thickness of aboutTo aboutA layer of dielectric material 56 of a thickness in the range. It should be noted that the thickness of the dielectric layer 56 may be set in accordance with a desired breakdown voltage. For example, for a 30 volt BVDSS, the dielectric layer 56 has aboutTo aboutA thickness within the range. For example, the dielectric layer 56 is an oxide that may be formed by oxidation of exposed portions of the epitaxial layer 20, decomposition of ethyl orthosilicate, and the like. Formed on dielectric layer 56 having a thickness of aboutTo aboutA layer of polysilicon 58 of a thickness in the range and preferably filling the trenches 30, 36, 42, and 48. When the conductivity type of epitaxial layer 20 is N-type, the conductivity type of polysilicon layer 58 is preferably N-type. The polysilicon layer 58 is etched to have a height above the surface of the oxide layer 56 of aboutIs substantially planar. Alternatively, polysilicon layer 58 may be planarized using chemical mechanical planarization ("CMP"), resist planarization, oxidation, and etching techniques, and the like. A layer of photoresist is patterned over polysilicon layer 58 to form masking structure 60 having masking features 62 and openings 64 that expose portions of polysilicon layer 58. The masking structure 60 is also referred to as a mask or an etch mask.

Referring now to fig. 5, the exposed portion of polysilicon layer 58 is etched using, for example, reactive ion etching to expose a portion of oxide layer 56. The etch leaves portions 58A, 58B, and 58C of polysilicon layer 58 in trenches 30, 36, and 42, respectively. Portions 58A, 58B, and 58C are referred to as shield electrodes or device electrodes. It should be noted that shield electrodes 58A, 58B, and 58C will preferably be connected to the source electrode in a subsequent step. The etch also leaves portions 58D and 58E of polysilicon layer 58, where portions 58D and 58E are over the portion of oxide layer 56 that is above surface 14, and portion 58D is also in trench 48. Portion 58D is also referred to as a termination electrode, a shield electrode, or a shield. It should be noted that the portion 58E is an optional feature that may be omitted from the semiconductor element 10 and is referred to as a field stop (field stop) structure. When portion 58E is included, portion 58E can be connected to the substrate in a subsequent step and act as a field stop structure to prevent the formation of parasitic MOSFETs due to inversion of the silicon surface. Portions 58A and 58B are in semiconductor device region 35, portions 58C and 58D are in termination region 49, and field stop structure 58E is in drain contact region 59. Exposed portions of masking structure 60 and oxide layer 56 are removed to expose portions of surface 14 and portions 32A, 38A, and 42A of sidewalls 32, 38, and 42, respectively. For example, a wet etch is used to remove exposed portions of oxide layer 56, which undercuts the surface of polysilicon portions 58A, 58B, and 58C below. A sacrificial layer of dielectric material (not shown) is formed over exposed portions 32A, 38A, and 42A and over source electrodes 58A, 58B, 58C, shield electrode 58D, and field stop structure 58E. In accordance with an embodiment of the present invention, the sacrificial layer of dielectric material is about above the portions 32A, 38A, and 42ATo aboutA thickness in the range and about above the source electrodes 58A, 58B, 58C, the shield electrode 58D, and the field stop structure 58ETo aboutOxides of a thickness within the range. The thickness is greater over source electrodes 58A, 58B, 58C, and shield electrode 58D due to the heavy doping of polysilicon layer 58. The exact ratio of oxide thickness on polysilicon to oxide thickness on silicon depends on the polysilicon doping and oxidation conditions. For example, the thickness of the layer on sidewalls 32A, 38A, and 48A is aboutAnd the thickness of the dielectric layer on the source electrodes 58A, 58B, 58C, the shield electrode 58D, and the field stop structure 58E is aboutThe oxide on sidewalls 32A, 38A, and 42A is removed and the oxide on source electrodes 58A, 58B, 58C, shield electrode 58D, and portion 58E is thinned, leaving oxide layers 68A, 68B, 68C, 68D, and 68E on source electrodes 58A, 58B, 58C, shield electrode 58D, and field stop structure 58E, respectively.

Referring now to fig. 6, a layer of dielectric material 74 is formed from or on exposed portions 32A, 38A, and 42A; forming dielectric material layers 74A, 74B, 74C, 74D, and 74E from or over polysilicon portions 58A, 58B, 58C, 58D, and 58E, respectively; forming a layer of dielectric material 74F from or on the exposed portion of surface 14 between termination region 49 and drain contact region 59; and a layer of dielectric material 74G is formed on or in the portion of epitaxial layer 20 laterally adjacent drain region 59. Preferably, the material for dielectric layers 74, 74A, 74B, 74C, 74D, 74E, 74F, and 74G is an oxide, wherein the thickness of dielectric layer 74 is aboutTo aboutWithin range, and oxide layers 68A and 74A, oxide layers 68B and 74B, oxide layers 68C and 74C, oxide layers 68D and 74D, and oxidationThe total thickness of layers 68E and 74E is aboutTo aboutWithin the range. Note that oxide may not be formed on the rest of oxide layer 56. Formed on dielectric layers 74 and 74A-74G having a thickness of aboutTo aboutA layer of polysilicon 80 of a thickness in the range and which preferably fills trenches 30, 36, and 42.

Referring now to fig. 7, polysilicon layer 80 is etched to leave portions 80A, 80B, and 80C, wherein portions 80A, 80B, and 80C are within trenches 30, 36, and 42, respectively. Portions 80A and 80B serve as gate electrodes or device control electrodes. The gate electrode 80A and the portion of the dielectric layer 74 along the sidewalls 32 of the trench 30 form a gate structure, wherein the portion of the dielectric layer 74 between the gate electrode 80A and the sidewalls 32 acts as a gate dielectric or gate dielectric material, and the gate electrode 80B and the portion of the dielectric layer 74 along the sidewalls 38 of the trench 36 form a gate structure, wherein the portion of the dielectric layer 74 between the gate electrode 80B and the sidewalls 38 acts as a gate dielectric or gate dielectric material. Portion 80C forms a floating electrode. It should be noted that the etching may be accomplished by using a mask (not shown) that may be out of the plane of fig. 7 so as to leave a portion of the polysilicon layer 80 on the surface to facilitate the formation of the gate electrode connection. Since the dielectric layers 74A, 74B, 74C, 74D, 74E and the dielectric layers 68A, 68B, 68C, 68D, and 68E are preferably the same material, such as an oxide, and for clarity, the dielectric layers 74A and 68A are shown as a single layer, indicated by reference numeral 75A, the dielectric layers 74B and 68B are shown as a single layer, indicated by reference numeral 75B, the dielectric layers 74C and 68C are shown as a single layer, indicated by reference numeral 75C, the dielectric layers 74D and 68D are shown as a single layer, indicated by reference numeral 75D, and the dielectric layers 74E and 68E are shown as a single layer, indicated by reference numeral 75E.

Still referring to fig. 7, an opening 79 is formed in dielectric layer 75E to expose a portion of field stop structure 58E using techniques well known to those skilled in the art.

Referring now to fig. 8, a layer of photoresist is patterned over gate electrodes 80A and 80B of polysilicon layer 80 and exposed portions of dielectric layer 74 to form masking structure 90 having masking feature 92 and opening 94. Masking structure 90 is referred to as a high voltage implant mask or high voltage implant masking structure. Opening 94 exposes a portion of dielectric layer 74 and gate electrodes 80A and 80B of polysilicon layer 80. Impurity material of P-type conductivity is implanted into portions of epitaxial layer 20 laterally adjacent trenches 30 and 36, i.e., portions of epitaxial layer 20 not protected by masking members. The implant forms doped regions 98 that act as body regions. Impurity material is also implanted into the gate electrodes 80A and 80B. It should be noted that the formation of doped regions 98 may be accomplished using multiple implants having different energies to tailor the profile of the P-type impurity material in the body region. Impurity material is also implanted into the gate electrodes 80A and 80B. In accordance with an alternative embodiment, this implantation may be performed through the polysilicon layer 80 by implanting impurity material at high energy using the masking structure 90 as an implantation mask, followed by etching the polysilicon layer 80. According to another alternative embodiment, polysilicon layer 80 may be etched until its top surface is approximately above surface 14Impurity material of P-type conductivity is then implanted through the thinned polysilicon layer 80, followed by etching of the remainder of the polysilicon layer 80 until it is recessed into the trenches 30, 36, and 42. Masking structure 90 is removed and epitaxial layer 20 is annealed.

Referring now to fig. 9, a layer of photoresist is patterned over a portion of dielectric layer 74 and polysilicon layer 80 to form a masking structure 102 having a masking feature 104 and an opening 106. The masking structure 102 is referred to as a source/drain implant mask or source/drain implant masking structure. Opening 106 exposes a portion of dielectric layer 74, gate electrodes 80A and 80B, and dielectric layer 74G in drain contact region 59. Impurity material of N-type conductivity is implanted into portions of epitaxial layer 20 laterally adjacent trenches 30 and 36 and unprotected portions of epitaxial layer 20 in drain contact region 59, i.e., portions of epitaxial layer 20 not protected by masking members 102. The implant forms a doped region 108 that acts as a source region and a doped region 109 that acts as a drain contact region. Impurity material is also implanted into the gate electrodes 80A and 80B. Masking structure 102 is removed and doped regions 108 and 109 are annealed.

Referring now to fig. 10, gate electrodes 80A and 80B and floating gate electrode 80C are recessed below surface 14. Techniques for recessing the gate electrodes 80A and 80B and the floating gate electrode 80C are known to those skilled in the art. For example, an etching mask (not shown) similar to the masking structure 90 may be formed, the gate electrodes 80A and 80B and the floating gate electrode 80C are anisotropically etched, and then the etching mask is removed. Alternatively, electrodes 80A, 80B, and 80C may be recessed in a previous etching step.

Optionally, a layer of refractory metal (not shown) is conformally deposited over the gate electrodes 80A, 80B, the floating electrode 80C, the exposed portions of the field stop structure 58E, and over the dielectric layer 74. For example, the refractory metal is of a composition having a composition ofTo aboutCobalt in a range of thicknesses. The refractory metal is heated to a temperature in the range of about 450 ℃ to about 900 ℃. The heat treatment causes the cobalt to react with the silicon to form cobalt silicide in all areas where the cobalt contacts the polysilicon or silicon. As is known to those skilled in the art, a salicide layer is referred to as a salicide (salicide) layer. Thus, cobalt salicide layer 110 is formed from gate electrode 80A, cobalt salicide layer 112 is formed from gate electrode 80B, cobalt salicide layer 114 is formed from floating electrode 80C, and cobalt salicide layer 116 is formed from field stop structure 58E. It is understood that siliconThe type of compound is not a limitation of the present invention. For example, other suitable silicides include nickel silicide, platinum silicide, titanium silicide, and the like. As is understood by those skilled in the art, silicon is consumed during silicide formation and the amount of silicon consumed depends on the type of silicide formed.

Referring now to FIG. 11, a dielectric layer having a thickness of about 74F, 74G, and 75E is formed over salicide layers 110, 112, and 114, silicide layer 116, and dielectric layers 74, 74F, 74G, and 75ETo aboutA layer of dielectric material 124 of a thickness in the range. For example, the dielectric layer 124 is of the order ofOxide of (4) a thickness of (2). Dielectric layer 124 may be planarized using, for example, chemical mechanical planarization ("CMP"). Alternatively, dielectric layer 124 may be a layer of borophosphosilicate glass ("BPSG") that may be reflowed by heating. A layer of photoresist is patterned over dielectric layer 124 to form masking structure 126 having masking feature 128 and opening 130 that exposes a portion of dielectric layer 124. The masking structure 126 is also referred to as a mask or an etch mask. The exposed portions of dielectric layer 124 are anisotropically etched using, for example, reactive ion etching to form openings in dielectric layer 124 that expose portions of doped region 108 between trenches 30 and 36 and portions of doped region 108 laterally adjacent to trenches 30 and 36.

Turning now to fig. 12, masking structure 126 is removed. The exposed portions of epitaxial layer 20 are recessed to a depth slightly deeper than source regions 108 using techniques well known to those skilled in the art. Impurity material of P-type conductivity is implanted into exposed portions of epitaxial layer 20 laterally adjacent trenches 30 and 36, i.e., portions of epitaxial layer 20 not protected by dielectric layer 124, to form doped regions 132. The implant is then annealed. A layer of photoresist is patterned over dielectric layer 124 to form masking structure 146 having masking features 148 and openings 150. This masking structure is referred to as a contact etch mask or contact etch masking structure. The portion of the dielectric layer 124 exposed by the opening 150 is etched using techniques well known to those skilled in the art to expose a portion of the salicide layer 116, a portion of the non-floating stop electrode 58D, and a portion of the doped region 109 adjacent to the portion 58E. The masking structure 146 is removed. Although not shown, it is understood that silicide may be formed from a portion of the stop electrode 58D and the doped region 109 exposed by the opening 150.

Referring now to fig. 13, a barrier layer is formed on dielectric layer 124 in contact with doped regions 132, source/drain regions 108 and 109, and non-floating stop electrode 58D. Suitable materials for the barrier layer include titanium nitride, titanium tungsten, and the like. A metallization system (not shown), such as an aluminum-copper (AlCu) metallization system, is formed in contact with the barrier layer. A masking structure is formed over the AlCu metallization system to expose a portion of the AlCu metallization structure. The AlCu metallization structure is etched to form a source conductor 134 having source electrode portions 134A, 134B, 134C, and 134D, a top-side drain electrode 136, and a field stop electrode 140 electrically coupled to the top-side drain electrode 136 by a conductor 142. It should be noted that etching the AlCu metallization structure also forms gate electrodes (not shown) in contact with the silicide layers 110 and 112.

Fig. 14 is a top view of semiconductor component 10 during fabrication and illustrates that gate electrodes 80A and 80B are electrically coupled together. Note that the gate electrodes 80A and 80B are indicated by broken lines. More particularly, fig. 14 shows a conductive strip 160 electrically coupling gate electrodes 80A and 80B through filled vias 162 and 164. The vias are filled with a conductive material. For clarity, various layers have been omitted from FIG. 14 to better show that gate electrodes 80A and 80B are electrically connected to each other. It should be noted that source electrode portions 134A, 134B, and 134C are electrically coupled together by source conductor 134. Fig. 14 also shows a via 167 filled with conductive material contacting the non-floating termination electrode 58D and a via 169 filled with conductive material contacting the field stop structure 58E.

Referring again to fig. 13, MOSFET 170 is formed from semiconductor device region 35, wherein doped region 108 forms a source region, the portion of epitaxial layer 20 laterally adjacent trenches 30 and 36 and substrate 18 form a drain region, and electrodes 134A, 134B, and 134C serve as source electrodes. MOSFET 170 has a topside drain contact 136. Semiconductor component 10 includes an edge termination structure 172 that includes a floating termination electrode 80C formed over source electrode 58C and an edge termination structure 174 that includes a non-floating termination electrode or a non-floating shield 58D formed in termination region 49. As discussed above, the top-side drain contact 136 may be electrically coupled to the field stop electrode 140.

Fig. 15 is a cross-sectional view of a semiconductor component 200 during fabrication in accordance with another embodiment of the present invention. It is to be noted that the steps for manufacturing the semiconductor element 200 are similar to the steps for manufacturing the semiconductor element 10, except that the trench 48 of the semiconductor element 10 is not formed in the semiconductor element 200. Alternatively, a shield plate 202 (shown in fig. 16) is formed. Shown in fig. 15 is semiconductor substrate 12 having trenches 30, 36, and 42, dielectric layer 22, polysilicon layer 58, and masking structure 60. Steps for fabricating trenches 30, 36, and 42, dielectric layer 56, polysilicon layer 58, and masking structure 60 have been described with reference to fig. 1-4. However, masking structures similar to masking structure 24 of fig. 1 have been modified to prevent formation of trenches 48. Thus, there are no grooves 48 in fig. 15.

Fig. 16 is a cross-sectional view of the semiconductor element 200 of fig. 15 at a later stage of fabrication. Shown in fig. 16 is a MOSFET 170 formed in semiconductor device region 35 and a termination structure 202 formed in termination region 49. Semiconductor device 200 is similar to semiconductor device 10 except that semiconductor device 200 has a non-floating electrode 176 without a trench (trench-less) instead of termination structure 174, i.e., semiconductor device 200 does not have a non-floating termination electrode or floating shield 58D formed in the trench.

Now, it should be appreciated that a semiconductor element including a semiconductor device and an edge termination structure has been provided. An advantage of including an edge termination structure comprising a floating gate electrode such as floating gate electrode 80C is that the floating gate electrode assumes a voltage between that on the drain electrode and the source electrode, which reduces the electric field across the gate oxide. The reduction of the voltage on the gate oxide improves the reliability of the device. In addition, the termination structure according to embodiments of the present invention allows for a constant spacing between trenches, which enables the formation of reduced surface field ("RESURF") regions to reduce the on-resistance (rds (on)) of the semiconductor element. Furthermore, termination structures fabricated in accordance with embodiments of the present invention provide the advantage of low cost because they use fewer masking steps than other edge termination structures.

While certain preferred embodiments and methods have been disclosed herein, it should be apparent from the foregoing to those skilled in the art that variations and modifications of such embodiments and methods may be made without departing from the spirit and scope of the invention. It is intended that the invention be limited only to the extent required by the appended claims and the rules and principles of applicable law.

Claims (10)

1. A method for manufacturing a semiconductor element, comprising:

providing a semiconductor material having first and second major surfaces;

forming at least one semiconductor device in a first region of semiconductor material, wherein a first semiconductor device of the at least one semiconductor device has a first electrode;

forming a first termination trench in a second region of semiconductor material, the first termination trench having sidewalls and a floor;

forming a second electrode in a first portion of the first termination trench, the second electrode being electrically coupled to the first electrode and spaced apart from the sidewalls and the floor by a first dielectric material;

forming a second dielectric material over the second electrode and the sidewalls of the first termination trench; and

forming a third electrode in a second portion of the first termination trench, the third electrode being electrically isolated from the second electrode by the second dielectric material.

2. The method of claim 1, wherein forming the third electrode comprises forming the third electrode as a floating electrode.

3. The method of claim 1, wherein forming the first semiconductor device comprises forming at least one trench metal oxide semiconductor field effect transistor, and wherein forming the at least one trench metal oxide semiconductor field effect transistor comprises:

forming a plurality of trenches in the first region of semiconductor material, wherein a lateral distance between adjacent ones of the plurality of trenches in the first region and a lateral distance between a first termination trench in the second region adjacent to one of the plurality of first trenches in the first region are substantially the same;

forming a source electrode in each of the plurality of trenches in the first region;

forming a gate structure in each of the plurality of trenches; and

a drain electrode is formed in contact with the semiconductor material.

4. The method of claim 1, further comprising:

forming a second termination trench in a second region of the semiconductor material, the second termination trench having sidewalls and a floor;

forming a third dielectric material on sidewalls and a floor of the second termination trench; and

forming a fourth electrode in the second termination trench.

5. A semiconductor component, comprising:

a semiconductor material having first and second major surfaces;

one or more device trenches extending into the semiconductor material from the first major surface, each of the one or more device trenches having sidewalls and a floor;

a first termination trench extending into the semiconductor material from the first major surface;

a first layer of dielectric material disposed on portions of the bottom surface and sidewalls adjacent to the bottom surface of the one or more device trenches and the first termination trench;

a device electrode in each of the one or more device trenches and a first termination electrode on the first layer of dielectric material in the first termination trench;

a second layer of dielectric material disposed on each device electrode and on the first termination electrode; and

a device control electrode in each of the one or more device trenches and a floating electrode in the first termination trench, wherein each device control electrode is electrically isolated from each device electrode by the second layer of dielectric material and the floating electrode is electrically isolated from the first termination electrode by the second layer of dielectric material.

6. The semiconductor component of claim 5, wherein the one or more device trenches include a first device trench and a second device trench, wherein a lateral distance between the first device trench and the second device trench of the one or more device trenches is substantially equal to a lateral distance between the second device trench and the first termination trench of the one or more device trenches.

7. The semiconductor component of claim 5, further comprising:

a second termination trench extending into the semiconductor material from the first major surface, the second termination trench having a floor and sidewalls;

a portion of a first layer of dielectric material disposed on a bottom surface and sidewalls of the second termination trench; and

a second termination electrode on the first layer of dielectric material in the second termination trench.

8. A semiconductor component, comprising:

a semiconductor material having a device region, a termination region, and first and second major surfaces;

a field effect transistor formed in the device region; and

a first termination structure formed in the termination region, the first termination structure comprising:

a first termination trench extending into the semiconductor material from the first major surface, the first termination trench having first and second portions;

a first layer of dielectric material on the bottom and sidewalls in a first portion of the first termination trench;

a first termination electrode on the first layer of dielectric material;

a second layer of dielectric material on the first termination electrode and on sidewalls in a second portion of the first termination trench; and

a floating electrode on the second layer of dielectric material.

9. The semiconductor element of claim 8, wherein the field effect transistor comprises:

one or more trenches extending into the semiconductor material from the first major surface, wherein each of the one or more trenches has first and second portions;

a first layer of dielectric material on the bottom and sidewalls in the first portion of each of the one or more trenches;

a source electrode on the first layer of dielectric material;

a second layer of dielectric material on the source electrode;

a gate dielectric material on sidewalls in the second portion of each of the one or more trenches; and

a gate electrode on the gate dielectric material in each of the one or more trenches.

10. The semiconductor component of claim 8, further comprising:

a second termination structure formed in the termination region, the second termination structure comprising:

a second termination trench extending from the first major surface into the semiconductor material;

a first layer of dielectric material on a bottom surface and sidewalls of the second termination trench; and

a third termination electrode on the first layer of dielectric material.