HK1146330B - Semiconductor component and method of manufacture - Google Patents

Description

Semiconductor device and method for manufacturing the same

Technical Field

The present invention relates generally to semiconductor components, and more particularly to power switching semiconductor components.

Background

Metal oxide semiconductor field effect transistors ("MOSFETs") are a common type of power switching device. The MOSFET device includes a source region, a drain region, a channel region extending between the source region and the drain region, and a gate structure disposed adjacent to the channel region. The gate structure includes a conductive gate electrode layer disposed adjacent to and separated from the channel region by a thin dielectric layer. When a voltage of sufficient strength is applied to the gate structure to place the MOSFET device in an on-state, a conductive channel region is formed between the source and drain regions, thereby allowing current to flow through the device. When the voltage applied to the gate is insufficient to cause formation of the channel, no current flows and the MOSFET device is in an off state. The MOSFETs may be P-channel field effect transistors, N-channel field effect transistors, depletion mode devices, etc., as understood by those skilled in the art.

Today's market for high voltage power switches is mainly driven by two main factors: breakdown voltage ("BVdss") and on-resistance ("Rdson"). Minimum breakdown voltage is required for a particular application and in practice designers are often able to meet BVdss specifications. However, this is often at the cost of Rdson. This performance trade-off is a major design challenge for manufacturers and users of high voltage power switching devices. Another challenge arises because power MOSFET devices have an intrinsic P-N diode between a P-type conductivity body region (body region) and an N-type conductivity epitaxial region. The intrinsic P-N diode is turned on under certain operating conditions and stores charge on the P-N junction. When a sudden reverse bias is applied to the P-N diode, the stored charge produces a negative current until the charge is completely depleted. The time for the charge to drain is called the reverse recovery time ("Trr") and this time delays the switching speed of the power MOSFET device. In addition, the stored charge ("Qrr") also causes a loss in the switching voltage level due to the peak reverse recovery current ("Irr") and reverse recovery time.

One technique to reduce Rdson and increase switching speed is to form trench gate structures (trench gate structures) and field plates in the same trench, where the trench gate structures are located above the field plates in the trench. The trench gate is connected to a source. A disadvantage of this arrangement is that complicated and expensive processing techniques are employed.

It would therefore be advantageous to have a semiconductor component with a lower Rdson while having a higher breakdown voltage and lower switching losses, i.e. low Qrr losses, and a method of manufacturing such a semiconductor component. For semiconductor components, cost-effective manufacturing is more advantageous.

Disclosure of Invention

According to an aspect of the present invention, there is provided a method for manufacturing a semiconductor element, comprising the steps of: providing a semiconductor material having a first major surface and a second major surface and having a body region; forming a first trench in the semiconductor material, the first trench having at least one sidewall; forming a gate structure in a portion of the first trench; forming a source region adjacent to the first trench; forming a second trench in the semiconductor material, the second trench extending through a portion of the source region and having sidewalls; forming a conductive material in a portion of the second trench; and forming self-aligned electrical connections that electrically connect the conductive material in the second trenches with the source and body regions.

According to an aspect of the present invention, there is provided a method for manufacturing a semiconductor element, comprising the steps of: providing a semiconductor material; forming a first trench in the semiconductor material; forming a gate structure in the first trench; forming a doped region of a first conductivity type in a portion of the semiconductor material adjacent to the first trench; forming a field plate adjacent the first trench, the field plate extending into the doped region; and forming self-aligned electrical contacts to the doped region and the field plate.

According to an aspect of the present invention, there is provided a semiconductor element including: a semiconductor material having a first major surface and a second major surface; a gate structure extending into the semiconductor material; a source region adjacent to the gate structure; a field plate extending through the source region; and a self-aligned contact contacting the field plate and the source region.

Drawings

The present invention will be better understood from the following detailed description taken in conjunction with the accompanying drawings, in which like reference characters designate like elements, and in which:

fig. 1 is a cross-sectional view of a semiconductor component at an early stage of fabrication taken along the region indicated by section line 1-1 in fig. 18, in accordance with an embodiment of the present invention;

fig. 2 is a cross-sectional view of the semiconductor device of fig. 1 at a later stage of fabrication;

fig. 3 is a cross-sectional view of the semiconductor device of fig. 2 at a later stage of fabrication;

fig. 4 is a cross-sectional view of the semiconductor device of fig. 3 at a later stage of fabrication;

fig. 5 is a cross-sectional view of the semiconductor device of fig. 4 at a later stage of fabrication;

fig. 6 is a cross-sectional view of the semiconductor device of fig. 5 at a later stage of fabrication;

fig. 7 is a cross-sectional view of the semiconductor device of fig. 6 at a later stage of fabrication;

fig. 8 is a cross-sectional view of the semiconductor device of fig. 7 at a later stage of fabrication;

fig. 9 is a cross-sectional view of the semiconductor device of fig. 8 at a later stage of fabrication;

fig. 10 is a cross-sectional view of the semiconductor device of fig. 9 at a later stage of fabrication;

fig. 11 is a cross-sectional view of the semiconductor device of fig. 10 at a later stage of fabrication;

fig. 12 is a cross-sectional view of the semiconductor device of fig. 11 at a later stage of fabrication;

fig. 13 is a cross-sectional view of the semiconductor device of fig. 12 at a later stage of fabrication;

fig. 14 is a cross-sectional view of the semiconductor device of fig. 13 at a later stage of fabrication;

fig. 15 is a cross-sectional view of the semiconductor device of fig. 14 at a later stage of fabrication;

fig. 16 is a cross-sectional view of the semiconductor device of fig. 15 at a later stage of fabrication;

fig. 17 is a cross-sectional view of the semiconductor device of fig. 16 at a later stage of fabrication; and

fig. 18 is a plan view of the semiconductor element shown in fig. 17.

Detailed Description

Mainly, the present invention provides a semiconductor element comprising a field plate and a semiconductor device, such as a field effect transistor or a trench field effect transistor (trench field effect transistor), a vertical power field effect transistor, a power field effect transistor, or a combination thereof. It should be noted that a power field effect transistor is also referred to as a vertical power device, and a vertical field effect transistor is also referred to as a power device. According to an embodiment, the semiconductor element is made by providing a semiconductor material, preferably comprising an epitaxial layer having a body region formed on a substrate. A gate trench is formed in the semiconductor material and extends through the body region. A gate structure is formed in the gate trench. A source region is formed in a portion of the epitaxial layer laterally adjacent to the gate trench. A separate field plate trench having sidewalls and a bottom is formed in the semiconductor material and extends through the source and body regions. The conductive material is formed in the field plate trench and is separated from the sidewalls of the field plate trench by a layer of dielectric material. Self-aligned, integrated or integrated electrical contacts are formed to the body region, the source region and the trench field plate. Since the electrical contacts are self-aligned integral structures, they reduce the size of the transistors that make up the semiconductor element.

According to another embodiment, a semiconductor component includes a gate trench including a gate structure and a separate field plate trench including a field plate. The body region is between the gate trench and the field plate trench, and the source region is in the body region. Self-aligned, bonded together or integrated contacts contact the body region, source region, and field plate.

Fig. 1 is a cross-sectional view of a portion of a semiconductor component 10 during fabrication according to an embodiment of the present invention. It should be noted that the cross-sectional view shown in fig. 1 is taken along the area indicated by section line 1-1 shown in fig. 18, but at an earlier stage of manufacture than that shown in fig. 18. Shown in fig. 1 is a semiconductor material 12 having opposing surfaces 14 and 16. Surface 14 is also referred to as a front or top surface and surface 16 is also referred to as a bottom or back surface. According to an embodiment, semiconductor material 12 includes an epitaxial layer 20 disposed on a semiconductor substrate 18. Preferably, substrate 18 is silicon heavily doped with an N-type dopant or impurity material, while epitaxial layer 20 is silicon lightly doped with an N-type dopant. The substrate layer 18 may have a resistivity of less than about 0.01 ohm-cm (Ω -cm), while the epitaxial layer 20 may have a resistivity of greater than about 0.1 Ω -cm. Substrate layer 18 provides a low resistance conductive path for current flowing through the power transistor and provides a low resistance electrical connection to a bottom drain conductor (drain conductor), a top drain conductor, or both conductors formed on bottom surface 16 of semiconductor material 12. A region or layer doped with an N-type dopant is referred to as a region having N-type conductivity or an N-conductivity type, while a region or layer doped with a P-type dopant is referred to as a region having P-type conductivity or a P-conductivity type. The N-type dopant is also referred to as an N-type impurity material, and the P-type dopant is also referred to as a P-type impurity material.

A layer of dielectric material 26 is formed on epitaxial layer 20 or from epitaxial layer 20. According to one embodiment, the material of dielectric layer 26 is about 200 angstroms thickTo aboutSilica in the range. Techniques for forming silicon dioxide layer 26 are well known to those skilled in the art. An implant mask (not shown) is formed over dielectric layer 26. By way of example, the implantation mask is a photoresist having an opening that exposes a portion of dielectric layer 26. A P-type conductivity doped layer (not shown) is formed in epitaxial layer 20. The doped layer may be formed by implanting an impurity material such as, for example, boron into the epitaxial layer 20. Boron may be present at about 1 × 10¹³Ions per square centimeter (ions/cm)²) To about 1X 10¹⁴Ion/cm²A dose in the range and an implant energy implant in the range of about 100 kilo electron volts (keV) to about 400 keV. The technique of forming the doped layer is not limited to the implantation technique. The mask structure is removed.

A protective layer 28 is formed over dielectric layer 26. The protective layer 28 may be about 500 a thickTo aboutSilicon nitride in the range. According to one embodiment, dielectric layer 26 has a thickness of aboutAnd the protective layer 28 has a thickness of aboutIs measured. Preferably, the materials of layer 26 and layer 28 are selected such that protective layer 28 limits oxygen diffusion and thus prevents the underlying layers from being oxidized. Although the protective layer 28 is shown as a single layer of material, it may be a multi-layer structure of different material types. The epitaxial layer 20 is annealed by heating to a temperature in the range of about 1,000 degrees celsius (c) to about 1,200 c. Annealing the epitaxial layer 20 drives the impurity material of the doped layer to form a doped region 30, the doped region 30 also being referred to as a body region.

A thickness of aboutTo aboutA layer of dielectric material 32 is formed over the protective layer 28. The dielectric layer 32 serves as a hard mask (hardmark). By way of example, dielectric material layer 32 is formed from a thickness of aboutTetraethylorthosilicate (TEOS) to form an oxide. The oxide layer formed by the decomposition of TEOS is referred to as a TEOS layer. Alternatively, TEOS layer 32 may be referred to as a hard mask layer or a TEOS hard mask layer. A photoresist layer is patterned over the TEOS layer 32 to form a masking structure 33 having masking members 34 and openings 36 exposing portions of the TEOS layer 32. The mask structure 34 is also referred to as an etch mask. The exposed portions of TEOS layer 32 are removed to form openings 38 that expose portions of protective layer 28. The masking structure 33 is removed.

Referring now to FIG. 2, exposed by removing protective layer 28Trenches 40 and 40A having sidewalls 42 and a bottom 44 are formed in epitaxial layer 20 by removing portions of dielectric layer 26 and portions of epitaxial layer 20 underlying the exposed portions of protective layer 28. It should be noted that for clarity, reference character "a" has been appended to the trench laterally spaced from the body region 30. Although the trench 40A is similar to the trench 40, the trench 40A serves as a part of a gate contact. Portions of layers 28, 26 and 20 may be removed using anisotropic etching techniques such as, for example, reactive ion etching. Although trenches 40 and 40A are shown as terminating in epitaxial layer 20, this is not a limitation of the present invention. For example, trenches 40 and 40A may extend into substrate 18. The etching technique, the number of trenches, and the shape of the trenches formed in epitaxial layer 20 are not limitations of the present invention. The TEOS layer 32 is removed, for example, by wet stripping techniques (wet stripping techniques). Preferably, the thickness is aboutTo aboutA sacrificial oxide layer (not shown) is formed within the confines of trenches 40 and 40A on sidewalls 42 and bottom 44. By way of example, the sacrificial oxide layer has a thickness of aboutIs measured. The sacrificial oxide layer is removed using a dilute hydrofluoric acid solution, exposing sidewalls 42 and bottom 44 of trenches 40 and 40A. Gate dielectric material is formed on sidewalls 42 and bottom 44 of trenches 40 and 40A. Preferably, the gate dielectric material 46 is about thickTo aboutOxides within the range. It should be noted that the width of the openings in the protective layer 28 may be in the range of about 0.2 micrometers (μm) to about 1.0 μm, as indicated by arrows 48, while the spacing or distance between adjacent openings in the protective layer 28 is in the range of about 0.8 μm to about 3.0 μm, depending on the applicationThe ideal operating voltage for the device is indicated by arrow 50.

Referring now to FIG. 3, a layer of conductive material such as, for example, at about thicknessTo aboutPolysilicon 52 in the range is formed on gate oxide layer 46 and over the remaining portion of silicon nitride protective layer 28. For clarity, the remaining portions of silicon nitride protective layer 28 are collectively referred to as silicon nitride protective layer 28 or protective layer 28. By way of example, the polysilicon layer 52 has an approximate thicknessAnd doped with an N-type impurity material, such as phosphorus. Alternatively, the polysilicon 52 is doped with a P-type impurity material such as, for example, arsenic.

Referring now to fig. 4, polysilicon layer 52 is anisotropically etched to form spacers 54 over portions of gate oxide layer 46 along sidewalls 42. Polysilicon spacers 54 and gate oxide layer 46 form a gate structure. A thickness of aboutTo aboutA layer of dielectric material 56 is formed within the confines of polysilicon spacer 54, on the portion of gate oxide layer 46 overlying bottom 44, and overlying silicon nitride protective layer 28. According to one embodiment, dielectric layer 56 is approximately thickSilicon nitride of (2).

Referring now to fig. 5, silicon nitride layer 56 is anisotropically etched to form spacers 58 over polysilicon spacers 54. Anisotropically etchThe techniques for crystalline silicon and silicon nitride layers are well known to those skilled in the art. A thickness of aboutTo aboutA layer of dielectric material in the field is grown over the areas not protected by the nitride. By way of example, the dielectric material layer is an oxide formed by oxidation in a wet ambient that thickens the dielectric material above the bottom 44. The thickened oxide layer above the base 44 is identified by reference numeral 60.

Referring now to fig. 6, protective layer 28 is removed from oxide layer 26 using a wet etchant (wet etch) that selectively removes the material of protective layer 28, i.e., removes silicon nitride when protective layer 28 is silicon nitride. In addition, the wet etchant also removes the silicon nitride spacers 58. A layer of low resistance material 62 is formed in trenches 40 and 40A and on top of dielectric layer 46 using, for example, Chemical Vapor Deposition (CVD). Preferably, the low resistance material is a refractory metal silicide such as, for example, tungsten silicide.

Referring now to fig. 7, the tungsten silicide layer 62 is etched away, leaving tungsten silicide plugs 64 in the trenches 40 and 40A. A photoresist layer is patterned over tungsten suicide plugs 64, oxide layer 26, and exposed portions of polysilicon spacers 54 and gate dielectric layer 46 to form a masking structure 66 having masking members 68 and openings 70 that expose portions of oxide layer 26. The mask structure 66 is also referred to as an implantation mask. A doped region or layer 72 of N-type conductivity is then formed in the portions of epitaxial layer 20 not protected by mask member 68, i.e., in the regions of epitaxial layer 20 underlying the portions of dielectric layer 26 exposed by openings 70. According to one embodiment, doped region 72 is formed by implanting an N-type conductivity impurity material such as, for example, at a dose of about 1 × 10¹⁴Atom/cm²To about 5X 10¹⁶Atom/cm²Phosphorus or arsenic in the range and implant energy in the range of about 20keV to about 500 keV. Doped region72 extend from the surface 14 into the epitaxial layer 20 a vertical distance less than the vertical distance that the body region 30 extends into the epitaxial layer 20, and said doped region 72 serves as a source region. Masking structure 66 is removed.

Referring now to FIG. 8, the thickness is aboutTo aboutA layer of dielectric material 74 is formed over oxide layer 26 and the exposed portions of gate dielectric layer 46, polysilicon spacers 54 and tungsten silicide plug 64. According to one embodiment, the material of dielectric layer 74 is approximately thickTEOS of (a). A thickness of aboutTo aboutA silicon nitride layer 76 in the field is formed over TEOS layer 74. Preferably, silicon nitride layer 76 has a thickness of aboutIs measured. A photoresist layer is patterned over silicon nitride layer 76 to form a masking structure 77 having a masking member 78 and an opening 80 that exposes a portion of silicon nitride layer 76. The mask structure 77 is also referred to as an etch mask.

Referring now to fig. 9, the exposed portions of silicon nitride layer 76 and portions of TEOS layer 74 underlying the exposed portions of silicon nitride layer 76 are removed to form openings that expose portions of epitaxial layer 20 between adjacent trenches 40. By way of example, an anisotropic reactive ion etch is used to remove portions of silicon nitride layer 76 and portions of TEOS layer 74. Alternatively, the anisotropic etch may be adjusted to leave a portion of TEOS layer 74 in the opening to serve as a shield for oxygenA (screen oxide). The masking structure 77 is removed. According to one embodiment, the dopant is doped by doping the N-type conductivity impurity material such as, for example, at a dose of about 1 x 10¹⁴Atom/cm²To about 5X 10¹⁶Atom/em²Phosphorus or arsenic having an implant energy in the range of about 5keV to about 30keV is implanted into source region 72 to form doped region 82. Doped region 82 extends from surface 14 into source region 72 a vertical distance less than the vertical distance that source region 72 extends into epitaxial layer 20, doped region 82 increasing the impurity material concentration of source region 72 and acting as an enhancement source region.

Still referring to FIG. 9, the thickness is aboutTo aboutA silicon nitride layer 84 is formed in-range on the exposed portions of epitaxial layer 20 and on silicon nitride layer 76. Preferably, the silicon nitride layer 84 has a thickness of aboutIs measured.

Referring now to fig. 10, silicon nitride layer 84 is anisotropically etched to form spacers 86 along silicon nitride layer 76 and TEOS layer 74. Trenches 90 having sidewalls 92 and a bottom 94 extending through body region 30 and epitaxial layer 20 are formed using an anisotropic etching technique such as, for example, reactive ion etching. Although trenches 90 are shown as extending through body region 30 and epitaxial layer 20 into substrate 18, this is not a limitation of the present invention. For example, trenches 90 may extend through body region 30 and terminate or terminate in epitaxial layer 20. Preferably, slots 90 are formed between adjacent slots 40. Thus, slots 90 alternate with slots 40. A thickness of aboutTo aboutDielectric material layer within range98 are formed on the bottom 94, along the sidewalls 92, along the silicon nitride spacers 86, and on the silicon nitride layer 76. A thickness of aboutTo aboutA conductive layer 100 is formed over the dielectric layer 98 in the field. By way of example, the material of the dielectric layer 98 within the trench 90 is about thickAnd conductive layer 100 is doped with a P-type impurity material, such as boron, and has a thickness of aboutOf polycrystalline silicon. Alternatively, the material of conductive layer 100 is polysilicon doped with an N-type impurity material, or it may be any number or combination of other conductive materials.

Referring now to fig. 11, polysilicon layer 100 is etched back to form polysilicon plugs 102 in trenches 90. It is noted that polysilicon plug 102 is separated from epitaxial layer 20 and doped regions 30, 72, and 82 by dielectric layer 98 and serves as a field plate.

Referring now to fig. 12, dielectric layer 98 is anisotropically etched with a wet etchant to recess portions of dielectric layer 98, thereby forming gaps 104 between polysilicon plugs 102 and doped regions 30, 72, and 82. Preferably, gap 104 extends perpendicularly from surface 14 to a portion of sidewall 92 laterally adjacent body region 30. Gap 104 exposes sidewalls of polysilicon plug 102 and portions of sidewalls 92.

Referring now to FIG. 13, the thickness is aboutTo aboutA polysilicon layer 106 is formed within the gap 104, over the polysilicon plug 102 and the silicon nitride layer 76, and adjacent the silicon nitride spacer 86. Polysilicon layer 106 may be undoped or doped with N-type conductivity or P-type conductivity impurity materials. The depth to which the gap 104 extends into the body region 30 is not a limitation of the present invention.

Referring now to fig. 14, polysilicon layer 106 is etched, leaving fingers or portions 108 in gaps 104. Portion 108 electrically connects the body region 30 to the field plate 102. Preferably, an anneal is performed to laterally diffuse impurity material from portion 108 into body region 30 and into polysilicon plug 102.

Referring now to fig. 15, the silicon nitride spacers 86 and the silicon nitride layer 76 adjacent to the silicon nitride spacers 86 are etched in preparation for forming the staggered stepped contact regions. It should be noted that forming the staggered step contact regions is optional. A photoresist layer is patterned over silicon nitride layer 76, polysilicon plugs 102, polysilicon fingers 108, and the alternating steps to form a mask structure 112 having mask members 114 and openings 116, openings 116 exposing portions of silicon nitride layer 76 over trenches 40A, i.e., over trenches laterally spaced from body region 30. The mask structure 112 is also referred to as an etch mask. The exposed portions of dielectric layer 76 and the portions of dielectric layer 74 underlying the exposed portions of dielectric layer 76 are anisotropically etched to expose tungsten suicide plugs 64 and polysilicon spacers 54 in trenches 40A. The mask structure 112 is removed.

Referring now to fig. 16, refractory metal 120 is conformally deposited over silicon nitride layer 76, the staggered step contact regions, enhanced source regions 82, polysilicon plugs 102, and polysilicon fingers 108. A layer of conductive material 122 is formed over the metal layer 120. By way of example, the refractory metal is a titanium-titanium nitride bilayer (titanium-titanium nitride bilayer), and the conductive layer 122 may be an aluminum alloy having a thickness in the range of about 0.4m to about 5 μm. A photoresist layer is patterned on the conductive layer 122 to form a mask structure 124 having a mask member 126 and an opening 128. The mask structure 124 is also referred to as an etch mask. Thus, portion 108 and conductive layers 120 and 122 form a self-aligned electrical connection or self-aligned electrical contact that electrically connects polysilicon plug or field plate 102 with body region 30 and source region 72.

Referring now to fig. 17, the exposed portion of the conductive material 122 and the portion of the refractory metal layer 120 underlying the exposed portion of the conductive material 122 are etched to electrically isolate a gate contact 130 from a source-body-field plate contact 132. The mask structure 124 is removed.

Fig. 18 is a top view of the semiconductor element 10 according to the embodiment of the present invention. Shown in fig. 18 are gate regions 132 alternating with source-body-field plate contacts 140. The gate region 132 extends to a gate contact 134. In addition, fig. 18 shows a slot termination region 142 and an edge seal contact region 144.

By now it should be appreciated that there has been provided a semiconductor element 10 having a trench gate structure and a field plate formed in a trench and a method for manufacturing the same. A trench gate structure and a trench for a field plate extend through the body region. Thus, the gate structure and the field plate are formed in separate trenches. Furthermore, a trench for the field plate extends through the source region. The field plate is electrically connected to the body region and the source region using a self-aligned conductive material. Because the source and body contacts are self-aligned within the field plate trenches and the conductive material is connected to the field plate, the body region, and the source region, they are also referred to as integral self-aligned contacts, integral self-aligned electrical contacts, bonded together self-aligned contacts, or bonded together self-aligned electrical contacts. An advantage of using an integral self-aligned contact is that it allows the formation of semiconductor elements with small geometries by forming vertical contact surfaces instead of lateral contact surfaces without employing complex or expensive processing steps.

Although preferred embodiments and methods are disclosed herein, it will be apparent to those skilled in the art from this disclosure that changes and modifications can be made to the above-described embodiments and methods without departing from the spirit and scope of the invention. For example, the semiconductor device may be a vertical device or a lateral device. It is intended that the invention be limited only to the extent required by the appended claims and the rules and principles of applicable law.

Claims (10)

1. A method for manufacturing a semiconductor element, comprising the steps of:

providing a semiconductor material having a first major surface and a second major surface and having a body region;

forming a first trench in the semiconductor material, the first trench having at least one sidewall;

forming a gate structure in a portion of the first trench;

forming a source region adjacent to the first trench;

forming a second trench in the semiconductor material, the second trench extending through a portion of the source region and having sidewalls;

forming a first dielectric material layer in the second trench;

forming a conductive material in a portion of the second trench, the conductive material being located over the first dielectric material layer in the second trench;

forming a gap between the semiconductor material and the conductive material in a portion of the second trench by removing the portion of the first dielectric material layer in the second trench;

forming a conductive structure in the gap; and

forming a self-aligned electrical connection in contact with the source region, the semiconductor material, the conductive structure in the gap, and the conductive material in the portion of the second trench to electrically connect the conductive material in the second trench with the source region and the body region.

2. The method of claim 1, wherein forming a conductive material in a portion of the second trench comprises: polysilicon is formed over the first layer of dielectric material.

3. The method of claim 2, wherein forming a conductive structure in the gap comprises: polysilicon is formed in the gap.

4. The method of claim 3, wherein the polysilicon in the gap is doped with an impurity material of the first conductivity type and the impurity material is laterally diffused from the polysilicon in the gap into the semiconductor material.

5. The method of claim 1, further comprising increasing a doping concentration of a portion of the source region, and wherein the step of forming a second trench comprises: the second trench is formed through the portion of the source region having the increased doping concentration.

6. A method for manufacturing a semiconductor element, comprising the steps of:

providing a semiconductor material;

forming a first trench in the semiconductor material;

forming a gate structure in the first trench;

forming a doped region of a first conductivity type in a portion of the semiconductor material adjacent to the first trench;

forming a source region in a portion of the doped region;

forming a field plate adjacent to the first trench, the field plate extending into the doped region, wherein forming the field plate comprises:

forming a second trench in the semiconductor material, the second trench having sidewalls;

forming a first layer of dielectric material over the sidewalls of the second trench; and

forming polysilicon over the sidewalls of the second trench;

recessing a portion of the first dielectric material layer to form a gap;

forming a conductive material in the gap; and

forming a self-aligned electrical connection with the source region, the semiconductor material, the conductive material in the gap, and the field plate contact.

7. The method of claim 6, wherein forming a self-aligned electrical connection to the source region, the semiconductor material, the conductive material in the gap, and the field plate contact comprises: the self-aligned electrical connection is formed as an ohmic contact.

8. The method of claim 7, the step of forming a conductive material in the gap comprising: polysilicon is formed in the gap and the concentration of the doped region of the first conductivity type is increased.

9. A semiconductor component, comprising:

a semiconductor material having a first major surface and a second major surface;

a gate structure extending into the semiconductor material, wherein the gate structure comprises:

a first trench extending into the semiconductor material from the first major surface, the first trench having sidewalls and a bottom;

a first dielectric material layer formed on sidewalls and a bottom of the first trench;

a first conductive material formed on the first dielectric material layer; and further comprising a source region adjacent to the first trench and extending from the first major surface into the semiconductor material;

a field plate extending through the source region, wherein the field plate comprises:

a second trench extending through the source region into the semiconductor material, the second trench having sidewalls and a bottom;

a second layer of dielectric material formed on portions of the sidewalls and over the bottom;

a second conductive material formed on a portion of the second dielectric material layer;

a gap filled with a third conductive material, the filled gap being between a portion of a sidewall of the second trench and the second conductive material; and

a fourth conductive material in electrical contact with the semiconductor material, the second conductive material, and the third conductive material; wherein the fourth conductive material serves as a self-aligned contact to the field plate and the source region.

10. The semiconductor element according to claim 9, further comprising:

a third trench extending into the semiconductor material from the first major surface, the third trench having sidewalls and a bottom;

the first dielectric material layer formed on the sidewalls and bottom of the third trench;

a first conductive material formed on the first dielectric material layer; the source region is adjacent to the third trench and extends into the semiconductor material from the first major surface; and wherein the second slot is between the first slot and the third slot.