HK1115240B - Semiconductor filter structure and method of manufacture - Google Patents

Description

Semiconductor filter structure and method of manufacture

Technical Field

The present invention relates generally to electronic devices, and more particularly to semiconductor device structures and methods of fabricating the same.

Background

Electronic filters are now used to suppress noise, reject unwanted signals, or otherwise manipulate the characteristics of the input signal in some way. Typical semiconductor-based filter designs include inductor, resistor and/or capacitor networks. Such networks are often placed together with discrete Transient Voltage Suppression (TVS) devices, such as Zener diodes (Zener diodes), to provide electrostatic discharge (ESD) protection in addition to signal processing. The capacitance division of the TVS device is typically used to further develop the filter characteristics.

An elliptical or Cauer filter is a type of filter design that utilizes inductors and capacitors. In certain applications, such as electromagnetic interference (EMI) or Universal Serial Bus (USB) filter applications, an elliptic filter is desirable because it has equal ripple (ripple) in both the pass and stop bands, sharp cut-off characteristics, low group delay characteristics for a given stop band, and superior stop band attenuation compared to other standard filter designs, such as Chebyshev filters.

One challenge facing semiconductor-based filter designers is providing efficient designs in as small a space as possible to meet the size requirements of some applications. This challenge is often difficult, especially when the filter design includes inductor and capacitor structures and TVS devices.

Therefore, to meet the above and other challenges, a structure and fabrication method is needed to improve the integration of passive components and TVS devices.

Drawings

FIG. 1 shows a schematic diagram of a prior art elliptical filter circuit; FIG. 2 shows a schematic diagram of a filter circuit according to an embodiment of the invention; FIG. 3 shows an enlarged plan view of a portion of a structure including a technical implementation of the filter circuit of FIG. 1 in accordance with the present invention; FIG. 4 shows an enlarged exploded view of a portion of the device shown in FIG. 3; FIG. 5 shows an enlarged cross-sectional view of a portion of the device of FIG. 3 with reference line 5-5; FIG. 6 shows an enlarged partial cross-sectional view of one embodiment of a device according to the present invention; FIG. 7 shows an enlarged partial cross-sectional view of an embodiment of a device according to another embodiment of the present invention; FIG. 8 shows an enlarged partial cross-sectional view of an embodiment of a device according to yet another embodiment of the present invention; FIG. 9 shows an enlarged partial cross-sectional view of an embodiment of a device according to yet another embodiment of the present invention; FIG. 10 shows an enlarged partial cross-sectional view of a portion of the device of FIG. 3 with reference line 10-10; fig. 11 illustrates an enlarged plan view of the device illustrated in fig. 6 and 7, in accordance with an embodiment of the present invention; fig. 12 shows an enlarged plan view of the device of fig. 6 and 7 according to another embodiment of the present invention; fig. 13 illustrates an enlarged plan view of the device illustrated in fig. 6 and 7, according to an additional embodiment of the present invention; fig. 14 shows an enlarged plan view of the device of fig. 6 and 7 according to yet another embodiment of the present invention; and FIG. 15 shows an enlarged plan view of the device of FIGS. 6 and 7 according to yet another embodiment of the present invention;

for simplicity and clarity of illustration, elements in the figures are not necessarily drawn to scale, and the same reference numbers in different figures denote the same elements. Moreover, descriptions and details of well-known steps and components are omitted for brevity of the description. As used herein, current carrying electrode means an element of a device that carries current through the device, such as a source or drain of an MOS transistor, or a collector or emitter of a bipolar transistor, or a cathode or anode of a diode; a control electrode denotes a cell of a device that controls the current through the device, such as the gate of a MOS transistor or the base of a bipolar transistor. Although these devices are explained herein as certain N-channel or P-channel devices, one of ordinary skill in the art will recognize that complementary devices are also possible in accordance with the present invention. For clarity of the drawing, the doped regions of the device structure typically have straight edges and precisely angled corners. However, it will be appreciated by those skilled in the art that, due to the diffusion and activation of dopants, typically the edges of the doped regions are not straight lines and the angles are not precise angles.

Detailed Description

Fig. 1 schematically depicts a prior art embodiment of a circuit representing an elliptic filter structure 215 having an input 201 and an output 203. The filter 215 includes an inductor 211 connected in parallel with the linear capacitor 207 to form a first resonant circuit. Inductor 212 is connected in parallel with linear capacitor 208 to form a second resonant circuit. A first discrete TVS device 237 is connected between the first terminal 226 of the inductor 211 and the common return terminal 209. A second discrete TVS device 238 is connected between terminal 209 and a common connection between the second terminal 227 of inductor 211 and the first terminal 229 of inductor 212. A third discrete TVS device 239 is connected between second terminal 228 and terminal 209 of inductor 12.

Fig. 2 schematically depicts an embodiment of a circuit representing an elliptic filter structure 15 according to an embodiment of the present invention having an input 101 and an output 103. The structure 15 comprises an inductor 11 connected in parallel with a floating capacitor 17 to form a first resonant circuit. Inductor 11 includes an input terminal 26 and an output terminal 27. Structure 15 further includes an inductor 12 in parallel with floating capacitors 18 and 19. Inductor 12 includes an input terminal 29 and an output terminal 28, with terminal 29 being a common connection with output terminal 27. First TVS device 337 is connected between input terminal 26 and common return terminal 109. A second TVS device 338 is connected between input terminal 29 and common return terminal 109, and a third TVS device 339 is connected between output terminal 28 and common return terminal 109.

Floating capacitor 17 comprises, for example, a first MOS capacitor and is merged or integrated with TVS device 337 into a single device or device 46 in accordance with the present invention. Floating capacitor 18 comprises, for example, a second MOS capacitor and is merged or integrated with TVS device 338 into a single device or device 43. Floating capacitor 19 comprises, for example, a third MOS capacitor and is merged or integrated with TVS device 339 into a single device or device 44. The capacitance of these devices is adjusted according to the output requirements or specifications of the filter or structure 15.

The following description refers to fig. 3, 4 and 5. Fig. 3 shows an enlarged plan view of a portion of an embodiment of a semiconductor device 10 according to the present invention, including structure 15 in fig. 2. The structure 15 is generally identified by an arrow. Devices 43, 44 and 46 are shown connected to inductors 11 and 12. In the present embodiment, the inductors 11 and 12 include a stacked or multi-layer structure. As will be appreciated by those skilled in the art, integrated semiconductor inductors such as inductor 11 or inductor 12, or combinations thereof, may be used to form several types of filters including Bessel, bandpass, Chebyschev and/or elliptic filters. It should be further understood that inductors 11 and 12 may comprise a single layer inductor. Fig. 4 shows an enlarged exploded view of a portion of the inductor structures 11 and 12 shown in fig. 3. Fig. 5 shows in a general manner an enlarged cross-sectional view of a portion of the first multilayer inductor 11 shown in fig. 3 with reference line 5-5. The cross-sectional view of fig. 5 shows pins 30, 31, 32, 33 and 34 through inductor 11 shown in fig. 3.

The inductor 11 is constituted by a first inductor element 14 and a second inductor element 13. A first inductor element 14 is formed overlying a first portion of the surface of substrate 37 and a second inductor element 13 is formed overlying element 14. The elements 14 are formed in a pattern that provides electromagnetic coupling between adjacent portions of the elements 14 such that the inductance of the elements 14 is greater than the inductance of a straight conductor. The element 13 overlays the element 14 in a similar pattern so that the pattern of the element 13 provides electromagnetic coupling between adjacent portions of the element 13 so that the inductance of the element 13 is greater than the inductance of a straight conductor. Further, the elements 13 and 14 are magnetically coupled to each other.

In addition, the pattern and close proximity of elements 14 and 13 provides electromagnetic coupling between elements 13 and 14 such that elements 13 and 14 form an inductance for inductor 11 that is greater than the sum of the discrete inductance of element 13 plus the discrete inductance of element 14. Typically, adjacent portions of elements 14 are separated by about one to six (1-6) microns and adjacent portions of elements 13 are separated by about one to ten (1-10) microns. To ensure adequate coupling therebetween, element 13 is typically about one-half to two (0.5-2) microns from element 14. To provide an electrical connection between the element 13 and the element 14, one end or terminal of the element 13 is electrically connected to one end or terminal of the element 14 at a node 16. The second terminal of element 14 serves as terminal 26 of inductor 11 and the second terminal of element 13 serves as terminal 27 of inductor 11.

The inductor 12 is constituted by a first inductor element 22 and a second inductor element 21. First inductor element 22 is formed overlying a second portion of the surface of substrate 37 and second inductor element 21 is formed overlying element 22. The elements 22 are formed in a pattern that provides electromagnetic coupling between adjacent portions of the elements 14 such that the inductance of the elements 22 is greater than the inductance of a straight conductor. The element 21 overlays the element 22 in a similar pattern so that the pattern of the element 21 provides electromagnetic coupling between adjacent portions of the element 21 so that the inductance of the element 21 is greater than the inductance of a straight conductor. In addition, the patterning and close-proximity overlay of elements 22 and 21 provides electromagnetic coupling between elements 22 and 21 such that elements 22 and 21 form an inductance for inductor 12 that is greater than the sum of the discrete inductance of element 21 plus the discrete inductance of element 22. To provide an electrical connection between element 22 and element 21, one end or terminal of element 21 is electrically connected to one end or terminal of element 22 at node 23. The second terminal of element 22 serves as terminal 28 of inductor 12 and the second terminal of element 21 serves as terminal 29 of inductor 12.

In one embodiment, elements 13 and 14 are formed in the shape of a square spiral. However, each of the elements 13 and 14 may be formed in other shapes as long as it provides mutual magnetic flux coupling between adjacent portions of the element 13 and mutual magnetic flux coupling between adjacent portions of the element 14 and between the elements 13 and 14. For example, elements 13 and 14 may be formed in a circular spiral, or an elongated spiral, or any known shape that provides magnetic flux coupling. In the preferred embodiment, element 14 begins at node 26 and extends in a clockwise direction over the surface of base 37 until it terminates at terminal 16. Element 13 begins at node 16 and extends in a clockwise direction to cover a portion of element 14 that is substantially the same radius as the corresponding portion of element 13 until it ends at terminal 27. Inductor 12 is similar in construction to inductor 11. Element 22 begins at node 23 and extends in a clockwise direction over the surface of substrate 37 until it ends at terminal 28. Element 21 begins at node 29 and extends in a clockwise direction over a similar portion of element 22 until it ends at terminal 23. The exploded view of fig. 4 helps illustrate the overlapping relationship between elements 13 and 14 and elements 21 and 22.

Referring to fig. 3 and 5, element 14 typically includes a conductor 41 and a capping dielectric 39. The element 13 typically includes a conductor 42 and a capping dielectric 40. Typically, conductors 41 and 42 are composed of a low resistance conductor material such as a metal in order to reduce series resistance. The materials used for conductors 41 and 42 typically have a resistivity no greater than about four to five (4-5) micro-ohms/cm. Typically, elements 13 and 14 are formed overlying a first portion of substrate 37. A dielectric 38 is typically formed on the surface of substrate 37 to electrically insulate conductor 11 from substrate 37. Conductors 41 are formed on the surface of dielectric 38 in the desired pattern of elements 14. For example, a mask may be applied to dielectric 38 and patterned to expose portions of dielectric 38 in which conductors 41 are formed. Alternatively, conductor 41 is formed using conventional photolithography and etching techniques, and a layer of conductive material is deposited overlying dielectric layer 38 and subsequently patterned. Thereafter, a dielectric 39 is formed to cover the conductor 41. Dielectric 39 may not be formed on conductor 41 where node 16 is formed. Conductor 42 is formed on the surface of dielectric 39 and dielectric 39 is coated on top of the top surface of conductor 41. Conductor 42 may also be formed on conductor 41 on the surface where node 16 is formed. Dielectric 40 may optionally be used to cover conductor 42 to electrically isolate conductor 42 from other elements of device 10.

Inductor 12 is formed in a similar manner as inductor 11. Element 22 includes a conductor similar to conductor 41 and a covering dielectric similar to dielectric 39. Element 21 includes a conductor similar to conductor 42 and a covering dielectric similar to dielectric 40. Node 23 is formed in a similar manner as node 16.

Fig. 6 illustrates a highly enlarged partial cross-sectional view of an integrated linear (i.e., voltage independent) floating capacitor or MOS capacitor structure or capacitor/TVS structure or device 91 suitable for use as devices 43, 44 and/or 46 in structure 15 in accordance with a first embodiment of the present invention. Device 81 is referred to as integrated because it is a single device that functions as both a capacitive element (i.e., a MOS gate diode) and a transient voltage element. Device 81 is said to be floating because both contacts of the capacitor (e.g., contact layers 69 and 76 described below) are insulated from ground or common return terminal 109. This supports certain filter or circuit designs such as elliptic filters.

Device 81 includes a semiconductor substrate or region 37 having, for example, a dopant concentration of about 1.0 x 10¹⁹atoms/cm³Of order of magnitude<100>A P-type conductive substrate. In one embodiment, substrate 37 comprises silicon. Alternatively, substrate 37 includes other semiconductor materials such as IV-IV or III-V materials. In addition, it should be understood that the term "semiconductor substrate" refers to a region of semiconductor material, which may include a semiconductor wafer, a region of semiconductor material formed within a semiconductor wafer, a layer of semiconductor material formed overlying a semiconductor wafer, or a layer of semiconductor material formed overlying an insulating layer or material.

A well, split well, doped or diffused region 72 is formed within region 37 and extends from major surface 84. In the present embodiment, the well region 72 has n-type conductivity and has a dopant concentration of about 1.0 × 10²⁰atoms/cm³Of the order of magnitude of (d). As an example, ion implantation and photomask techniques are used to form the split-well region 72. Alternatively, a hard mask process is used to form the split well regions 72. An insulating or passivation layer 67 comprising silicon dioxide, deposited oxide, nitride, spun-on silicon oxide (spin-on glass), combinations thereof, or the like is formed overlying major surface 84 and well region 72. An aperture 60 is then formed in a portion of the layer 67 over the split portion of the well region 72, and a passivation or capacitance layer 68 is formed within the aperture 60 and overlies the layer 67. Capacitive layer 68 comprises, for example, an oxide and has a thickness selected according to the desired capacitance/voltage characteristics of device 61. By way of example, when layer 68 comprises silicon oxide, it has a thickness of from about 0.005 microns to about 0.05 microns. It should be understood that layer 68 may also comprise other materials such as silicon nitride, tantalum pentoxide, barium strontium titanate, titanium dioxide, or combinations thereof, including combinations with silicon oxide or similar materials.

A first contact or conductive layer 69 is formed overlying layer 68 to provide one plate of the MOS capacitor and well region 72 provides the other plate. By way of example, the first contact layer 69 comprises a doped polycrystalline semiconductor material (e.g., doped)Hetero-poly crystalline silicon) or another conductive material and may comprise a silicide layer or comprise several different materials formed in a layered structure. In one embodiment, the first contact layer 69 includes a high dose phosphorous implant (e.g., 1.0 x 10)¹⁵atoms/cm²To about 1.0X 10¹⁶atoms/cm²) Doped about 0.4 microns to about 0.8 microns of polysilicon. Next, a second passivation layer 71 is formed overlying major surface 84 and includes, for example, about 0.5 micron of a deposited oxide, such as an oxide formed using tetraethyl orthosilicate (TEOS).

The apertures 73 and 74 are formed using conventional photoresist and etching techniques, with the aperture 73 covering a portion of the well region 72 and the aperture 74 covering a split portion of the well region 72. Next, a conductive layer, designed as a recessed (formed) contact layer 76 and 77, is formed in apertures 73 and 74 overlying major surface 84. By way of example, contact layers 76 and 77 comprise aluminum, an aluminum alloy, or another conductive material. In one embodiment, contact layers 76 and 77 comprise a 2.0 micron aluminum/silicon alloy.

Consistent with the present invention, device 81 has a split well region 72 that is discontinuous beneath layer 68. That is, the capacitor layer 68 adjoins or contacts both the region 37 and the well region 72 to form a MOS gate diode device. Expressed in another way, portions of the well region 72 are separated by portions of the region 37. Also consistent with the present invention, the split well region 72 forms both the plates of the capacitor element and the electrodes or junctions of the TVS element. In the present invention, the term "split-well region" means a doped well region, wherein a portion of the doped well region is discrete or discontinuous, so that a portion of the substrate 37, a portion of the doped region 272 (shown in figures 7 and 9), or a portion of the semiconductor layer 237 (shown in figure 8) is exposed within the well region, surrounded by the well region, partially bounded on one side by the well region, bounded on all sides by the well region, or surrounded on the major surface 84 by the well region. This is further illustrated in the plan views of the split well 72 in figures 11-15 below.

In addition, consistent with the present invention, the concentration of substrate 37 is selected so that the threshold voltage VT of the capacitor is positive,and the capacitance characteristic is substantially constant over a desired operating voltage range. For example, for gate-to-well voltages in the range of 3 volts and higher, the substrate 37 has a high doping concentration (e.g., a surface concentration greater than about 1.0 x 10¹⁸atoms/cm³) Will result in a constant capacitance gate-source (C)_GS) And (4) characteristics. Further consistent with the present invention, well region 72, which is electron or carrier rich, overlaps edges 181 and/or 182 of MOS gate 69, thereby ensuring a low impedance path to the channel that is formed under the MOS gate.

In another embodiment, well region 72 is formed to provide an approximate 3.0 x 10 by high dose phosphorous ion implantation¹⁹atoms/cm³Followed by high dose arsenic ion implantation to provide an about 5.0 x 10¹⁹atoms/cm³The peak concentration of (c). In an alternative embodiment, the order of ion implantation may be reversed. The injection chain provides an order of magnitude of about 8.0 x 10¹⁹atoms/cm³Net peak doping of. Consistent with the present invention, the implant chain reduces the series and contact resistance of the well region 72 by 90%, which enhances, for example, the Radio Frequency (RF) characteristics of the structure.

In device 81, the MOS capacitor formed by contact layer 69, layer 68, and a portion of well region 72 provides a floating capacitance element (e.g., capacitor 18, and/or 19 of fig. 2) for devices 43, 44, and/or 46, and the pn junction formed between well region 72 and substrate 37 provides a TVS element (e.g., diode 337, 338, and/or 339 of fig. 2) for devices 43, 44, and/or 46. Consistent with the present invention, because device 81 is integrated, it has a lower impedance, such as compared to prior art non-integrated devices.

In device 81, the well/substrate capacitor formed between split-well region 72 and substrate 37 forms a smaller area that allows for a smaller layout in some applications. However, if the design requires a larger well/substrate diode, device 81 only allows the area of the well to be increased without affecting the size of the MOS capacitor itself. An example of this feature is described more fully below in conjunction with fig. 11 and 12. Further, the area of the MOS capacitor in device 81 (i.e., the area of contact layer 69 and layer 68 in aperture 60) and well region 72 are independent, which provides more accurate control of capacitance/voltage characteristics in some applications.

Fig. 7 illustrates a highly enlarged partial cross-sectional view of an integrated linear (i.e., voltage independent) floating capacitor or MOS capacitor structure or capacitor/TVS structure or device 91 suitable for use as devices 43, 44 and/or 46 in structure 15 in accordance with a second embodiment of the present invention. Device 91 is similar to device 81 except that region 37 includes a lightly doped P-type region 237, which region 237 is formed overlying heavily doped P-type substrate 137.

In certain applications, such as where a MOS FET device is associated with the integrated MOS capacitor of the present invention, there are design challenges when highly doped region 37 is used by itself, as in device 81. For example, the P-type substrate 37 may result in a positive and order of magnitude high threshold voltage. Furthermore, heavy doping can affect the mobility of carriers in the channel region of a MOS FET device. Also, when the well region 72 is formed directly in the highly doped region 37, as in the device 81, the leakage current of the pn junction formed between these regions may be higher than desired, and the capacitance per unit area may also be higher than desired. In device 91, a pn junction of lower capacitance and lower leakage current is provided for use in applications requiring these characteristics.

In device 91, the junction between well region 72 and lightly doped region 237 acts more like a single-sided junction, with the junction capacitance controlled by the doping concentration and thickness of region 237. One constraint on the doping concentration and thickness of region 237 is that these variables be selected to support the desired breakdown voltage and ESD characteristics for the TVS device. The authors of the present invention have found that the device 91 according to the present invention reduces the unit capacitance (specific capacitance) by a factor of about 5-10. This allows more accurate tuning of the diode and floating MOS capacitor capacitances in a decoupled and independent manner, thereby increasing the freedom of design goals.

By way of example, substrate 137 includes a dopant concentration of approximately 1.0 × 10¹⁹atoms/cm³Of order of magnitude<100>A P-type conductive substrate. In one embodiment, substrate 137 comprises silicon. Alternatively, substrate 137 includes other semiconductor materials such as IV-IV or III-V materials. Layer 237 comprises a P-type layer, such as formed using epitaxial growth techniques, and has a doping concentration less than that of substrate 137. In one embodiment, the doping concentration of layer 237 is about 1.0 × 10¹⁵atoms/cm³To about 1.0X 10¹⁶atoms/cm³On the order of magnitude, and a thickness on the order of about one to ten microns. The doping concentration and thickness of layer 237 vary according to well-known principles depending on the desired breakdown voltage and ESD requirements.

An additional feature of layer 237 is the provision of a lightly doped n-type region 272 formed in major surface 84 beneath capacitor layer 68 and adjacent well region 72. Region 272 is optional and conveniently provided or set to control V_TTo a desired negative voltage to ensure a substantially constant MOS capacitance between zero and ten volts. In one embodiment, region 272 includes a peak concentration of about 1.0 × 10¹⁶atoms/cm³A doped region of phosphorus or arsenic of a magnitude.

Fig. 8 illustrates a highly enlarged partial cross-sectional view of an integrated linear (i.e., voltage independent) floating capacitor or MOS capacitor structure or capacitor/TVS structure or device 101 suitable for use as devices 43, 44 and/or 46 in structure 15 in accordance with a third embodiment of the present invention. Device 101 is similar to devices 81 and 91 except that well region 72 comprises a single-sided split well which overlaps only the edge 181 of the MOS capacitor and the edge 182 overlaps the semiconductor layer 237. In the present embodiment, the well region 72 where electrons are sufficient overlaps only the edge 181 of the MOS capacitor, thereby ensuring rapid supply of charges for the formation of a channel in the MOS capacitor. This in turn enables high frequency operation of the capacitor structure. The device 101 further illustrates an optional doped region 238 that is either n-type or p-type and is formed adjacent to at least a portion of the well region 72. In one embodiment, the optional doped region 238 extends through the layer 237 to the semiconductor substrate 137. The optional doped region 238 has a higher doping concentration than the semiconductor layer 237 and is configured to control, vary, or reduce a breakdown voltage or a clamping voltage of a junction between the well region 72 and the semiconductor layer 237.

Fig. 9 illustrates a highly enlarged partial cross-sectional view of an integrated linear (i.e., voltage independent) floating capacitor or MOS capacitor structure or capacitor/TVS structure or device 201 suitable for use as devices 43, 44 and/or 46 in structure 15 in accordance with a fourth embodiment of the present invention. The device 201 is similar to the device 101 and further includes an n-type region 272 formed at the major surface 84 beneath the MOS capacitor and adjoining the well region 72. In the present embodiment, the region 272 extends until it overlaps the edge 182 of the MOS capacitor. The device 201 further includes an optional doped region 239 formed adjacent to at least a portion of the well region 72. In this embodiment, the optional doped region 239 includes a p-type region with a higher doping concentration than the semiconductor layer 237. The optional doped region 239 is configured to control, vary, or reduce a breakdown voltage or a clamping voltage of a junction between the well region 72 and the semiconductor layer 237.

FIG. 10 illustrates a highly enlarged partial cross-sectional view of the device 10 of FIG. 3 with reference line 10-10 in accordance with the present invention. In this partial cross-sectional view, devices 46, 44 and 43 in the technical implementation of structure 15 shown in fig. 3 are shown as integrated device 91 shown in fig. 7 including optional doped region 272. In alternative embodiments, devices 46, 44, and/or 43 include device 81 shown in FIG. 6, device 101 shown in FIG. 8, and/or device 201 shown in FIG. 9.

Fig. 11 shows a plan view of an embodiment of devices 81 and 91 according to the invention. In this embodiment, split-well region 72 is lightly shaded to show that a portion of substrate 37 (or doped region 272 or semiconductor layer 237) is exposed in layer 67 through aperture 70. The well region 72 includes a ring-like portion 720 and a rectangular-like portion 721 that define the floating MOS capacitor elements of the devices 81 and 91, thereby providing a convenient structure for the electrode 76 (shown in fig. 6 and 7) to contact the well region 72 through the aperture 73 in the layers 67, 68 and 71 (shown in fig. 6 and 7). Examples of apertures 60 in layer 67 (shown in fig. 6 and 7) are shown to further define the floating MOS capacitor elements of devices 81 and 91. It should be understood that the portions 720 and 721 of the well region 72 may be formed of other shapes including square, polygon, circle, triangle, combinations thereof, or the like. In addition, portion 721 may be rounded.

Fig. 12 shows a plan view of another embodiment of devices 81 and 91 according to the present invention. This embodiment is similar to the embodiment shown in figure 11 except that the aperture 731 is larger than the aperture 73 of figure 11 and the portion 722 of the split-well region 72 is larger than the portion 721 of figure 11. In an embodiment of device 91, region 272 or semiconductor layer 237 is exposed in aperture 60 rather than substrate 37. Fig. 12 illustrates an advantage of the present invention because the area of the well-substrate diode or TVS device can be increased (e.g., the area of portion 722 is larger than the area of portion 721) without affecting the area of the MOS capacitor (portion 720). That is, the area of the floating MOS capacitor in the present invention is independent of the area of the well-substrate diode.

Fig. 13 shows a plan view of a further embodiment of devices 81 and 91 according to the invention. In the present embodiment, the shaded portion of the split well region 72 includes a rectangular portion 726 and a semicircular ring portion 727. In an embodiment of device 91, region 272 or semiconductor layer 237 is exposed in aperture 60 rather than substrate 37. The diameter 827 of the semicircular ring portion 727 is equal to the height 826 of the rectangular portion 726.

Fig. 14 shows a plan view of a further embodiment of devices 81 and 91 according to the invention. In this embodiment, the shaded portion of the split well region 72 includes a rectangular portion 726 and a semicircular ring portion 728. In an embodiment of device 91, region 272 or semiconductor layer 237 is exposed in aperture 60 rather than substrate 37. The diameter 828 of the semicircular ring portion 728 is less than the height 826 of the rectangular portion 726. That is, for rectangular portion 726, semi-circular ring portion 728 is inserted or embedded in non-coincident with it.

Fig. 15 shows a plan view of an additional embodiment of devices 81 and 91 according to the present invention. In the present embodiment, the hatched portion of the split well region 72 includes a semicircular ring portion 729 and a semicircular portion 730. In an embodiment of device 91, region 272 or semiconductor layer 237 is exposed in aperture 60 rather than substrate 37. Diameter 829 of semicircular ring section 729 is smaller than diameter 830 of semicircular section 730. That is, semi-circular ring portion 729 is inserted or embedded in non-coincident with semi-circular portion 731.

In view of the foregoing, it is apparent that there has been provided a structure and method of fabrication for an integrated floating capacitor/TVS device. The structure saves space, facilitates integration with other component parts in the construction of resonant structures such as elliptical filters, and provides performance characteristics comparable to or superior to prior art filter designs.

While the invention has been described and illustrated with reference to specific embodiments thereof, it is not intended that the invention be limited to these illustrative embodiments. Those skilled in the art will recognize that modifications and variations can be made without departing from the spirit of the invention. It is therefore intended to embrace all such changes and modifications that fall within the scope of the appended claims.

Claims (10)

1. A filter, comprising:

a semiconductor substrate of a first conductivity type and having a first doping concentration;

a semiconductor layer formed overlying the semiconductor substrate, the semiconductor layer being of a first conductivity type and having a second doping concentration less than the first doping concentration, the semiconductor layer having a first major surface;

a first floating capacitor device formed adjacent to the first major surface; and

a first transient voltage suppression device formed adjacent to the first major surface, wherein the first floating capacitor device and the first transient voltage suppression device share a first doped region of a second conductivity type formed in the semiconductor layer, and wherein the first doped region terminates at the first major surface such that the first floating capacitor device overlies a portion of the semiconductor layer and a portion of the first doped region.

2. The filter of claim 1 wherein the first doped region comprises a split-well region, the split-well region being split at the first major surface such that a portion of the semiconductor layer is surrounded by the split-well region.

3. The filter of claim 1, further comprising a first inductor, the first inductor overlying at least a portion of the semiconductor substrate.

4. A semiconductor filter comprising:

a semiconductor substrate of a first conductivity type and having a first doping concentration;

a semiconductor layer of the first conductivity type formed overlying the semiconductor substrate, wherein the semiconductor layer has a second doping concentration less than the first doping concentration; and

a first doped region of a second conductivity type opposite the first conductivity type formed in the semiconductor layer, wherein the first doped region is configured to form a TVS device with the semiconductor layer, and wherein the first doped region is further configured to form one plate of a floating MOS capacitor.

5. The semiconductor filter of claim 4, wherein said first doped region comprises a split-well region, wherein said floating MOS capacitor is contiguous with a portion of said semiconductor layer and further contiguous with a portion of said first doped region.

6. The semiconductor filter of claim 5, further comprising a second doped region of said second conductivity type formed in said semiconductor layer adjacent to said first doped region, wherein said second doped region is configured to control a threshold voltage of said floating MOS capacitor.

7. The semiconductor filter of claim 4, further comprising a first multilayer inductor covering at least a portion of the semiconductor substrate, the first multilayer inductor having a first terminal and a second terminal, the first multilayer inductor further having a first conductor and a second conductor and a first dielectric, the first conductor covering the portion of the semiconductor substrate, the second conductor covering at least a portion of the first conductor, the first dielectric disposed between the first conductor and the second conductor, wherein one of the first terminal and the second terminal is coupled to the floating MOS capacitor.

8. A method of forming a semiconductor filter, comprising the steps of:

providing a semiconductor substrate of a first conductivity type and a semiconductor layer of the first conductivity type formed overlying the semiconductor substrate and having a first major surface; and

forming a first doped region of a second conductivity type in said semiconductor layer, wherein said first doped region comprises a split well region, and wherein said first doped region is configured to form a TVS device with said semiconductor layer, and wherein said first doped region is further configured to form a plate of a floating MOS capacitor.

9. The method of claim 8, further comprising the steps of: forming a second doped region of the second conductivity type in the semiconductor layer adjacent to the first doped region, wherein the second doped region is configured to control a threshold voltage of the floating MOS capacitor.

10. The method of claim 8, further comprising the steps of: forming a first multilayer inductor overlying at least a portion of the semiconductor substrate, the first multilayer inductor having a first terminal and a second terminal, the first multilayer inductor further having a first conductor overlying the portion of the semiconductor substrate and a second conductor overlying at least a portion of the first conductor and a first dielectric disposed between the first conductor and the second conductor.