HK1091946B - Integrated semiconductor inductor and method therefor - Google Patents

Description

Integrated semiconductor inductor and method of forming the same

Technical Field

The present invention relates generally to electronic devices and, more particularly, to methods of forming semiconductor devices and structures.

Background

In the past, various methods and structures have been employed in the semiconductor industry to integrate filters into monolithic semiconductor devices. Typically, these filters are limited to simple pi filters comprising resistive and capacitive elements, or in some cases inductive and passive elements. An example of a pi-type filter is NUF6106 sold by ONSemiconductor of 5005 East McDowell Road of Phoenix Arizona. pi-type filters generally do not provide sufficient attenuation above the cut-off frequency of the filter. The filter comprising the inductor is typically a pi-type filter having a series inductor coupled in series with the pi-type filter. An example of such a filter is disclosed in U.S. patent application publication No. US 2003/0228848. Inductive filters typically have excessive loss (typically referred to as insertion loss) at frequencies above the filter cut-off frequency and often have undesirable group delay distortion.

It is therefore desirable to integrate filters onto monolithic semiconductor devices that have lower group delay distortion, lower insertion loss below the cutoff frequency, and higher loss above the cutoff frequency.

Disclosure of Invention

According to an aspect of the present invention, there is provided an integrated semiconductor inductor comprising: a semiconductor substrate; a first multilayer inductor overlying at least a portion of the semiconductor substrate, the first multilayer inductor having a first terminal and a second terminal, the first multilayer inductor further having a first conductor overlying the portion of the semiconductor substrate, a second conductor overlying at least a portion of the first conductor to form a magnetic coupling between the first conductor and the second conductor, a first dielectric disposed between the first conductor and the second conductor, wherein the first conductor is connected to the first terminal of the first multilayer inductor and the second conductor is connected to the second terminal of the first multilayer inductor; and a first connection extending through the first dielectric for making electrical contact between the first conductor and the second conductor.

According to another aspect of the present invention, there is provided a method of forming an integrated semiconductor inductor, comprising: providing a semiconductor substrate; forming a first inductor element overlying at least a portion of a semiconductor substrate; forming a second inductor element overlying at least a portion of the first inductor element, wherein the first inductor element is magnetically coupled to the second inductor element, and wherein the first inductor element and the second inductor element extend in opposite directions; and electrically connecting one end of the first inductor element to one end of the second inductor element.

According to another aspect of the present invention, there is provided an integrated semiconductor filter comprising: a first multilayer inductor overlying a first portion of a surface of the semiconductor substrate, the first multilayer inductor comprising a first inductor element extending in a first direction overlying the semiconductor substrate and a second inductor element extending in a different direction overlying the first inductor element to form a magnetic coupling between the first and second inductor elements, wherein the first inductor element is electrically connected to the second inductor element; and a first capacitor coupled in series with the first inductor.

Drawings

FIG. 1 illustrates an enlarged plan view of a portion of an embodiment of a filter integrated onto a semiconductor device in accordance with the present invention;

FIG. 2 schematically illustrates a portion of an embodiment of a circuit representing the filter shown in FIG. 1 in accordance with the present invention;

FIG. 3 illustrates an exploded view of a portion of the filter shown in FIG. 1 in accordance with the present invention;

FIG. 4 illustrates an enlarged cross-sectional view of a portion of the filter shown in FIG. 1 in accordance with the present invention; and

fig. 5 illustrates an enlarged cross-sectional view of another portion of the filter shown in fig. 1 in accordance with the present invention.

For simplicity and clarity of illustration, elements in the figures are not necessarily drawn to scale, and the same reference numbers in different figures denote the same elements. In addition, descriptions and details of well-known steps and elements are omitted for brevity of the description. As used herein, current carrying electrode means an element of a device that carries current through the device, such as a source or drain of an MOS transistor, or an emitter or collector of a bipolar transistor, or a cathode or anode of a diode, and a control electrode means an element of a device that controls current through the device, such as a gate of an MOS transistor or a base of a bipolar transistor. Although the devices are explained herein as specific N-channel or P-channel devices, one of ordinary skill in the art will recognize that complementary devices are possible in accordance with the present invention. For clarity of the drawing, the doped regions in the illustrated device structure typically have straight line edges and corner angles that are precise in angle. However, it will be appreciated by those skilled in the art that due to the diffusion and movement of dopants, the edges of doped regions are generally not straight and the angles of the corners are not very precise.

Detailed Description

Fig. 1 schematically illustrates an enlarged plan view of a portion of an embodiment of a semiconductor device 10, the semiconductor device 10 including a fifth order bessel filter 20 integrated onto a semiconductor substrate 37. The filter 20 is indicated by an arrow in a usual manner. As will be seen further below, the elements of the filter 20 facilitate the formation of resonant structures. The filter 20 includes a first stacked or multilayer inductor 11 and a second stacked or multilayer inductor 12 that serve as inductors of the filter 20. As will be appreciated by those skilled in the art, integrated semiconductor inductors such as inductor 11 or inductor 12 or combinations thereof may be used to form other types of filters other than the filter 20 of the quintic bessel filter, including band pass filters, Chebyschev filters and elliptic filters. The filter 20 further includes a first transient voltage suppression device (TVS)75, a first capacitor 70, a second transient voltage suppression device (TVS)76, a second capacitor 71, and a third transient voltage suppression device (TVS) 77.

Fig. 2 schematically illustrates a portion of an embodiment of a circuit 45 representing the filter 20 shown in fig. 1. The description refers to both fig. 1 and fig. 2. Inductor 11 is coupled in parallel with capacitor 70 to form a first resonant circuit on substrate 37. Inductor 12 is coupled in parallel with capacitor 71 to form a second resonant circuit on pad 37. TVS75 is connected between first terminal 26 of inductor 11 and common return terminal 79. The portion of TVS75 indicated by the dotted line functions as a third capacitor of filter 20. TVS76 is connected between terminal 79 and the common connection point of second terminal 27 of inductor 11 and first terminal 29 of inductor 12. The portion of TVS76 indicated by the dashed line functions as a fourth capacitor of filter 20. TVS 77 is connected between second terminal 28 of inductor 12 and terminal 79, the portion indicated by the dashed line functioning as the fifth capacitor of filter 20. Those skilled in the art will appreciate that the TVSs 75, 76, and 77 may also provide electrostatic discharge protection for other components or circuits that may be connected to the filter 20.

Fig. 3 illustrates an enlarged exploded view of a portion of inductors 11 and 12 shown in fig. 1.

Fig. 4 illustrates an enlarged cross-sectional view of a portion of inductor 11 in a conventional manner. The cross-section of inductor 11 is illustrated by cutting out legs 30, 31, 32, 33 and 34 thereof. The description refers to fig. 1, 2, 3 and 4. The inductor 11 is formed to include a first inductor element 14 and a second inductor element 13. The first inductor element 14 is formed overlying a first portion of the surface of the substrate 37 and the second inductor element 13 is formed overlying the element 14. The structure of element 14 is formed to provide electromagnetic coupling between adjacent portions of element 14 such that the inductance of element 14 is greater than the inductance of a straight conductor. Element 13 is formed in the same pattern over element 14 such that the structure of element 13 provides electromagnetic coupling between adjacent portions of element 13 to provide element 13 with an inductance greater than that of a straight conductor. Thus, the elements 13 and 14 are magnetically coupled to each other. In addition, the patterning and overlying proximity of elements 14 and 13 provides electromagnetic coupling between elements 13 and 14 such that elements 13 and 14 form an inductance for inductor 11 that is greater than the sum of the inductance of element 13 alone plus the inductance of element 14 alone. Typically, adjacent portions of elements 14 are spaced approximately 1 to 6(1-6) microns apart and adjacent portions of elements 13 are spaced approximately 2 to 10(2-10) microns apart. Typically, to ensure adequate coupling between elements 13 and 14, elements 13 are spaced approximately 0.5 to 2(0.5-2) microns from elements 14. To provide an electrical connection between elements 13 and 14, one end or terminal of element 13 is electrically connected to one end or terminal of element 14 at node 16. The second end of element 14 functions as terminal 26 of inductor 11 and the second end of element 13 functions as terminal 27 of inductor 11.

The inductor 12 is formed to include a first inductor element 22 and a second inductor element 21. The first inductor element 22 is formed overlying a second portion of the surface of the substrate 37 and the second inductor element 21 is formed overlying the element 22. The patterning of element 22 is formed to provide electromagnetic coupling between adjacent portions of element 22 to provide element 22 with an inductance greater than that of a straight conductor. Element 21 is formed in the same pattern over element 22 such that the structure of element 21 provides electromagnetic coupling between adjacent portions of element 21 to provide element 21 with an inductance greater than that of a straight conductor. In addition, the patterned and blanket proximity of elements 22 and 21 provides electromagnetic coupling between elements 22 and 21 such that elements 22 and 21 form an inductance for inductor 12 that is greater than the sum of the inductance of element 21 alone plus the inductance of element 22 alone. To provide an electrical connection between elements 22 and 21, one end or terminal of element 21 is electrically connected to one end or terminal of element 22 at node 23. The second end of element 22 functions as terminal 28 of inductor 12 and the second end of element 21 functions as terminal 29 of inductor 12.

In a preferred embodiment, the elements 13 and 14 form a square spiral shape. However, each of the elements 13 and 14 may be formed in other shapes that provide mutual flux coupling between adjacent portions of the elements 13, between adjacent portions of the elements 14, and between the elements 13 and 14. For example, elements 13 and 14 may form a circular spiral, or an elongated spiral, or any one of a variety of known shapes that provide flux coupling. In the preferred embodiment, element 14 begins at node 16 and extends in a counterclockwise direction above the surface of substrate 37 until terminating at terminal 26. Element 13 starts at node 16 and extends in a clockwise direction over that portion of element 14 having substantially the same radius as the corresponding portion of element 13 and until terminating at terminal 27. The inductor 12 is formed in the same manner as the inductor 11. Element 22 begins at node 23, extends in a clockwise direction above the surface of substrate 37, and terminates at terminal 28. Element 21 begins at node 23, extends in a counterclockwise direction over a similar portion of element 22, and finally terminates at terminal 29. The exploded view in fig. 2 helps illustrate the overlapping relationship between elements 13 and 14 and between elements 21 and 22.

Referring to fig. 1 and 4, the element 14 typically includes a conductor 41 and a capping dielectric 39. The element 13 typically includes a conductor 42 and a capping dielectric 40. Typically, to minimize the series resistance, the conductors 41 and 42 are formed of a conductor material having a low resistance, such as metal. Typically, the resistivity of the material used for conductors 41 and 42 is no greater than about 4 to 5(4-5) micro-ohm-cm. Typically, the elements 13 and 14 are formed overlying a first portion of the substrate 37. To electrically isolate inductor 11 from substrate 37, dielectric 38 is typically formed on the surface of substrate 37. Conductors 41 are formed on the surface of dielectric 38 in the desired pattern for elements 14. For example, dielectric 38 may be masked and patterned to expose portions of dielectric 38 where conductors 41 are to be formed. Thereafter, a dielectric 39 is formed covering the conductor 41. Dielectric 39 may not be formed over the portion of conductor 41 that forms node 16. Conductor 42 is formed on the surface of dielectric 39 that covers the top surface of conductor 41. Conductor 42 is also formed on the surface of conductor 41 where node 16 is formed. Typically, a dielectric 40 is provided to cover conductor 42 to electrically isolate conductor 42 from other elements of device 10.

The inductor 12 is formed in the same manner as the inductor 11. Element 22 includes a conductor similar to conductor 41 and a covering dielectric similar to dielectric 39. Element 21 includes a conductor similar to conductor 42 and a covering dielectric similar to dielectric 40. Node 23 is formed in a similar manner as node 16.

It should be noted that for the purpose of illustrating the elements 13, 14, 21 and 22 in fig. 1 and 2, the edges of the dielectric layer 40 that may obscure the underlying elements 14 and 22 are not shown in fig. 1 and 2 for clarity of description.

Referring to fig. 1 and 5, TVS75, TVS76, and TVS 77 are formed on the surface of substrate 37. Typically, each of TVS75, TVS76 and TVS 77 is formed by forming first doped region 46 on the surface of substrate 37. To form a contact region for each TVS75, 76 and 77, a second doped region 47 is formed inside the doped region 46. Dielectric 38 may be formed before regions 46 and 47 or may be formed after regions 46 and 47 are formed. A conductor 49 is provided to make electrical contact to region 47. Conductors 49 of TVS75 and 77 typically extend across dielectric 38 to make electrical contact with respective terminals 26 and 28 in respective inductors 11 and 12. Conductor 42 of inductor 11 and a corresponding conductor of inductor 12 may extend into electrical contact with conductor 49 of TVS76, thereby connecting terminals 27 and 29 to TVS 76. Those skilled in the art will recognize that substrate 37 functions as terminal 79 in fig. 2.

Capacitors 70 and 71 may be planar capacitors overlying the surface of substrate 37 or may be Metal Oxide Semiconductor (MOS) capacitors formed on the surface of substrate 37 or may be formed as trench capacitors or other well-known capacitor structures. Fig. 5 illustrates a planar capacitor as the capacitor 70 and a MOS capacitor as the capacitor 71 in a usual manner. Capacitor 71 includes doped region 55 formed on the surface of substrate 37. Doped region 56 and doped region 57 are formed inside region 55 to serve as the source and drain of the MOS transistor forming capacitor 71. Dielectric 38 may form a gate insulator for a MOS transistor or a different insulator may be formed as a gate insulator. To form the gate conductor of capacitor 71, gate material 60 is typically formed over region 55 and disposed between regions 56 and 57. Dielectric 58 is typically formed around material 60 to insulate material 60 from other elements. Conductors 63 may be formed to make electrical contact to regions 56 and 57. Conductor 63 may also extend across dielectric 38 to make electrical contact with conductor 49 of TVS 76. Conductor 64 is typically formed to make electrical contact between material 60 and conductor 49 of TVS 77. Conductor 63 forms one terminal of capacitor 71 and conductor 64 forms a second terminal of capacitor 64, as is well known in the art. Dielectric 38 may be provided with a conductor 51 to form an electrical connection with conductor 49 of TVS75 and serve as one plate of capacitor 70. A portion of conductor 51 may be provided with dielectric 52 to form the dielectric of capacitor 70 and another conductor 53 may be provided to be placed beneath at least a portion of dielectric 52 to form the second plate of capacitor 70 and extend laterally across dielectric 38 to make electrical contact with conductor 49 of TVS 76. Conductors 51, 53, 63, and 64 are illustrated in circuit 45 of fig. 2.

Referring to fig. 2, a signal is received at an input 65 of filter 20 and a filtered output signal is formed at an output 66. It is believed that the insertion loss of the filter 20 is reduced by about 10 decibels (10db) and the group delay distortion is reduced by about 50 percent (50%). It is also believed that the use of integrated inductors such as inductors 11 or 12 in other filter structures will also improve insertion loss and group delay distortion.

In view of all of the above, it is evident that a new device and method is disclosed. Included, among other features, is forming a multilayer inductor on a semiconductor substrate. The multilayer inductor facilitates forming a capacitor in parallel with the inductor and forming a resonant circuit on the semiconductor substrate. The multilayer inductor provides greater inductance in a given area of the semiconductor die, thereby reducing cost. In addition, other circuit elements may be formed on the substrate 37 along with the multilayer inductor.

Although the present invention has been described with reference to specific preferred embodiments, it is evident that many alternatives and variations will be apparent to those skilled in the semiconductor arts. For example, the inductors 11 or 12 may be used as independent inductors instead of in the filter circuit, and the number of stages of the filter 20 and the structure of each stage may be changed to form other types of filters. Also, the word "connected" is used throughout for clarity of description, but is intended to have the same meaning as the word "coupled". Thus, "connected" should be interpreted to include direct connections or indirect connections.

Claims (5)

1. An integrated semiconductor inductor, comprising:

a semiconductor substrate;

a first multilayer inductor overlying at least a portion of the semiconductor substrate, the first multilayer inductor having a first terminal and a second terminal, the first multilayer inductor further having a first conductor overlying the portion of the semiconductor substrate, a second conductor overlying at least a portion of the first conductor to form a magnetic coupling between the first conductor and the second conductor, a first dielectric disposed between the first conductor and the second conductor, wherein the first conductor is connected to the first terminal of the first multilayer inductor and the second conductor is connected to the second terminal of the first multilayer inductor;

a first connection extending through the first dielectric for making electrical contact between the first conductor and the second conductor;

a first capacitor coupled in parallel with the first multilayer inductor, the first capacitor having a first terminal and a second terminal, the first terminal of the first capacitor being coupled to the first terminal of the first multilayer inductor, the second terminal of the first capacitor being coupled to the second terminal of the first multilayer inductor; and

a second capacitor having a first terminal coupled to the second terminal of the first multilayer inductor, wherein the second capacitor is a transient voltage suppressor.

2. The integrated semiconductor inductor of claim 1 wherein the first multilayer inductor has a resistivity of no more than 5 micro-ohm-cm.

3. The integrated semiconductor inductor of claim 1 wherein the first conductor and the second conductor are metal conductors.

4. A method of forming an integrated semiconductor inductor, comprising:

providing a semiconductor substrate;

forming a first inductor element overlying at least a portion of a semiconductor substrate;

forming a second inductor element overlying at least a portion of the first inductor element, wherein the first inductor element is magnetically coupled to the second inductor element, and wherein the first and second inductor elements extend in opposite directions, the second inductor element being coupled to the common connection terminal;

electrically connecting one end of the first inductor element to one end of the second inductor element;

forming a third inductor element overlying at least another portion of the semiconductor substrate;

forming a fourth inductor element overlying at least a portion of the third inductor element, wherein the third inductor element is magnetically coupled to the fourth inductor element, and wherein the third and fourth inductor elements extend in opposite directions, the fourth inductor element being coupled to the common connection terminal; and

a common electrical coupling is formed between one end of the second inductor element and one end of the fourth inductor element.

5. The method of claim 4, further comprising coupling a capacitor in parallel with the first inductor element and the second inductor element.