HK1151890B - Method of forming an mos transistor and structure therefor - Google Patents

Description

Method for forming MOS transistor and structure thereof

The divisional application is based on the Chinese patent application with the application number of 2007100842229.8, the application date of 2007, 2 and 27, and the title of the invention is "method for forming MOS transistor and structure thereof".

Technical Field

The present invention relates generally to electronic devices and, more particularly, to methods and structures for forming semiconductor devices.

Background

In the past, portable electronic systems have often been powered by multiple power sources, such as one or two batteries, and a wall AC outlet with the aid of an AC/DC converter or battery charger. Switching networks are commonly used to control power flow according to the mode of operation. For example, if the portable device is powered by a main battery while the secondary battery is charging, then some switches are closed and others are opened. In another mode, the switches may be reversed. To be effective in all modes, the switch must be turned on and off in both directions. However, power metal oxide semiconductor field effect transistors (power MOSFETs) can only switch off the voltage in one direction. In the opposite direction, the body diode of the MOSFET conducts current, so that two power MOSFETs are usually connected in series to act as a switch. These two power MOSFETs are typically used with the drains tied together so that when the gate voltage is 0, one of the devices will always disconnect the voltage applied across the two transistors, regardless of their polarity. An example of such a switch is NTLTD7900 provided by Ansenet semiconductor of Phoenix, Arizona (ONSemiconductor of Phoenix Arizona). Because such switches use two transistors, the switches use twice as much silicon as one transistor, which increases cost. In addition, since the two transistors are connected in series, the on-resistance is high.

Accordingly, it is desirable to have a method of forming a bidirectional switch that has a high breakdown voltage in both directions, which reduces the on-resistance of the bidirectional switch and reduces cost.

Drawings

FIG. 1 schematically illustrates a circuit representation of a portion of a particular embodiment of a MOS transistor diode according to the present invention;

FIG. 2 illustrates a cross-sectional portion of a particular embodiment of the MOS transistor of FIG. 1 in accordance with the present invention;

fig. 3 is a graph illustrating a specific embodiment of some of the region doping profiles of the MOS transistor of fig. 1 in accordance with the present invention;

FIG. 4 illustrates an enlarged cross-sectional portion of the MOS transistor of FIG. 1 illustrating an early stage portion of a particular embodiment of a method of forming a MOS transistor according to the invention;

fig. 5-12 illustrate enlarged cross-sectional portions of the MOS transistor of fig. 1 illustrating subsequent stage portions of a particular embodiment of a method of forming the MOS transistor of fig. 1 in accordance with the invention;

FIGS. 13 and 14 illustrate enlarged cross-sectional portions of the MOS transistor of FIG. 1, illustrating portions of stages of an alternative embodiment of a method of forming portions of the MOS transistor of FIG. 1 in accordance with the invention;

fig. 15 and 16 illustrate enlarged cross-sectional portions of the MOS transistor of fig. 1 illustrating portions of stages of a further alternative embodiment of a method of forming portions of the MOS transistor of fig. 1 in accordance with the invention;

fig. 17 illustrates a cross-sectional portion of another MOS transistor at a stage in a method of forming a MOS transistor in accordance with the invention.

For simplicity and clarity of illustration, elements in the figures are not necessarily to scale, and the same reference numbers in different figures denote the same elements. In addition, descriptions and details of well-known steps and elements may be omitted for simplicity of the description. As used herein current carrying electrode means an element in a device that carries current through the device such as the source and drain of a MOS transistor, or the emitter and collector of a bipolar transistor, or the anode and cathode of a diode, and a control electrode means an element in the device that controls current through the device, for example, the gate of a MOS transistor, or the base of a bipolar transistor. Although the devices are explained herein as certain N-channel or P-channel devices, one of ordinary skill in the art will recognize that complementary devices are also possible in accordance with the present invention. For clarity of the drawing, the doped regions of the device structure are depicted as corners having generally straight line boundaries and precise angles. However, those skilled in the art recognize that due to the diffusion and activation of dopants, the boundaries of doped regions are generally not straight lines, nor are the corners precisely angled.

Detailed Description

Fig. 1 schematically illustrates a circuit representation of a bidirectional transistor 20 that is capable of conducting current through the transistor 20 in both directions and of disconnecting the inverted voltage across the transistor 20 in both directions. Transistor 20 includes a first MOS transistor 21, a first switch or first switching transistor 27, and a second switch or second switching transistor 29. The parasitic source-drain diode of transistor 27 is represented by diode 28 and the parasitic source-drain diode of transistor 29 is represented by diode 30. The transistor 20 also includes: a control terminal 35 configured to provide a connection to a control or gate of transistor 20; a first current terminal 33 configured to provide a connection to a first current-carrying electrode (CCE1) of transistor 20; and a second current terminal 34 configured to provide a connection to a second current-carrying electrode (CCE2) of transistor 20. As will be seen further below, the first and second current carrying electrodes may serve as the source and drain of transistor 20. Although transistors 20, 21, 27, and 29 are illustrated and described herein as N-channel transistors, transistor 20 and transistors 21, 27, and 29 may also be used as P-channel transistors. As will be seen further below, transistor 21 includes a body region or body 22 that is isolated from the two current carrying electrodes of transistor 21. To facilitate bi-directional current conduction in transistor 20, body 22 is not directly connected to either current-carrying electrode of transistor 21, but is selectively connectable to either current-carrying electrode via transistors 27 and 29 in response to signals applied to the first and second current-carrying electrodes of transistor 20. The source of a transistor is typically an electrode connected to the body of the transistor. Since body 22 is not directly connected to the source or drain of transistor 21, it is not clearly shown in the circuit schematic representation of transistor 20 which current carrier electrode of transistor 20 is the source of transistor 20 or which current carrier electrode is the drain of transistor 20.

In operation, if the voltage of the signal applied to the second current carrying electrode through terminal 34 is greater than the voltage of the signal applied to the first current carrying electrode through terminal 33, then the second current carrying electrode serves as the drain and the first current carrying electrode serves as the source for transistors 20 and 21. Transistor 21 is in an off state if the voltage applied to terminal 35 is less than the threshold voltage of transistor 21 relative to the voltage applied to terminal 33. The gate of transistor 29 is at a low voltage so that transistor 29 is also off. The gate of transistor 27 is the voltage applied to terminal 34. Assuming that the voltage applied to terminal 34 is greater than the threshold of transistor 27, transistor 27 turns on and connects body 22 to the first current carrying electrode, thus ensuring that body 22 is connected to the lowest voltage applied to transistor 20. This facilitates transistor 20 withstanding the voltage applied between terminals 33 and 34. If the voltage applied to terminal 35 is changed to be greater than the threshold voltage of transistor 21. Transistor 21 is turned on so that the voltage on terminal 34 is substantially the same as the voltage on applied terminal 33 (minus the drain-source turn-on voltage Vds-on of transistor 21). Therefore, the voltage applied to the gates of the transistors 27 and 29 is also a low voltage, and both the transistors 27 and 29 are turned off. Body 22 is floating, but body 22 never exceeds about 0.6V, due to diode 28, which is greater than the voltage on terminal 33. Since transistor 21 is conductive, current can flow from terminal 34 through transistor 21 to terminal 33. Because transistor 20 is on, transistor 21 does not have to disconnect the voltage applied between the first and second current carrying electrodes, and thus the connection of body 22 is not important.

If these signals applied to terminals 33 and 34 are reversed, such that the highest voltage is applied to CCE1 through terminal 33 and a lower voltage is applied to CCE2 through terminal 34, then the second current-carrying electrode serves as the source and the first current-carrying electrode serves as the drain for transistors 20 and 21. If the voltage applied to terminal 35 is again less than the threshold voltage of transistor 21 relative to the voltage applied to terminal 34, then transistor 21 is turned off. The gate of transistor 27 receives the low voltage at 34 so that transistor 27 is turned off. The gate of transistor 29 receives the high voltage at 33 which causes transistor 29 to connect body 22 to the second current carrying electrode and thus to the lowest voltage applied to transistor 20. This connection facilitates transistor 20 withstanding the voltage applied between CCE1 and CCE2 through terminals 33 and 34. If the voltage applied to terminal 35 is changed to be greater than the threshold voltage of transistor 21, transistor 21 is turned on so that current flows from terminal 33 through transistor 21 to terminal 34. Because transistor 21 is on, the voltage on terminal 33 is substantially the same as the voltage applied to terminal 34 (minus the drain-source turn-on voltage Vds-on of transistor 21). Therefore, the voltage applied to the gates of the transistors 27 and 29 is also a low voltage, and both the transistors 27 and 29 are turned off. Body 22 is floating, but because of diode 30, body 22 never exceeds about 0.6V, which is greater than the voltage on terminal 34. Because transistor 21 is on, transistor 21 does not have to break the voltage, and thus the connection of body 22 is not important.

To help provide this functionality to transistor 20, the drain of transistor 27 is commonly connected to the gate of transistor 29 and the first current-carrying electrodes of transistors 20 and 21. A drain of transistor 27 is commonly connected to body 22 and a source of transistor 29. A drain of transistor 29 is commonly connected to a gate of transistor 27 and to the second current-carrying electrodes of transistors 20 and 21.

Fig. 2 illustrates an enlarged cross-sectional portion of the particular embodiment of transistor 20 depicted in fig. 1.

Fig. 3 is a graph illustrating one embodiment of a doping profile of regions of transistor 20 relative to the doping depth of transistor 20. The abscissa represents depth and illustrates some regions of the transistor 20 that are involved as the depth increases. The ordinate represents the doping concentration. These descriptions refer to fig. 1, 2 and 3. In one particular embodiment, transistor 21 is an N-channel vertical MOSFET having a gate of channel type, and transistors 27 and 29 are lateral N-channel transistors. In this particular embodiment, transistor 21 has multiple channel gates 45-49 that extend generally parallel to each other across semiconductor substrate 40. For the cross-section depicted in fig. 2, those skilled in the art will recognize that the multi-channel gate generally extends in a direction perpendicular to the plane of the paper, however, any variation in the geometry of the channel gate is possible for the channel gate. In some embodiments, electrical contact is made to a gate located at the far end of the portion of transistor 21 depicted in fig. 2. Substrate 40 typically includes a bulk N-type substrate 37 and an N-type epitaxial layer 39, with the N-type epitaxial layer 39 being formed on the surface of bulk substrate 37. Transistors 21, 27, and 29 are formed on a first surface 41 of substrate 40. A conductor 36 is formed on the second surface of the substrate 37 providing a connection between the CCE2 and the terminal 34.

Transistors 21, 27, and 29 are formed on substrate 40. Transistor 21 includes a first doped region 42 formed on a first surface 41 of substrate 40 and extending a first distance into substrate 40. Region 42 serves as body 22 of transistor 21 and has a conductivity type opposite that of layer 39. The highest doping concentration of region 42 is typically no less than the highest doping concentration of layer 39 in order to provide a channel region and block forward voltage applied to transistor 20. Region 42 is at a maximum concentration of about 1E16 to 1E18atoms/cm³Doping the transistor 20 with boron (atomic number per cubic centimeter) facilitates the transistor 20 to withstand a forward breakdown voltage of at least about 10 to 50 volts (10-50V). Region 42 and layer 39 help block forward voltage applied to transistor 20, for example, when the voltage applied to terminal 34 is greater than the voltage applied to terminal 33. Region 42 is often referred to as the pHV region. Doped regions 91 and 92 are formed within region 42 to facilitate electrical contact with region 42. Regions 91 and 92 are typically of the same conductivity type as region 42 and have a higher doping concentration. Although only one region 91 and one region 92 are shown, one skilled in the art will recognize that more regions 91 and 92 may be used, including forming such regions interspersed between gates 45-49. The P-N junction formed at the interface between region 42 and layer 39 forms a diode, which is depicted as diode 24 in fig. 1. Other high voltage regions, also referred to as nHV regions, are formed to help block reverse voltage such as when the voltage applied to terminal 33 is greater than the voltage applied to terminal 34. Such high voltage region is formed as doped region 43 extending from surface 41 a second distance into region 42 and overlying at least oneOn the part area 42. The second distance of the region 43 must be sufficiently deep to withstand high reverse voltages. As shown in fig. 3, region 43 typically has a doping concentration less than that of region 42 so as to provide a high reverse breakdown voltage between regions 42 and 43, and may also provide a threshold voltage of about 0.5 volts to 2.0 volts for the MOS transistor formed by regions 42 and 43 and layer 39 of transistor 21. The maximum concentration of the region 43 may be in the range of 1E16 to 1E18atoms/cm³In turn, transistor 20 is advantageously resistant to reverse breakdown voltages of at least about 10 to 50 volts (10-50V). The P-N junction formed at the interface between regions 43 and 42 forms another diode, depicted in fig. 1 as diode 23. A channel is formed extending from surface 41 into layer 39 via regions 42 and 43 to form channel-type gates 45, 46, 47, 48 and 49 of transistor 21. Gates 45-49 are generally identified by arrows. Forming a channel via the region 43 divides the region 43 into a plurality of regions 43. The gate structure of gates 45-49 includes a first insulator, such as a first silicon dioxide 72 (sometimes referred to as oxide 72), and a second insulator, such as a second silicon dioxide 83, formed along the sidewalls of each channel. Silicon dioxide 72 or silicon dioxide 83, referred to herein as oxide 72 and oxide 83, respectively. The first insulator serves as the gate dielectric for gates 45-49. The gate dielectric is generally along the sidewalls of the channel and is positioned alongside region 42. The thicker second insulator helps to withstand high electric fields and thus increases the reverse breakdown voltage of transistor 20. An optional third insulator, such as a thick bottom silicon dioxide 79, is formed along the bottom of each trench. To help reduce the gate-to-CCE 2 capacitance of transistor 21 and to withstand higher voltages across silicon dioxide 79, the third insulator along the bottom of each channel is typically thicker than the first insulator to help reduce the gate-to-CCE 2 capacitance and also to maintain a larger voltage across silicon dioxide 79. A gate conductor 80 is formed in each channel to facilitate the formation of gates 45-49. In a preferred embodiment, conductor 80 is doped polysilicon, but may be other conductor materials in other embodiments. The conductor 80 is typically covered with an additional insulator 95. Doped regions 44 are formed in the linerOn the surface of bottom 40 and between trench gates 45-49. Region 43 generally serves as the first current-carrying electrode (CCE1) of transistor 21, and region 44 serves to help obtain a low-resistance electrical contact to region 43. Region 44 is of opposite conductivity type to region 42 and has a higher doping concentration than regions 42 and 43 (see fig. 3). The higher doping concentration helps to obtain ohmic contact with the region 43. Region 44 may be doped with arsenic to a maximum doping concentration of about 1E18 to 1E21atoms/cm³In the meantime. Region 44 is formed on surface 41 and extends into substrate 40 a third distance that is less than the second distance of region 43 so as to overlap a portion of region 43. Region 43 is typically formed before region 44, and a portion of region 43 may be over-doped to form region 44. Region 44 is generally separated from the vertical portions of the sidewalls of the respective channels forming gates 45-49 by a first distance 50. Distance 50 helps to reduce the gate-to-CCE 1 capacitance and helps to reduce the electric field across oxide 83, thus increasing the drain-to-source reverse breakdown voltage of transistor 21. This also helps to leave a wider lateral depletion region.

Transistors without region 43 can only withstand very small reverse voltages, typically less than about 8 volts (8V). However, due to the region 43, the transistor 20 can withstand a large reverse voltage. Thus, it can be seen that transistor 20 includes: a first blocking junction (e.g., at the interface of regions 42 and 43) that blocks a voltage applied in a first direction across transistor 20; and a second blocking junction (e.g., at the interface of layer 39 and region 42) that blocks a voltage applied in a second direction across transistor 20.

In one embodiment, the region 42 has about 9E16atoms/cm³And the junction between region 42 and layer 39 is about 2.8 microns from surface 41. The region 43 has an area of about 5E16atoms/cm³And the junction between regions 42 and 43 is about 1.5 microns from surface 41. These parameters help provide transistor 20 with a reverse breakdown voltage generally between regions 43 and 42 that is greater than 20 volts (20V), and generally about 30 volts (30V), to provide transistor 20 with a reverse breakdown voltage of generally between regions 43 and 42And a forward breakdown voltage generally between region 42 and layer 39 of greater than 25 volts, and typically about 30 volts (30V). Region 44 is spaced about 0.3 microns from the vertical sidewalls of gates 45-49, which leaves a wider depletion region and also reduces the electric field in the second insulator by about 60%, thus helping to increase the reverse breakdown voltage of transistor 20.

Transistor 29 may be formed on surface 41 adjacent one side of transistor 21. In a preferred embodiment, transistor 29 includes a doped region 101 that extends across a first surface of substrate 40. Region 101 may be positioned parallel to region 42 or may be positioned differently in other embodiments. Region 101 serves as the body of transistor 29 and is typically of the opposite conductivity type as layer 39. Doped region 102 is formed in region 101 and has the opposite conductivity type to serve as the drain of transistor 29. Doped region 103 is formed within region 102 to have the same conductivity type at a doping concentration greater than region 102 to facilitate forming an electrical contact with region 102. A doped region 105 having a conductivity type and doping concentration similar to that of region 103 is formed in region 101, spaced from 102, to serve as the source of transistor 29. A doped region 104, having the same conductivity type as region 101, is formed next to region 104 to facilitate forming an electrical contact with region 101. The gate 106 of the transistor 29 includes: a gate insulator formed on the surface of substrate 40 and overlying at least a portion of regions 103 and 105, a gate conductor formed overlying the gate insulator, and a dielectric layer overlying the gate conductor to isolate the gate conductor from other conductors.

Doped region 93 is formed on surface 41 adjacent to region 101 and extends into layer 39 to form an electrical contact with layer 39. The regions 93 extend parallel 101 but may be positioned differently in other embodiments. Region 93 is generally of the same conductivity type as layer 39 and has a higher doping concentration. Region 93 facilitates the formation of electrical contact between the drain of transistor 39 and CCE2 of transistor 21.

Transistor 27 may be formed on surface 41 near the other side of transistor 21. Transistor 27 generally includes a doped region 110 similar to doped region 101. The doped regions 110 may extend parallel to one side of the transistor 20, or may be differently positioned. Similar to region 102, doped region 111 is formed extending from surface 41 into region 110 and forms the drain of transistor 27. Similar to region 103, doped region 112 is formed within region 111 to facilitate forming an electrical contact to region 111. Doped region 114, which is similar to doped region 105, is formed in region 110 and is spaced apart from region 111 to serve as the source of transistor 27. Doped region 113, which is similar to region 114, is formed next to region 113 and facilitates the formation of a low resistance electrical contact to region 110. The doping types and concentrations of regions 113, 114, 111, and 112 are similar to 104, 105, 102, and 103, respectively.

Fig. 4 illustrates an enlarged cross-sectional portion of transistor 20 illustrating an early stage of a particular embodiment of a method of forming transistor 21 in transistor 20. This description is made with reference to fig. 2, 3 and 4. One region of substrate 40 is used to form transistor 21. Other areas of substrate 40 are used to form transistors 27 and 29, however, such areas are not illustrated in this description for clarity of description. Other areas of substrate 40 are used for other types of devices. Substrate 40 generally comprises a bulk semiconductor substrate 37 having an epitaxial layer 39 formed on one surface of substrate 37. However, in some embodiments, epitaxial layer 39 is not required, and transistor 20 is formed on bulk semiconductor substrate 37, such as in a doped region of substrate 37. In this case, the upper surface of substrate 37 will become surface 41. In most embodiments, buried layer 38 is formed within a portion of substrate 40 and beneath a portion of transistor 21. Buried layer 38 is formed by a variety of well-known methods including doping substrate 40 with a high energy implant or by doping a portion of substrate 37 prior to forming layer 39. Buried layer 38 under the gate of transistor 21 allows a lower amount of doping to be used within layer 39, which facilitates the formation of regions 101 and 110 within layer 39.

A first insulating layer 59, such as a pad oxide typically formed of silicon dioxide, is formed on surface 41 of substrate 40 to a thickness of approximately 400 and 1000 angstroms. Layer 59 may be openFormed by a variety of well-known methods, including thermal oxidation. A mask (not shown) is used to assist in doping a portion of surface 41 to form doped region 43 within substrate 40. Region 43 is typically formed by high energy implantation to achieve the desired doping concentration at the depths described hereinabove. For example, the phosphorus may be present at about 1E12 to 1E13atoms/cm²The dose of (c) is about 200 to 800(200-800) Kev (kilo electron volts) energy implantation. A drive is driven at about 1000 to 1100(1000-1100) degrees celsius for about 60(60) minutes for activating the dopants. Thus, the region 42 may be formed with the region 43, with the region 43 overlying a portion of the region 42. In a preferred embodiment, region 42 is formed by first implanting dopants in layer 39 with the highest doping concentration at a depth deeper than that of region 43. The implanted dopants are represented in fig. 4 by the plus symbol (+) 32. The dopants, represented by the additive symbols 32, may be formed by high energy implantation to achieve the desired doping concentration at the depths described hereinabove. For example, boron may be present at about 8E12 to 1E14atoms/cm²A dose of about 500Kev to 2 Mev. A drive is driven at about 900 to 1000 (900-. Thus, portions 31 in region 39 are doped adjacent to region 43 and overlying the dopant represented by plus sign 32 to ensure that region 42 extends from surface 41 to the desired depth of peak doping concentration. The region 31 is indicated in a general manner by a long dash line. The peak doping concentration of region 31 is typically 1E18 to 1E20atoms/cm³Preferably about 1E19atoms/cm³. Region 31 is typically implanted at a lower energy to form a peak doping closer to surface 41 than the dopant of plus sign 32. For example, the portions 31 are typically at about 1E14 to 5E15atoms/cm²The implant is performed at an energy of about 60 Kev. Other methods may also be used to form region 42, such as multiple epitaxial layers and related doping of the epitaxial layers to obtain region 42. However, the high energy implantation method provides good control of the depth and doping concentration of region 42 and is therefore preferred. Thus, region 43 is disposed within region 42 and covers a portion of region 42.

Fig. 5 illustrates an enlarged cross-sectional view of a portion of transistor 20at another subsequent stage in a particular embodiment of a method of forming transistor 20. A first protective layer 62 is formed over layer 59. As will be seen further hereinafter, protective layer 62 is used to assist in forming the first and second insulators of gates 45-49. Layer 62 also helps to ensure that the openings of channels 64-68 near surface 41 are equal to or wider than the width of channels 64-68 distal to the openings. This configuration facilitates subsequent formation of conductor material within trenches 64-68. The material used for layer 62 is one that limits the diffusion of oxides and thus limits the oxidation of any layers underlying layer 62. Although layer 62 is shown as a single layer of material, it could be a layer structure of different material types. Layers 59 and 62 are preferably silicon dioxide and a silicon oxide stack on silicon nitride, respectively.

A mask (not shown) may be used for layer 62 and patterned to form openings where trenches 64, 65, 66, 67, and 68 are formed. The openings in the mask are used to form openings through layer 62, through layer 59, and into substrate 40 to a depth 63, thus forming openings into substrate 40 to obtain trenches 64, 65, 66, 67, and 68. Channels 64-68 generally have sidewalls 51 that are approximately aligned with the boundaries of the openings through layers 59 and 62. Channels 64-68 also have a bottom 69. As is well known in the art, the chemical reaction used to etch layer 62 and subsequent layer 59 is different than the chemical reaction used to etch substrate 40. In a preferred embodiment, an anisotropic fluorine-based RIE type etch is used to etch layers 59 and 62. The openings in substrate 40 to obtain channels 64-68 may be formed by a variety of well-known techniques such as Reactive Ion Etching (RIE), which typically uses chlorine or bromine chemistry, or fluorine-based processes such as Bosch processes. In a preferred embodiment, depth 63 is greater than the depth of region 42.

One of the masks (not shown) used to form trenches 64-68 may also be used to assist in forming the openings through layer 62. Opening 60 is later used to form field oxide 61 (fig. 2). Although field oxide 61 generally surrounds transistor 21, only a portion of oxide 61 is shown to simplify the drawing. An optional doped region 73 is formed in substrate 40 below bottom 69 of channels 64-68 to help provide transistor 20 with a low on-resistance. Region 73 is typically doped with the same dopant type as layer 39. The mask is removed later.

The sidewalls 51 and bottom 69 are then oxidized to form an oxide 57, as indicated by the dashed lines, that extends from the sidewalls 51 and bottom 69 into the material of the substrate 40.

Fig. 6 illustrates another enlarged cross-sectional view of a portion of transistor 20at another subsequent stage in a particular embodiment of a method of forming semiconductor transistor 20. Oxide 57 is removed thereby causing sidewalls 51 to recede or recess under layer 62 and extend bottom 69 into substrate 40. The amount of set back or recess is generally determined by the thickness of the oxide 57 and the amount of oxide 57 removed. In a preferred embodiment, oxide 57 is formed to a thickness of about 100 nanometers on each of sidewalls 51 and bottom 69. Preferably, all of the oxide 57 is removed, resulting in a sidewall 51 that is formed that is set back approximately half the thickness of the oxide 57. During the removal of oxide 57 from sidewalls 51 and bottom 69, a portion of layer 59 is also removed from beneath layer 62 and adjacent to the opening through layer 62. In general, the process of removing oxide 57 is preferably oxidation followed by a portion of layer 59 immediately adjacent oxide 57 (fig. 5) and extending along layer 59 and flushly under layer 62 for a distance 58. The distance 58 is typically greater than the thickness of the oxide 57 and may be approximately 100 to 1000 nanometers, preferably 150 nanometers.

Removing a portion of layer 59 also removes a portion of sidewall 51 near surface 41, forming a portion of sidewall 51 within shoulder 71 adjacent or near the interface of sidewall 51 and surface 41, and particularly at the interface of sidewall 51 and surface 41. Flap 71 forms a non-orthogonal intersection with surface 41. A portion of layer 59 under layer 62 is removed leaving a portion of layer 62 overhanging the openings of channels 64-84 as overhang 70. Projections 70 extend through side walls 51 and expose the lower or bottom surface of layer 62. The cutout of the lower portion of layer 62 also forms the openings of channels 64, 65, 66, 67, and 68 at surface 41 to be wider than the width of channels 64, 65, 66, 67, and 68 at the ends of the openings along side walls 51. The wide opening facilitates the formation of the remaining elements of channels 64-68, including the subsequent formation of conductor 80 within trenches 64-68. Removing a portion of the sidewall 51 also facilitates the formation of a protective liner (spacer) at a later stage.

In other embodiments, the width of channels 64-68 may be increased to extend below layer 59 and wings 71 formed by other processes, such as removing a portion of sidewalls 51 by an isotropic silicon etch (wet or dry).

Fig. 7 illustrates an enlarged cross-sectional view of a portion of transistor 20at another subsequent stage in a particular embodiment of a method of forming transistor 20. A first silicon dioxide 72 is formed along sidewall 51, including shoulder 71, and bottom 69. Oxide 72 generally extends from the bottom surface of raised portion 70 along shoulder 71, sidewall 51, and across bottom 69. To form oxide 72 along wings 71 and at the top edges of channels 64-68, wings 71 help provide low stress regions. In a preferred embodiment, a portion of oxide 72 formed along sidewalls 51 juxtaposed to region 43 will serve as the gate oxide for transistor 21. Thus, the oxide 72 is thin, typically between about 20 and 100 nanometers thick, and preferably about 60 nanometers thick. The oxide 72 is formed by a variety of well-known processes including dry oxygen oxidation and wet oxidation.

Fig. 8 illustrates an enlarged cross-sectional view of a portion of transistor 20at a next subsequent stage in a particular embodiment of a method of forming transistor 20. To facilitate the subsequent formation of a thick insulator, such as thick silicon dioxide 79 (fig. 2), along bottom 69 without substantially increasing stress or altering the thickness of oxide 72 along sidewalls 51, polysilicon layer 76 is formed over oxide 72, including forming polysilicon layer 76 overlying wings 71, sidewalls 51 and bottom 69. In a preferred embodiment, a conformal layer of polysilicon is formed over layer 62, including over the edges of the openings through layer 62, over the bottom surfaces of raised portions 70, or over oxide 72. The polycrystalline layer 76 is typically formed to a thickness of about 20 to 100 nanometers, and is preferably deposited to a thickness of about 50 nanometers.

Thereafter, the non-vertical portions of layer 76 overlying protective layer 62, the edge portions of protruding portions 70, and the portion on bottom 69 are removed to reveal at least a portion of oxide 72 along bottom 69. Preferably, an amount of layer 76 is removed to ensure that a portion of layer 76 on sidewalls 51 and shoulders 71 is no further from oxide 72 than the edge of raised portion 70. As shown in fig. 8, layer 76 remains on the portion of oxide 72 under raised portion 70, thus covering all of oxide 72 except at the bottom 69 portion. The dashed lines indicate the portions of layer 76 removed from bottom 69. Typically, that portion of layer 76 is removed by anisotropic reactive ion etching, which leaves layer 76 on that portion of oxide 72 on sidewalls 51 including wings 71.

A second protective layer 78 is formed over layer 76 and the exposed portion of oxide 72 along bottom 69. Layer 78 is typically formed of the same material as layer 62. The straight line represents the transition between layer 62 and layer 78. Layer 76 is recessed under the sidewalls of raised portion 70 to form a substantially planar surface of layer 62, which surface of layer 62 is free of layer 76 for forming layer 78. If there is no step recessed into layer 76 under raised portion 70, layer 78 cannot be formed on the sidewalls of layer 62, so that the exposed portion of layer 78 and the top of oxide 72 are readily exposed for subsequent processing operations. A non-vertical portion of layer 78 is removed to reveal at least a portion of oxide 72 along bottom 69. The portion of layer 78 is typically removed by an etching operation known as anisotropic liner (spacer). For example, the portion of layer 78 may be removed by a timed RIE etch that ensures that all non-vertical portions of layer 78 overlying bottom 69 are removed. In a preferred embodiment, the etching that removes the portion of layer 78 is timed to remove about 50% more material than expected along bottom 69. For example, if layer 78 forms to a thickness of about 50 nanometers, the removal etch is timed to remove about 75 nanometers.

Fig. 9 illustrates an enlarged cross-sectional view of a portion of transistor 20at another subsequent stage in a particular embodiment of a method of forming transistor 20. The thickness of oxide 72 along a portion of bottom 69 is increased to form a thick silicon dioxide 79 at the bottom of trenches 64-68. The thickness of thick silicon dioxide 79 is formed without substantially increasing or changing the first thickness of oxide 72 along sidewalls 51, particularly the thickness juxtaposed with region 43. Silicon dioxide 79 is typically formed by further oxidizing the material exposed within channels 64-68. The remaining portions of layers 78 and 76 protect oxide 72 on sidewalls 51. In a preferred embodiment, the silica 79 is formed using a wet oxidation process with a hydrogen source. In a preferred embodiment, the thickness is typically increased by about 200 nanometers to a total thickness of about 230 nanometers, but in other embodiments the amount may be increased more or less. In this preferred embodiment, the wet oxidation is performed at about 1000 degrees celsius. A protective layer 78 (fig. 8) and a layer 76 are formed, the layer 76 covering the oxide 72 along the sidewalls 51 including the wings 71, which acts like a multi-layer buffered local oxidation of silicon, facilitating the formation of a very thick silicon dioxide 79 without creating stress or dislocations at the bottom of the trenches 64-68. During the formation of silicon dioxide 79, field oxide 61 may be formed at opening 60.

Layers 62 and 78 are removed (fig. 8) leaving layer 76 to protect oxide 72. Layers 62 and 78 may be removed by a variety of well-known processes, preferably by a nitride wet strip operation such as hot phosphoric acid removal.

Fig. 10 illustrates an enlarged cross-sectional view of a portion of transistor 20at another subsequent stage in a particular embodiment of a method of forming transistor 20. Conductor 80 is formed within channels 64-68. Conductor 80 is typically formed by conformal coating with doped polysilicon that fills trenches 64-68. Thereafter, the polysilicon is etched to remove a portion of the polysilicon and leave another portion as conductor 80, filling the trench to a depth at least substantially equal to the depth of the bottom of region 43, so that the top of conductor 80 is not substantially deeper than the top of region 42 in the active area of transistor 21 and may be closer to surface 41. The active region is generally that portion of region 42 between gates 45-49 (see fig. 2). Some of the active areas are generally indicated by areas 52-54 (see fig. 2). The objective is to make sure that the top of conductor 80 is closer to surface 41 than the bottom of region 43 is to surface 41, so oxide 72 can serve as the gate dielectric for gates 45-49. For example, it may be desirable to ensure that the top of conductor 80 extends past the junction formed at the interface of regions 42 and 43. However, those skilled in the art recognize that there will always be some differences, such as process variations, such that some portions of conductor 80 may be deeper in the active area than the top of region 42. A portion of the polysilicon is removed leaving conductor 80 and the exposed portion of the polysilicon of layer 76 is also removed. Those skilled in the art will appreciate that conductor 80 may be a variety of other well-known conductor materials, such as WSi, W or other low resistance conductors. Where conductor 80 is formed of polysilicon, the polysilicon surface is used to form a silicide or other similar well-known conductor. Alternatively, conductor 80 may be formed as doped polysilicon surrounding a silicide core. For example, a portion of conductor 80 is formed using Chemical Vapor Deposition (CVD). After the first partial conductor 80 is formed, the remainder may form silicide, resulting in a structure of the conductor 80 having a silicide core surrounded by polysilicon.

Thereafter, a second oxide 83 is formed on the exposed portion of oxide 72 to a thickness greater than the thickness of oxide 72. Oxide 83 is also formed on surface 41 as insulator 84 and on top of conductor 80. Oxide 83 is typically no deeper than, and preferably not as deep as, the P-N junction formed at the interface between regions 42 and 43. Such a depth ensures that the insulator in the active gate region of transistor 21 remains thin. The oxide 83 and insulator 84 are formed by a variety of well known methods including thermal oxidation of the exposed silicon, CVD deposition, or other well known techniques.

Fig. 11 illustrates an enlarged cross-sectional view of a portion of transistor 20at a next subsequent stage in a particular embodiment of a method of forming semiconductor transistor 20. Removing the portion of oxide 83 overlying conductor 80 facilitates making electrical contact with conductor 80. Another conductor 86 is formed within the remaining openings of channels 64-68 to form electrical contact with conductor 80. Conductor 86 may be doped polysilicon, a metal conductor, a metal silicide, or the like. Conductor 86 reduces the gate resistance of transistor 21. Conductor 86 can be formed by a variety of methods including forming a conformal coating of doped polysilicon and removing portions of the conformal coating to leave conductor 86. In some trenches, such as trenches 64 and 68, the conformal coating may be patterned to leave conductors 87 electrically connected to conductors 80. The conductor 87 is optional and the conductor 87 may not be present in all embodiments.

Insulator 95 is typically formed over at least conductor 80, which conductor 80 is located in a channel in the active region of transistor 21, as described in channels 65-67. As is well known to those skilled in the art, channels 64-68 and conductors 80 and 86 generally extend laterally across surface 41 herein, out of the plane of the page depicted in FIG. 11, to facilitate making electrical contact with conductors 80 and 86.

In another particular embodiment of a method of forming conductors 80 and 86, a first conductor, such as conductor 80 formed as doped polysilicon, is formed within an opening, such as trench 66, proximate a dielectric, such as oxide 72. Thereafter, such as after forming oxide 83, a second conductor, such as a metal-silicon alloy, may be formed as a core extending within the first conductor. In this case, the second conductor is generally lower in resistivity than the first conductor. Such a configuration can reduce gate resistance. Additionally, a metal-silicon alloy can also be formed on the upper surface of the first conductor to further reduce the gate resistance.

Doped region 44 is formed within region 43 to facilitate forming a low resistance electrical contact to the first current carrying electrode of transistor 21.

Doped regions 91 and 92 may also be formed on surface 41. A mask is used to expose a portion of insulator 84. The exposed portion of insulator 84 is removed to reveal a portion of surface 41.

Fig. 12 illustrates an enlarged cross-sectional view of a portion of transistor 20at a next subsequent stage in a particular embodiment of a method of forming transistor 20. In some embodiments, optional conductor 89 may be formed over a portion of optional conductor 87. A dielectric 90, such as an inter-layer dielectric, is formed on substrate 40. Openings are formed in insulator 84 and dielectric 90 to expose regions 44, 91, and 92.

Referring again to fig. 2, a conductor material is formed within the opening in dielectric 90. The conductor material may be a variety of well-known conductor materials including aluminum, aluminum-silicon, polysilicon, WSi, W, or a combination of conductive materials. In a preferred embodiment, the coating of conductive material is patterned to form conductors 119, 120, 121, 125, and 126. Conductor 120 is formed to make electrical contact to region 93 and, through electrical contact to region 103, to the drain of transistor 29. A portion of dielectric 90 insulates conductor 120 from a portion of the surface of substrate 40. Conductor 120 connects the drain of transistor 29 to CCE2 of transistor 21. Conductor 121 is formed to make electrical contact to region 42 via region 92 and to region 105 in order to connect body 22 to the source of transistor 29. Another portion of dielectric 90 insulates conductor 121 from a portion of the surface of substrate 40. The conductor 119 extends to overlie all of the regions 44 and makes electrical contact with all of the regions 44 to form the CCE1 of the transistor 21. Other regions of dielectric 90 insulate conductors 119 from gates 45-49. Conductor 125 is formed to make electrical contact to region 91, and regions 113 and 114, so as to form an electrical contact between body 22 and the source of transistor 27. Another portion of dielectric 90 insulates conductor 125 from other portions of transistors 21 and 27. Conductor 126 is formed to make electrical contact to region 112 in order to form an electrical connection to the source of transistor 27. A portion of the conductor 126 extends across the substrate 40 to electrically connect the conductor 126 to the conductor 119, and thus to the CCE1, and to the gate of the transistor 29. Additionally, a portion of conductor 120 may extend across substrate 40 to connect the drain of transistor 29 to the gate of transistor 27. Those skilled in the art will appreciate that the use of multiple metal layers to facilitate the formation of connections between portions of transistor 20 will simplify the connections.

As will be appreciated by those skilled in the art from the foregoing description and fig. 1-12, the body 22 of transistor 21 formed by region 42 has electrical contacts via regions 91 and 92 that are spaced apart from the electrical contacts connected to CCE1 via region 44. Body 22 has separate electrical connections to conductors 121 and 125 and is not connected to CCE1 by conductor 119. Separating the electrical contact to the body from the electrical contact to CCE1 or to the source facilitates bidirectional current conduction through transistor 21 under the control of gates 45-49 without forcing current to flow through body diodes 23 and 24.

Fig. 13 and 14 illustrate enlarged cross-sectional views of a portion of transistor 20 that include alternative methods of forming at least the second insulator of gates 45-49, according to some stages of alternative embodiments of methods of forming transistor 20. This description generally begins after the steps described with respect to the description of fig. 9 are performed.

After removing the non-vertical portions of layers 62 and 78, as described with respect to the fig. 8 illustration, an optional third insulator, such as silicon dioxide 79, is formed, as described with respect to the fig. 9 illustration. Conductor 80 is formed within channels 64-68. As described hereinabove, conductor 80 is typically formed by conformal coating of doped polysilicon that fills trenches 64-68. Thereafter, the polysilicon is etched to remove a portion of the polysilicon and leave another portion as conductor 80, filling the trench to a depth at least substantially equal to the depth of the bottom of region 43, so that the top of conductor 80 is not substantially deeper than the top of region 42 within the active area of transistor 21 (e.g., between trenches 64-68). In some embodiments, the conductor material in some of the trenches, such as trenches 64 and 68, may be patterned as desired to form conductors 87. Thereafter, a protective layer 128 may be formed over conductors 80 in channels 65-67 to protect conductors 80. The protective layer 128 is typically an insulator such as silicon dioxide, but may be other insulators such as silicon nitride.

Referring to fig. 14, insulator 129 is formed in trenches 65-67 and overlies conductor 80. Insulator 129 may be a variety of dielectric materials including silicon dioxide, silicon nitride, or other well-known dielectric materials. Another protective layer 130 is formed over insulator 129 to reduce stress within transistor 20. Note that layer 128 also helps to reduce stress within transistor 20 in the case where insulator 129 is silicon nitride. Protective layers 128 and 130 are optional and may be omitted in some embodiments. For example, layer 128 and insulator 129 may be silicon dioxide, which forms a portion of dielectric 90. For this particular embodiment, layers 128 and 130 may not be used. Insulator 129, and optional layers 128 and 130, are generally disposed along the sidewalls of channels 65-67 and form a thick insulator for the second insulator of transistor 20. Oxide 72 plus insulator 129 forms a second insulator along the channel sidewalls and the insulator juxtaposed to region 43, the thickness of region 43 being greater than the thickness of the portion of oxide 72 juxtaposed to region 42. The use of silicon nitride for insulator 129 further increases the dielectric constant of the second insulator. Thereafter, the remainder of the transistor 21 is formed as described herein above.

In another embodiment, insulator 129 is not formed, but may be replaced with a semiconductor material such as polysilicon. For this particular embodiment, layer 128 is formed by oxidizing conductor 80 or other methods. Subsequently, a semiconductor material, such as doped or undoped polysilicon, is formed on layer 128. For example, semiconductor material is formed during the formation of gate conductors for other MOS transistors, such as transistors 27 and 29, that are disposed in other regions of substrate 40.

Fig. 15 and 16 illustrate enlarged cross-sectional views of a portion of transistor 20 that include alternative methods of forming at least the second insulator of gates 45-49 at some stages of another alternative embodiment of a method of forming transistor 20. This description generally begins after the steps described with respect to the description of fig. 9 are performed.

After removing the non-vertical portions of layers 62 and 78, as described with respect to the fig. 8 illustration, an optional silicon dioxide 79 is formed, as described with respect to the fig. 9 illustration. Conductor 80 is formed within channels 64-68. As described hereinabove, conductor 80 is typically formed by conformal coating of doped polysilicon that fills trenches 64-68. Thereafter, the polysilicon is etched to remove a portion of the polysilicon and leave another portion as conductor 80, filling the trench to a depth at least substantially equal to the depth of the bottom of region 43, so that the top of conductor 80 is not substantially deeper than the P-N junction at the interface of regions 42 and 43. In some embodiments, the conductor material in some of the channels, such as channels 64 and 68, may be patterned to form conductors 87.

A silicon nitride layer 133 is formed over conductor 80, with conductor 80 at least within channels 65-67. Layer 133 is typically formed by using a silicon nitride coating. The thickness of layer 133 is generally much less than the remaining depth of channels 65-67. Thereafter, layer 133 is covered with dielectric layer 134 and fills the remaining depth of the trench 65-67 opening. The material for layer 134 is preferably a material that is not etched by the method of etching layer 133, and a material that is etchable by the method of not etching layer 133. The material for layer 134 may be silicon dioxide, or a variety of other well-known dielectrics. For example, layer 134 may be formed with a TEOS coating.

Referring to fig. 16, portions of layer 134 are thereafter removed, leaving other portions of layer 134 within trenches 65-67 as dielectric fill 136. Preferably, this portion of layer 134 is removed by an anisotropic etch that removes the horizontal device portions of layer 134 while leaving the vertical portions as spacers 138. Such an etch is terminated after the underlying layer 133 is exposed, thereby leaving a portion of layer 134 within trenches 65-67 to fill trenches 65-67. Subsequently, the exposed portion of layer 133 is removed, leaving the other portion of layer 133 underlying dielectric fill 136 as a nitride liner 137. The exposed portions of layer 133 are removed by a nitride wet strip etch that does not etch the filler 136 material. Dielectric fill 136 may also be formed as a portion of dielectric 90 or another dielectric. For example, fill 136 may be formed by applying a coating of dielectric material and removing portions outside of trenches 65-67, or fill 136 may be selectively formed using a mask. Oxide 72 plus liner 137 and dielectric fill 136 form a second insulator along the trench sidewalls that is juxtaposed to region 43, with the thickness of region 43 being greater than the thickness of oxide 72 juxtaposed to region 42. Likewise, forming dielectric fill 136 leaves an associated plane on which other MOS devices may be formed. In addition, dielectric fill 136 helps to reduce the field effect of the upper region of the gate of transistor 20. Those skilled in the art will appreciate that conductor 80 is formed with a silicide core in order to reduce the gate resistance of transistor 20, as explained in the illustration of fig. 10.

Fig. 17 illustrates a partial cross-sectional portion of another embodiment of a MOS transistor 145 at a stage in the method of forming transistor 145. Transistor 145 is typically a vertical channel type MOS transistor, similar to transistor 20, however, transistor 145 does not include region 43 and the body of transistor 145 is connected to the source. In forming transistor 145, until conductor 80 is formed as described in the description of fig. 9, it is similar to transistor 20. However, instead of forming region 43, region 42 is formed to extend all the way to surface 41 without region 43.

A first conductor 151 is formed within channels 64-68. Second conductor 149 is formed to extend into conductor 151 such that conductor 151 is located between conductor 149 and oxide 72. Conductor 151 is similar to conductor 80 and is typically made of the same material as conductor 80. Conductor 151, however, typically fills trenches 64-68 to the extent close to surface 41 or even substantially the same as surface 41, rather than filling the trenches to the depth used for conductor 80. Second conductor 149 is a conductor having a lower resistivity than the material used for conductor 151. Conductor 149 is preferably a metal-silicon alloy, such as tungsten-silicon (WSi2), titanium-silicon (TiSi2), platinum-silicon (PtSi), or aluminum-silicon (AlSi), but may be other conductor materials having a lower resistivity than the material of conductor 151. This structure reduces the gate resistance of transistor 145. Conductor 151 may be formed by applying a thin layer of doped polysilicon that coats the sidewalls and bottom of trenches 64-68, leaving only an opening in the middle of the trench. Conductor 149 is formed to fill the remaining portion of the opening in the trench. For example, a metal-silicon alloy, such as WSi, may be deposited to fill the remainder of the opening. Alternatively, a metal may be deposited, followed by annealing to form the metal-silicon alloy. In another method of forming conductor 149, conductor 151 may be omitted. Because layer 76 was formed earlier, a thin layer of polysilicon is typically on oxide 72. In this case, the remaining portion of the trench may be filled with a metal-silicon alloy to form the second conductor, while layer 76 forms the first conductor. Polysilicon layer 76 is typically thick enough to avoid the metal-silicon alloy adversely affecting the work function of the resulting gate of transistor 145. Depositing the metal-silicon alloy or metal may be accomplished by well-known methods such as Chemical Vapor Deposition (CVD) processes. The method of forming conductors 149 and 151 is also typically to form such conductors on layer 59. Portions of conductors 149 and 151 on layer 59 may be removed, leaving conductors 149 and 151 in the channel. Typically, a portion of conductor 149 is first removed, for example, by a fluorine/chlorine chemical reaction. When a portion of conductor 149 is removed, a chemical reaction is altered, for example to a bromine/chlorine chemical reaction, to etch away a portion of conductor 151 from layer 59. The chemistry used to remove portions of conductors 149 and 151 is generally more corrosive to the material of conductor 151, which leaves the tips of conductors 149 extending beyond the surface of conductor 151.

A metal-silicon alloy (not shown) may also be formed on the top surface of conductor 151 to further reduce gate resistance. Subsequently, a doped region 147 is formed on substrate 40 to serve as the source of transistor 145. Doped region 146 is formed to pass through the source of region 147 into region 42 to serve as the body contact region for transistor 145. Subsequently, dielectric 90 is formed over conductors 149 and 151 to insulate them from other elements of transistor 145. Thereafter, openings are formed through dielectric 90 and layer 59 to expose regions 146 and 147. Conductor 119 is formed to electrically contact the source of region 147 and the body of transistor 145 through region 146. Those skilled in the art will recognize that the gate structure, including conductors 149 and 151, typically extends through substrate 40 and thus forms a contact at a point outside the active area of transistor 145.

In view of all of the above, it is evident that a novel device and method is disclosed. Among other features, including the selective formation of nHV regions under the region about the first current carrying electrode (CCE1) may be advantageous to withstand high reverse voltages across transistor 20. Forming the second insulator to be thicker than the first insulator facilitates a transistor having a high reverse breakdown voltage while still having a low gate-to-source/drain capacitance and a low on-resistance.

While the subject matter of the invention is described using specific preferred embodiments, many alternatives and variations will be apparent to those skilled in the semiconductor arts. Although the method of forming a transistor is described with respect to forming a bidirectional transistor, the method is also applicable to forming a unidirectional transistor. Those of ordinary skill in the art will recognize that the illustrated steps constitute only a portion of the processing steps required to form transistor 20. Moreover, the word "connected" is used throughout for clarity of description, but is also meant to have the same meaning as the word "coupled". Thus, "connected" should be interpreted to include direct and indirect connections.

Claims (3)

1. A MOS transistor, comprising:

a substrate having a first conductivity type;

a body region of the transistor formed as a first doped region of a second conductivity type in the substrate having a first doping concentration and electrically connected to the conductor;

a high voltage region of the transistor formed as a second doped region having a second doping concentration of the first conductivity type, wherein the second doping concentration is less than the first doping concentration, and wherein the high voltage region overlies at least a portion of the body region;

an opening extending into the substrate and into the first doped region and the second doped region, the opening having a sidewall; and

a gate structure of a MOS transistor within the opening, the gate structure including a first insulator having a first thickness along a first portion of the sidewall adjacent the body region, the gate structure further including a second insulator having a second thickness along another portion of the sidewall adjacent the high voltage region, wherein the second thickness is greater than the first thickness.

2. The MOS transistor of claim 1, further comprising a third doped region of the first conductivity type overlying a portion of the second doped region.

3. The MOS transistor of claim 2, wherein the second doped region is connected to a first conductor, the body region is electrically connected to a second conductor, and the second conductor is not directly connected to the first conductor.