HK1191444B - Method of making an insulated gate semiconductor device having a shield electrode structure - Google Patents

Description

Method for manufacturing insulated gate semiconductor device having shield electrode structure

Cross Reference to Related Applications

This application is related to AN application entitled "METHOD OF creating AN electric device with a case number ONS01413F2, having a common assignee and co-inventors, filed concurrently with the present application.

Technical Field

This document relates generally to semiconductor devices and, more particularly, to methods of forming insulated gate devices and structures.

Background

Metal oxide field effect semiconductor transistor (MOSFET) devices have been used in many power switching applications, such as DC-DC converters. In a typical MOSFET, a gate electrode provides on and off control by applying an appropriate gate voltage. For example, in an N-type enhancement MOSFET, conduction occurs when a conductive N-type inversion layer (i.e., channel region) is formed within a P-type body region in response to application of a positive gate voltage that exceeds an intrinsic threshold voltage. The inversion layer connects the N-type source region to the N-type drain region and allows majority carriers to conduct between these regions.

There is a class of MOSFET devices in which a gate electrode is formed within a trench extending downwardly from a major surface of a semiconductor material (e.g., silicon). In this type of device current flows through the device mainly in the vertical direction and thus the device cells can be packed more tightly. All other things being equal, packing tighter device units can increase current carrying capability and reduce on-resistance of the device.

Achieving reduced specific on-resistance (ohms per unit area) performance is an important goal for MOSFET device designers. The reduced specific on-resistance enables product cost and gross margin or profitability to be determined for the MOSFET design. For example, a low specific on-resistance allows for a smaller MOSFET die or chip, which in turn results in lower cost in terms of semiconductor materials and package structure. However, challenges remain in fabricating higher density MOSFET devices that can achieve desired performance, including reduced specific on-resistance. Such challenges include: providing reliable die size reduction, reducing manufacturing costs, simplifying process steps, and improving yield.

Accordingly, it is desirable to have methods and structures for reducing cell pitch, reducing manufacturing costs, simplifying processing steps, improving yield, or combinations thereof. Further, methods and structures for maintaining or improving electrical performance are advantageous over related structures.

Disclosure of Invention

According to an aspect of the present invention, there is provided a method for manufacturing an insulated gate semiconductor device having a shield electrode structure, comprising the steps of: providing a region of semiconductor material having a major surface; forming a trench extending from the major surface into the region of semiconductor material; forming a first dielectric layer along a surface of the trench; forming a first conductive layer adjacent to the first dielectric layer, wherein the first conductive layer is configured as a shield electrode; removing portions of the first dielectric layer from upper sidewall surfaces of the trench; thereafter forming a gate dielectric layer along the upper sidewall surfaces of the trench; forming a first spacer layer adjacent to the gate dielectric layer; forming a second dielectric layer covering the first conductive layer; removing the first spacer layer; and forming a second conductive layer adjacent to the gate dielectric layer and the second dielectric layer, wherein the second conductive layer is configured as a control electrode.

According to one aspect of the invention, wherein the step of forming the first spacer layer may comprise forming the first spacer layer comprising an oxidation resistant material, and wherein the step of removing the first spacer layer comprises etching the first spacer layer.

According to one aspect of the invention, wherein the step of forming the first spacer layer may comprise forming a nitride spacer layer.

According to an aspect of the invention, further comprising the step of forming a second spacer layer between the gate dielectric layer and the first spacer layer.

According to an aspect of the invention, wherein the step of forming said second spacer layer comprises forming a crystalline semiconductor spacer layer.

According to an aspect of the invention, wherein the step of forming the second dielectric layer may comprise forming the second dielectric layer using local oxidation.

According to one aspect of the invention, wherein the step of forming the first conductive layer may comprise the step of recessing the first conductive layer below an upper surface of the first dielectric layer.

According to an aspect of the present invention, the method may further include the steps of: forming a first doped region within the region of semiconductor material, wherein the first doped region and trench are contiguous, and wherein the first doped region has a first conductivity type; and forming a second doped region adjacent to the first doped region, wherein the second doped region has a second conductivity type opposite to the first conductivity type.

According to an aspect of the present invention, the method may further include the steps of: forming a third dielectric layer overlying the major surface; forming a fourth dielectric layer overlying the third dielectric layer, wherein the third and fourth dielectric layers comprise different materials, and wherein the third and fourth dielectric layers are formed prior to the step of forming the trench; and etching to remove the first spacer layer and the fourth dielectric layer after the step of forming the second dielectric layer.

According to an aspect of the invention, wherein the step of forming the trench may include forming the trench with sloped sidewalls.

According to an aspect of the invention, the step of forming the first dielectric layer may comprise the steps of: forming a first oxide layer comprising a thermal oxide; forming a second oxide layer comprising a deposited oxide; removing upper portions of the first and second oxide layers along the upper sidewall surfaces of the trench prior to the step of forming the gate dielectric layer, wherein the step of removing exposes upper portions of the first conductive layer; and removing a portion of the first conductive layer to recess the first conductive layer below the upper surfaces of the first and second oxide layers.

According to another aspect of the present invention, there is provided a process for forming an insulated gate semiconductor device, comprising the steps of: forming a first trench extending from the main surface in the substrate; forming a shield electrode dielectric layer along a surface of the trench; forming a shield electrode adjacent to the shield electrode dielectric layer, wherein the shield electrode dielectric layer separates the shield electrode from the substrate; removing portions of the shield electrode dielectric layer from upper sidewall surfaces of the trench; forming a gate dielectric layer along the upper sidewalls of the trench; forming a spacer layer along the gate dielectric layer, wherein the spacer layer comprises an oxidation resistant material; thereafter forming a dielectric layer overlying the shield electrode using an oxidation process; removing the spacer layer; forming a gate electrode adjacent to the gate dielectric layer; forming a body region of a first conductivity type within said substrate, wherein said body region and said trench are contiguous; and forming a source region of the second conductivity type in spaced relation to the body region.

According to one aspect of the invention, wherein the step of forming the spacer layer may comprise forming a nitride spacer layer, and wherein the step of removing the spacer layer comprises etching the nitride spacer layer.

According to an aspect of the invention, a step of forming a crystalline semiconductor spacer between the nitride spacer and the gate dielectric layer may also be included.

According to an aspect of the invention, there may be further included a step of forming a masking layer overlying the major surface prior to the step of forming the trench, wherein the masking layer comprises a dielectric layer, and wherein the dielectric layer and the spacer layer comprise a nitride material.

According to another aspect of the present invention, there is provided a method for forming a semiconductor device, comprising the steps of: providing a substrate having a trench and a first electrode, the first electrode being in a lower portion of the trench and being isolated from the substrate by a dielectric layer formed along a surface of the trench; removing portions of the dielectric layer along upper sidewall surfaces of the trench; forming a gate dielectric layer along the upper sidewalls of the trench; forming a first spacer layer along the gate dielectric layer, wherein the first spacer layer comprises an oxidation resistant material; forming an inter-electrode dielectric layer adjacent to the first electrode and a lower portion of the gate dielectric layer using a local oxidation process, wherein the local oxidation process increases a thickness of the lower portion; removing the first spacer layer; and forming a second electrode adjacent to the first dielectric layer.

According to an aspect of the present invention, a step of forming a second spacer layer between the gate dielectric layer and the first spacer layer may be further included.

According to one aspect of the invention, wherein the step of forming the first spacer layer may comprise forming a nitride spacer layer, and wherein the step of removing the first spacer layer comprises etching the nitride spacer layer.

According to one aspect of the invention, wherein the step of forming the second spacer comprises forming a polysilicon spacer.

According to one aspect of the invention, wherein the step of forming the second spacer layer comprises forming an amorphous silicon spacer layer.

Drawings

FIGS. 1-9 illustrate partial cross-sectional views of a semiconductor device at various stages of manufacture according to a first embodiment of the present invention;

fig. 10 shows a partial cross-sectional view of a semiconductor device at an intermediate step of manufacture according to a second embodiment of the present invention; and

fig. 11-17 show partial cross-sectional views of the semiconductor device of fig. 1-9 at more stages of fabrication.

For simplicity and clarity of illustration, elements in the figures are not necessarily drawn to scale, and the same reference numbers generally indicate the same elements in different figures. Accordingly, descriptions and details of well-known steps and elements may be omitted for simplicity of the description. As used herein, current carrying electrode means a device element that carries current through the device, e.g., a source and drain region of an MOS transistor, an emitter or collector of a bipolar transistor, or a cathode or anode of a diode, while a control electrode means a device element that controls current through the device, e.g., a gate of an MOS transistor or a base of a bipolar transistor. Although these devices are explained herein as specific N-channel devices, it will be understood by those skilled in the art that P-channel devices and complementary devices are equally possible in light of the description of the present invention. For clarity of the drawings, the doped regions of the device structure are shown as having generally straight edges and angularly precise corners; however, it will be appreciated by those skilled in the art that the edges of the doped regions are not generally straight lines and the corners are not precise angles due to the diffusion and activation of the dopants.

Also, the term "major surface" when used in conjunction with a semiconductor region or substrate means a surface of the semiconductor region or substrate that forms an interface with another material (e.g., an electrical dielectric, insulator, conductor, or polycrystalline semiconductor). The major surface may have a topography that varies in the x, y, and z directions.

In addition, the structures in the description of the present invention may be implemented as a cellular matrix design (in which the bulk regions are a plurality of separate distinct cellular regions or ribbon-like regions) or a single matrix design (in which the bulk regions are a single region formed in an elongated pattern, typically in a serpentine pattern or with a central portion of the attachment attached). However, for ease of understanding, one embodiment in the description of the present invention will be described herein as a honeycomb matrix design. It should be understood that the present disclosure encompasses both honeycomb matrix designs and single matrix designs.

Detailed Description

Fig. 1 shows a partial cross-sectional view of a semiconductor device 10 or cell 10 at an early stage of manufacture according to a first embodiment. Device 10 includes a region of semiconductor material, semiconductor substrate, or semiconductor region 11, which may be, for example, an N-type silicon substrate 12 having a resistivity of approximately 0.001-0.005 ohm-cm. For example, substrate 12 may be doped with phosphorus, arsenic, or antimony. In the illustrated embodiment, substrate 12 provides a drain region, a drain contact, or a first current carrying contact for device 10. In this embodiment, the device 10 may comprise an active region 102 and a contact region 103, in which contact region 103 a contact to a shielding electrode structure, e.g. as described below, may be achieved. Further, in the present embodiment, device 10 may be configured as a vertical power MOSFET structure, but the description is equally applicable to Insulated Gate Bipolar Transistors (IGBTs), MOS-gated thyristors, and other related or equivalent structures known to those skilled in the art.

Semiconductor layer, drift region or extended drain region 14 may be formed within, on or overlying substrate 12. in one embodiment, semiconductor layer 14 may be formed using semiconductor epitaxial growth techniques alternatively, semiconductor layer 14 may be formed using semiconductor doping and diffusion techniques in an embodiment suitable for a 50 volt device, semiconductor layer 14 may be N-type with a doping concentration of about 1.0 × 10¹⁶-1.0×10¹⁷Atoms per cubic centimeter (atoms/cm)³) And may have a thickness of about 3-5 microns. The doping concentration and thickness of semiconductor layer 14 may be based on the desired source-drain Breakdown Voltage (BV) of device 10_DSS) Is increased or decreased by the rated value (rating). In one embodiment, semiconductor layer 14 may have a graded dopant profile. In alternative embodiments, the conductivity type of substrate 12 may be opposite to the conductivity type of semiconductor layer 14, forming embodiments such as IGBTs.

Masking layer 47 may be formed overlying major surface 18 of region of semiconductor material 11. In one embodiment, region of semiconductor material 11 also includes a major surface 19 opposite major surface 18. In one embodiment, masking layer 47 may comprise a dielectric film or a film that is resistant to the etch chemistry used to form the trenches described below. In one embodiment, masking layer 47 may include multiple layers including, for example, a 0.030 micron thermal oxide dielectric layer 471, an approximately 0.2 micron silicon nitride dielectric layer 472, and an approximately 0.1 micron deposited oxide dielectric layer 473. According to an embodiment, dielectric layer 472 may be configured to protect major surface 18 from erosion effects in subsequent process steps, e.g., occurring after formation of the trench structure. This erosion effect is a problem for related devices when thermal oxide is formed along the upper surface of the trench structure and proximate to the exposed portion of semiconductor layer 14 along major surface 18. The erosion problem may result in, among other problems, a non-uniform dielectric layer along major surface 18, which in turn may adversely affect the dopant profile of subsequently formed doped regions (e.g., body and/or source regions).

Openings 58 and 59 may then be formed within masking layer 47. In one embodiment, openings 58 and 59 may be formed using a photoresist and etching process. In one embodiment, opening 58 may have a width 16 of about 0.2-0.25 microns, and opening 59 may have a width 17 of about 0.4-0.5 microns. In one embodiment, the initial spacing 181 between the openings 58 may be about 0.55-0.65 microns.

After openings 58 and 59 are formed, sections of semiconductor layer 14 may be removed to form trenches 22 and 27 extending from major surface 18. For example, the trenches 22 and 27 may be treated with a fluorocarbon chemistry (e.g., SF)₆/O₂) Plasma etching techniques are performed. In one embodiment, trenches 22 and 27 may extend partially into semiconductor layer 14. In one embodiment, trenches 22 and 27 may extend through semiconductor layer 14 and into substrate 12. In one embodiment, trenches 22 and 27 may be formed in a single etch step without the use of sidewall spacers, which reduces the number of process steps and saves cost, as opposed to a multi-step etch process that uses sidewall spacers to define the deeper portions of the trenches. In one embodiment, a sloped sidewall etch may be used with a slope of, for example, approximately 88-89.5. For example, when SF is used₆/O₂With chemicals, the inclined side walls may be formed by increasing O₂Is achieved by the flow of₂An increase in flux will increase the sidewall Si-F-O passivating agent. When using a bevel etch, trenches 22 may be separated by a distance 182 of about 0.6-0.70 microns near the lower surface of trenches 22, as generally shown in FIG. 1. In one embodiment, trenches 22 and 27 may have a depth of about 1.5-2.5 microns. According to this embodiment, trenches 22 may be configured as trenches for gate electrodes and shield electrodes of active devices of device 10 formed within active region 102, while trenches 27 may be configured as contact trenchesA trench in which an external contact to the shield electrode within the contact region 103 may be formed. In one embodiment, contact region 103 may be located within a peripheral portion of device 10. In another embodiment, contact region 103 may be located within a central portion of device 10. In yet another embodiment, multiple contact zones 103 may be used. For example, one contact region may be disposed within a peripheral portion of device 10, while another contact region may be disposed within a central portion of device 10.

Fig. 2 shows a partial cross-sectional view of device 10 after additional processing. In an optional step, a sacrificial layer (not shown) is formed adjacent to the surfaces of trenches 22 and 27. For example, a thermal silicon oxide layer may be formed. The sacrificial layer and dielectric layer 473 can then be removed using, for example, an etching process. A layer of material 261 may then be formed along the surfaces of trenches 22 and 27. In one embodiment, layer 261 may be a dielectric material or an insulating material. For example, layer 261 may be a wet oxide layer or a thermal oxide layer of about 0.03 microns. Portions of semiconductor layer 14 may be consumed during the formation of the thermal oxide, which causes pitch 181 to be reduced by approximately that of the sacrificial layer (if used) and the thickness of layer 261, designated as reduced pitch or first reduction 1810. In one embodiment, the first reduction 1810 may be about 0.5-0.6 microns.

Fig. 3 shows a partial cross-sectional view of device 10 after further processing. Conformal layer 262 may be formed along sidewall portions of layer 261 and dielectric layer 472 and cover dielectric layer 472. In one embodiment, the conformal layer 262 may be a dielectric material or an insulating material. In one embodiment, the conformal layer 262 may be a deposited oxide. In one embodiment, rather than using sidewall spacers and local oxidation techniques to form the shield electrode dielectric along only the lower surface of the trench, dielectric layer 261 and conformal layer 262 are formed along the entire surface of trench 22, which can result in variability in gate length control, increased gate-drain capacitance due to longer bird's beak effects, and impact device shrinkage due to additional and greater erosion of adjacent semiconductor layers. For example, the conformal layer 262 may have a thickness of about 0.05-0.1 microns. In an alternative embodiment, conformal layer 262 may be formed by depositing a polysilicon layer and fully oxidizing it to convert it to a thermal oxide. In one embodiment, layers 261 and/or 262 are configured as a shield electrode dielectric layer or structure 259, which dielectric layer or structure 259 separates, insulates, or spaces the shield electrode (e.g., element 21 shown in fig. 17) from semiconductor layer 14 and substrate 12 (if trench 22 is adjacent to substrate 12). In one embodiment, shield electrode dielectric structure 259 may be formed in the absence of nitride material, as it has been found that nitride material in the associated device may trap undesirable charge under reverse bias conditions or under Unclamped Inductive Switching (UIS) conditions, which may lead to unstable breakdown voltage characteristics.

In one embodiment, a layer of material may be formed overlying major surface 18 and within trenches 22 and 27. In one embodiment, the material layer may be a crystalline semiconductor material, a conductive material, or a combination thereof. In one embodiment, the material layer may be doped polysilicon. In one embodiment, the polysilicon may be doped with an N-type dopant, such as phosphorus or arsenic. In a subsequent step, the material layer may be planarized to form intermediate structures 1021 and 1141 within trenches 22 and 27, respectively. In one embodiment, chemical mechanical polishing techniques may be used for the planarization step. When the material layer comprises a crystalline semiconductor material, the material layer may be heat treated before or after planarization, for example, to activate and/or diffuse any dopant material present within the crystalline semiconductor material.

Fig. 4 shows a partial cross-sectional view of device 10 after further processing. For example, the intermediate structures 1021 and 1141 may be further recessed within the trenches 22 and 27 to form the shield electrode 21 and the shield electrode contact portion 141. For example, dry etching with fluorine or chlorine based chemistry may be used for the recessing step. In one embodiment, an etching step (e.g., a wet etching step) may be used to remove conformal layer 262 overlying dielectric layer 472 and along sidewall portions of dielectric layer 472. A wet etch step may be used to further remove the conformal layer 262 and the layer 261 from the upper sidewall portions or sidewall portions 221 of the trenches 22 and from the upper sidewall portions or sidewall portions 271 of the trenches 27, as shown in fig. 5. In one embodiment, a buffered hydrofluoric acid (HF) strip may be used. The etching step may also expose portions 210 of shield electrode 21 and portions 1410 of shield electrode contact portion 141, for example, as shown in fig. 5.

Fig. 6 shows a partial cross-sectional view of device 10 after additional processing. In one embodiment, dielectric layer 266 can be formed along sidewall portions 221 and 271 and along exposed portions 210 and 1410. In one embodiment, the dielectric layer 266 may be a thin sacrificial or thermal oxide layer, or another dielectric or insulating layer. In one embodiment, dielectric layer 266 may have a thickness of about 0.005-0.01 microns. Subsequently, an etching step may be used to remove additional portions of shield electrode 21 and shield electrode contact portion 141, e.g., as shown in fig. 7. In one embodiment, the portion of dielectric layer 266 overlying shield electrode 21 and shield electrode contact portion 141 may be removed with an initial break-through etch or removal step. For example, fluorine-based chemistries may be used for the breakthrough step, while fluorine or chlorine-based chemistries may be used for the recess etch step.

Fig. 8 shows a partial cross-sectional view of device 10 after further processing. In one embodiment, a removal step may be used to remove dielectric layer 266 and portions of layers 261 and 262. Then, according to the present embodiment, dielectric layers are formed along sidewall portions 221 and 227 of trenches 22 and 27. In one embodiment, a dielectric layer may also be formed overlying portions of layers 261 and 262, shield electrode 21, and/or shield electrode contact 141. According to this embodiment, the dielectric layer forms a gate layer or gate dielectric layer 26 along the upper sidewall surfaces 221 of the trenches 22. The gate layer 26 may be an oxide, nitride, tantalum pentoxide, titanium dioxide, barium strontium titanate, high dielectric constant (high-k) dielectric material, combinations thereof, or other related or equivalent materials known to those skilled in the art. According to the present embodiment, gate layer 26 is formed after shield electrode dielectric structure 259 is formed. Forming gate layer 26 after forming shield electrode dielectric structure 259 reduces exposure of gate layer 26 to multiple plasma etch and other etch steps that may lead to yield problems and gate control problems, thereby improving the performance of device 10. In one embodiment, gate layer 26 may be silicon oxide and may have a thickness of about 0.01-0.06 microns. Portions of semiconductor layer 14 may be further consumed in the formation of gate layer 26, which may cause spacing 181 to approximately reduce the thickness of gate layer 26. This reduction in pitch 181 is designated as a reduced pitch or second reduction 1811. In one embodiment, the second reduction 1811 may be about 0.045-0.055 microns.

In the presence of layers 261 and 262 along the lower sidewall portions of trench 22 and when gate layer 26 is formed after shield electrode dielectric structure 259 is formed, lower portion 260 of gate layer 26 within trench 22 may be thinner than an upper portion of gate layer 26. This thinning is believed to be caused at least in part by the stresses present in the various material layers in which thinning occurs in the vicinity thereof. Although forming gate dielectric layer 26 after formation of layers 261 and 262 may improve the integrity of gate dielectric layer 26, the thinning of the gate dielectric layer may result in reduced yield and/or impaired device performance. According to the present embodiment, the influence of the thinning effect is reduced.

Fig. 9 shows a partial cross-sectional view of device 10 after additional processing. In subsequent steps, a layer of material is formed along gate layer 26 and overlying major surface 18. In one embodiment, the material layer may be a different material than the gate layer 26. In one embodiment, the material layer may be an oxidation resistant material. Then, the material layer may be anisotropically etched to form the spacer layer 55 along the sidewall portions of the gate layer 26, while leaving other portions of the gate layer 26 exposed over the shield electrode 21 and the shield electrode contact portion 141. In one embodiment, the spacer layer 55 may be a nitride material, such as deposited silicon nitride. In one embodiment, the spacer layer 55 may have a thickness of about 0.015-0.02 microns. In one embodiment, the lower portion of spacer layer 55 is adjacent to and/or fills in lower portion 260 of gate layer 26, for example, as shown in fig. 9.

Fig. 10 shows a partial cross-sectional view of a device 10 according to an alternative embodiment. In an alternative processing step, a layer of crystalline semiconductor material may be formed along gate layer 26 and overlying major surface 18 prior to the formation of the layer of material used to form spacer layer 55. Then, the material layer used to form the spacer layer 55 may be formed along the crystalline semiconductor material layer. Both layers may then be anisotropically etched to form spacers 55 and 56, for example, as shown in FIG. 10. Alternatively, the layer of crystalline semiconductor layer may be anisotropically etched prior to formation of layer 55. In one embodiment, the spacer layer 56 may comprise about 0.03 microns of polysilicon and may be doped or undoped. In another embodiment, the spacer layer 56 may comprise 0.03 microns of amorphous silicon and may be doped or undoped.

Fig. 11 shows a partial cross-sectional view of device 10 after additional processing based on the embodiment of fig. 9. According to the present embodiment, the layer 127 may be formed adjacent to the shielding electrode 21 and the shielding electrode contact portion 141. In one embodiment, layer 127 may comprise a dielectric or insulating material and be configured, for example, as an inter-poly dielectric layer or an inter-electrode dielectric layer. In one embodiment, layer 127 may comprise silicon oxide formed using a wet oxidation technique. In one embodiment, layer 127 may have a thickness of about 0.1-0.3 microns. According to the present embodiment, spacers 55 (and optionally spacers 56) are configured to provide a local oxidation that compensates for the thinning of gate layer 26 along lower portion 260. In one embodiment, layer 127 increases the thickness of gate layer 26 near where gate layer 26 and shield dielectric structure 259 meet or abut.

In related devices formed after the formation of a gate dielectric layer over an interpoly dielectric layer, gate thinning is not adequately addressed, which can lead to yield degradation and/or device performance impairment. In the present embodiment, the dielectric layer used to form gate layer 26 is formed prior to formation of inter-poly dielectric layer 127, and according to the present embodiment, the effect of gate layer thinning is reduced with a local oxidation process, thereby improving, for example, performance and yield. Therefore, the influence of the thinning effect can be reduced, and the interpoly dielectric can be formed without increasing the process cost. Also, because gate layer 26 is formed prior to the formation of layer 127, rather than being later stripped and re-formed as in the related device, the integrity of the interface between semiconductor layer 14 and gate layer 26 can be maintained.

Fig. 12 shows a partial cross-sectional view of device 10 after further processing. In a subsequent step and according to the present embodiment, the spacers 55 (and 56, if present) are removed by etching or lift-off or another physical removal process. According to the present embodiment, the spacers 55 are physically removed, as opposed to exposing the spacers 55 to a sacrificial process that converts the spacers 55 to a different material, typically with the spacers 55 remaining in place. Related devices using, for example, nitrided gates or nitride depleted gate structures are known to have yield and performance issues related to high oxide charge, high interface state density, and poor film uniformity. In this embodiment, the physical removal of spacers 55 reduces the above-described problems, thereby improving the performance of device 10. In one embodiment, the dielectric layer 472 may also be removed. In an optional step, an oxidation process may be used to increase or increase the thickness of the gate layer 26. Subsequently, a conductive or crystalline semiconductor layer 281 may be formed overlying major surface 18 and formed within trenches 22 and 27. In one embodiment, layer 281 may comprise doped polysilicon. In one embodiment, the polysilicon may be doped with an N-type dopant, such as phosphorus or arsenic. Subsequently, a masking layer (not shown) may be formed overlying major surface 18, and a removal step may be used to remove portions of layer 281 from within trenches 27. The masking layer may then be removed.

According to this embodiment, a layer of material may be formed overlying major surface 18 and along portions of trenches 27. In one embodiment, the material layer may be a dielectric material or an insulating material. In one embodiment, the layer of material may include a deposited oxide and may have a thickness of approximately 0.08-0.12 microns. The material layer may then be anisotropically etched to form spacer layer 68 within trench 27. An anisotropic etch step may also remove portions of layer 127 to form opening 1270 within layer 127 in trench 27, thereby exposing a portion of shield contact portion 141. According to the present embodiment, the shield contact portion 141 is configured to provide a planar or horizontal portion 1410 for making subsequent contact with another shield electrode portion 142 (shown in fig. 14). In one embodiment, planar portion 1410 may be oriented generally parallel to major surface 19 of substrate 12. In one embodiment, the planar portion 1410 may be oriented generally perpendicular to the sidewall portions 271 of the trench 27. The planar portion 1410 is also shown in fig. 13, which fig. 13 is a 90 degree rotation of the contact region 103 of the device 10. In one embodiment, planar portion 1410 terminates in a recessed configuration within trench 27 in contact region 103. Planar portion 1410 is an improvement over related devices in which the shield contact structure is bent up to major surface 18 as a single or continuous structure. It has been found that the formation of the bent portions of the shield contact structure is a source of yield problems in related devices. Fig. 13 also shows a gate electrode contact portion 282, which gate electrode contact portion 282 may also be formed within contact region 103 and configured to provide external electrical connection to gate electrode 28 within active portion 102 of device 10. In one embodiment, the gate electrode contact portion 282 may be formed as part of the layer 281.

Fig. 14 shows a partial cross-sectional view of device 10 after further processing. A layer of material may be formed overlying major surface 18 and formed within trench 27. In one embodiment, the layer of material may include a crystalline semiconductor material, a conductive material, or a combination thereof. In one embodiment, the layer of material may comprise doped polysilicon. In one embodiment, the polysilicon may be doped with an N-type dopant, such as phosphorus or arsenic. Subsequently, the layer of material may be planarized using the dielectric layer 471 as a stop layer. In one embodiment, chemical mechanical planarization may be used for the planarization step. This planarization step may be used to form the shield contact portion 142, the shield contact portion 142 being in contact with the shield contact portion 141 along the planar portion 1410 according to the present embodiment. In addition, the planarization step may form a gate electrode 28 within the trench 22, for example, as shown in fig. 14.

Subsequently, a masking layer (not shown) may be formed overlying contact region 103, and body, bulk, or doped region 31 may be formed extending from major surface 18 adjacent trench 22. Body region 31 may have a conductivity type opposite to that of semiconductor layer 14. In one embodiment, body regions 31 may have P-type conductivity and may be formed using, for example, a boron dopant source. Body region 31 has a doping concentration suitable for forming an inversion layer that may operate as a conduction channel or channel region 45 (e.g., as shown in fig. 17) of device 10. Body region 31 may extend from major surface 18 to a depth of, for example, approximately 0.5-2.0 microns. It should be understood that body region 31 may be formed at an earlier stage of fabrication, e.g., prior to formation of trench 22. Body region 31 may be formed using doping techniques such as ion implantation and annealing techniques.

Fig. 15 shows a partial cross-sectional view of device 10 after additional processing. In a subsequent step, masking layer 131 may be formed overlying portions of major surface 18. In one embodiment, source, current conducting, or carrying regions 33 may be formed in, within, or overlying body region 31 and may extend from major surface 18 to a depth of, for example, about 0.1-0.5 microns. In one embodiment, source regions 33 may have N-type conductivity and may be formed using, for example, phosphorus or arsenic dopant sources. In one embodiment, an ion implantation doping process may be used to form source regions 33 within body region 31. Then, the masking layer 131 may be removed, and the implanted dopant may be annealed.

Gate electrode 28 and shield electrode contact portion 142 may be recessed below major surface 18 as shown in fig. 16. In one embodiment, approximately 0.15-0.25 microns of material may be removed as a result of the recessing step. In an optional step, enhancement or conductive region 89 may be formed within the upper surface of gate electrode 28 and/or shield electrode contact portion 142. In one embodiment, the conductive region 89 may be a salicide structure. In one embodiment, the conductive region 89 may be cobalt silicide. A material layer 477 may then be formed overlying major surface 18, gate electrode 28, and shield electrode contact portion 142. In one embodiment, the material layer 477 may be a dielectric material or an insulating material. In one embodiment, the material layer 477 may be a nitride layer (e.g., a deposited silicon nitride layer) and may have a thickness of about 0.05 microns.

In one embodiment, one or more layers 41 may be formed overlying major surface 18. In one embodiment, layer 41 comprises a dielectric layer or an insulating layer and may be configured as an interlayer dielectric (ILD) structure. In one embodiment, layer 41 may be a silicon oxide, for example, a doped or undoped deposited silicon oxide. In one embodiment, layer 41 may comprise at least one layer of deposited silicon oxide doped with phosphorus or boron and phosphorus and at least one layer of undoped oxide. In one embodiment, layer 41 may have a thickness of approximately 0.4-1.0 microns. In one embodiment, layer 41 may be planarized to provide a more uniform surface topography, which may improve manufacturability.

Subsequently, a masking layer (not shown) may be formed overlying device 10, and openings, vias, or contact trenches 422 may be formed to make contact with source regions 33, body regions 31, and shield contact portions 142, for example, as shown in fig. 17. In one embodiment, the masking layer may be removed and a recess etch may be used to remove portions of source regions 33 and portions of shield contact portions 142. The recess etch step may expose portions of body region 31 below source regions 33. A P-type body region contact, enhancement region, or contact region 36 may then be formed within body region 31 that may be configured to provide a lower contact resistance with body region 31. Ion implantation (e.g., using boron) and annealing techniques may be used to form contact region 36.

Conductive region 43 may then be formed within contact trench 422 and configured to provide electrical contact to source region 33, body region 31 (via contact region 36), and shield electrode contact portion 142. In one embodiment, the conductive region 43 may be one or more conductive plug structures. In one embodiment, the conductive region 43 may include a conductive barrier structure or liner and a conductive filler material. In one embodiment, the barrier structure may comprise a metal/metal-nitride structure, such as titanium/titanium-nitride or other related or equivalent materials known to those skilled in the art. In another embodiment, the barrier structure may also include a metal-silicide structure. In one embodiment, the conductive fill material comprises tungsten. In one embodiment, the conductive region 43 may be planarized to provide a more uniform surface topography.

Conductive layer 44 can be formed overlying major surface 18 and conductive layer 46 can be formed overlying major surface 19. Conductive layers 44 and 46 are generally configured to provide electrical connections between individual device components of device 10 and components of the next level. In one embodiment, the conductive layer 44 may be titanium/titanium-nitride/aluminum-copper or other related or equivalent materials known to those skilled in the art and configured as a source electrode or terminal. In one embodiment, conductive layer 46 may be a solderable metal structure, such as titanium-nickel-silver, chromium-nickel-gold, or other related or equivalent materials known to those skilled in the art, and configured as a drain electrode or terminal. In one embodiment, another passivation layer (not shown) may be formed overlying conductive layer 44. In one embodiment, all or a portion of shielding electrode 21 may be connected to conductive layer 44, thereby configuring shielding electrode 21 to: which is at the same potential as source region 33 when device 10 is in use. In another embodiment, shield electrode 21 may be configured to be independently biased or partially coupled to gate electrode 28.

In one embodiment, the operation of device 10 may proceed as described below. Assume that the source electrode (or input terminal) 44 and the shield electrode 21 are at a potential V of 0 volts_SIn operation, the gate electrode 28 will receive a control voltage V of 4.5 volts_GThe control voltage V_GGreater than the turn-on threshold of device 10 and drain electrode (or output terminal) 46 will be at a drain potential V of less than 2.0 volts_DThe following operations are carried out. V_GAnd V_SMay cause body region 31 to invert adjacent gate electrode 28 to form channel 45, which channel 45 may electrically connect source region 33 to semiconductor layer 14. Device current I_DSWill flow from drain electrode 46 and be routed to source electrode 44 via semiconductor layer 14, channel 45, and source region 33. In one embodiment, I_DSOn the order of 10.0 amps. To switch device 10 to the off state, a control voltage V, which is less than the on threshold of device 10, is applied to gate electrode 28_G(e.g., V)_G<1.0 volts). The control voltage will remove channel 45, and I_DSNo longer flows through device 10. According to the present embodiment, gate layer 26 is formed before interpoly dielectric layer 127. Subsequent methods for forming interpoly dielectric layer 127 may reduce the thinning effect of the gate layer, which may improve yield and device performance. Further, by using multi-part shield contact structures (e.g., elements 141 and 142) and planar contact portions (e.g., element 1410), an improved shield electrode contact structure may be formed to provide electrical contact to shield electrode 21, which may improve yield and performance.

The above-described methods and structures provide several advantages over related devices. For example, the method may facilitate die shrink to about 0.8 microns or less, which may improve performance parameters, such as specific on-resistance. In addition, the method may promote higher yields and improved gate oxide performance as compared to some previous methods.

From all the above descriptions, the person skilled in the art can determine: according to one embodiment, a method for forming a semiconductor device includes: a region of semiconductor material (e.g., element 11) having a major surface (e.g., element 18) is provided. The method includes forming a trench (e.g., element 22) extending from a major surface into a region of semiconductor material. The method includes forming a first dielectric layer (e.g., elements 261, 262) along a surface of the trench, and forming a first conductive layer (e.g., element 21) adjacent to the first dielectric layer, wherein the first conductive layer is configured as a shield electrode. The method includes removing portions of the first dielectric layer from upper sidewall surfaces of the trench (e.g., element 221). The method includes thereafter forming a gate dielectric layer (e.g., element 26) along upper sidewall surfaces of the trench. The method includes forming a first spacer layer (e.g., element 55) adjacent to the gate dielectric layer and then forming a second dielectric layer (e.g., element 127) overlying the first conductive layer. The method includes removing the first spacer layer. The method includes forming a second conductive layer (e.g., element 28) adjacent to the gate dielectric layer and the second dielectric layer, wherein the second conductive layer is configured as a control electrode.

It will also be appreciated by those skilled in the art that, according to another embodiment of the invention, the method described in the preceding paragraph further comprises the steps of: a second spacer layer (e.g., element 56) is formed between the gate dielectric layer and the first spacer layer.

It will also be appreciated by those skilled in the art that the method described in the preceding paragraph further comprises the step of forming a second spacer layer (e.g. element 56) comprising forming a crystalline semiconductor spacer layer according to another embodiment of the present invention.

It will also be appreciated by those skilled in the art that, according to another embodiment of the invention, the method described in the preceding paragraph further comprises the steps of: forming a third dielectric layer (e.g., element 471) overlying the major surface, forming a fourth dielectric layer (e.g., element 472) overlying the major surface, wherein the third and fourth dielectric layers comprise different materials, and wherein the third and fourth dielectric layers are formed prior to the step of forming the trench, and etching to remove the first spacer layer and the fourth dielectric layer after the step of forming the second dielectric layer.

It will also be appreciated by those skilled in the art that, according to another embodiment of the invention, the method described in the preceding paragraph further comprises the steps of: forming a first oxide layer (e.g., element 261) comprising a thermal oxide, forming a second oxide layer (e.g., element 262) comprising a deposited oxide; the upper portions of the first and second oxide layers along the upper sidewall surface of the trench (e.g., element 221) are removed prior to the step of forming the gate dielectric layer, wherein the removing step exposes the upper portions (e.g., element 210) of the first conductive layer (e.g., element 21), and a portion of the first conductive layer is removed to recess the first conductive layer below the upper surfaces of the first and second oxide layers.

It will also be appreciated by those skilled in the art that, according to yet another embodiment, a process for forming an insulated gate semiconductor device comprises the steps of: a first trench (e.g., element 22) extending from a major surface (e.g., element 18) is formed within a substrate (e.g., element 11). The method includes forming a shield electrode dielectric layer (e.g., elements 261, 262) along a surface of the trench. The method includes forming a shield electrode (e.g., element 21) adjacent to a shield electrode dielectric layer, wherein the shield electrode dielectric layer separates the shield electrode from the substrate. The method includes removing portions of the shield electrode dielectric layer from upper sidewall surfaces of the trench (e.g., element 221). The method includes forming a gate dielectric layer (e.g., element 26) along upper sidewalls of the trench. The method includes forming a spacer layer (e.g., element 55) along the gate dielectric layer, wherein the spacer layer comprises an oxidation resistant material. The method includes thereafter forming a dielectric layer (e.g., element 127) overlying the shield electrode using an oxidation process. The method includes removing the spacer layer. The method includes forming a gate electrode (e.g., element 28) adjacent to the gate dielectric layer. The method includes forming a body region (e.g., element 31) of a first conductivity type within the substrate, wherein the body region is contiguous with the trench. The method includes forming a source region (e.g., element 36) of the second conductivity type spaced apart from the body region.

It will also be appreciated by those skilled in the art that, according to yet another embodiment, a method for forming a semiconductor device comprises the steps of: a region of semiconductor material (e.g., element 11) having a major surface (e.g., element 18) is provided. The method includes forming a masking layer (e.g., elements 47) overlying the major surface, wherein the masking layer includes at least one dielectric layer (e.g., 471, 472, 473). The method includes forming a trench (e.g., element 22) through an opening (e.g., element 58) in a masking layer within a region of semiconductor material. The method includes forming a first electrode dielectric layer (e.g., elements 261, 262) along a surface of the trench and forming a first electrode (e.g., element 21) adjacent to the first electrode dielectric layer. The method includes removing portions of the first electrode dielectric layer along upper sidewall surfaces of the trenches (e.g., elements 221). The method includes forming a gate dielectric layer along upper sidewall surfaces of the trench and forming a first spacer layer (e.g., element 55) along the gate dielectric layer. The method includes forming an inter-electrode dielectric layer (e.g., element 127) adjacent to the first electrode and the first spacer layer, wherein the inter-electrode dielectric layer increases a thickness of the gate dielectric layer proximate to where the gate dielectric layer meets the first electrode dielectric layer (e.g., element 260). The method includes removing the first spacer layer. The method includes forming a second electrode (e.g., element 28) adjacent to the gate dielectric layer. The method includes forming a first doped region (e.g., element 31) adjacent to the trench and forming a second doped region (e.g., elements 33, 36) adjacent to the first doped region.

It will also be appreciated by those skilled in the art that, according to yet another embodiment, a method for forming a semiconductor device comprises the steps of: a substrate (e.g., element 11) is provided having a trench (e.g., element 22) and a first electrode (e.g., element 21) within a lower portion of the trench and isolated from the substrate by a dielectric layer (e.g., elements 261, 262) formed along a surface of the trench. The method includes removing portions of the dielectric layer along upper sidewall surfaces of the trench (e.g., element 221). The method includes forming a gate dielectric layer (e.g., element 26) along upper sidewalls of the trench. The method includes forming a spacer layer (e.g., element 55) along the gate dielectric layer, wherein the spacer layer comprises an oxidation resistant material. The method includes thereafter forming an inter-electrode dielectric layer (e.g., element 127) adjacent to a lower portion (e.g., element 260) of the first electrode and gate dielectric layers using a local oxidation process that increases a thickness of the lower portion. The method includes removing the spacer layer. The method includes forming a second electrode (e.g., element 28) adjacent to the gate dielectric layer.

It will also be appreciated by those skilled in the art that, according to another embodiment, the method described herein may further include the step of forming the shield electrode dielectric structure in the absence of a nitride material.

It will also be appreciated by those skilled in the art that the method described herein may also include the step of forming the trench in a single etching step, according to another embodiment of the present invention.

In view of all of the above, it is evident that a novel process is disclosed herein. Including, among other features, forming an insulated shield electrode structure within a lower portion of the trench, forming a dielectric layer along upper sidewall portions of the trench, forming a spacer layer along the dielectric layer, and forming an interpoly dielectric layer overlying the insulated shield electrode structure. The method increases the thickness of the dielectric layer in the vicinity of the insulated shield electrode structure, which may improve yield and performance of, for example, submicron vertical power transistor devices. In addition, the method forms the gate dielectric layer prior to the formation of the interpoly dielectric layer, which maintains the integrity of the semiconductor material/gate dielectric layer interface, thereby further improving yield and performance.

While the present subject matter has been described in terms of certain preferred and exemplary embodiments, the foregoing drawings, and the description thereof, depict only typical embodiments of the subject matter and are not therefore to be considered to limit the scope of the invention. It is evident that numerous alternatives and variations will be apparent to those skilled in the art. For example, although the present subject matter has been described with respect to a particular N-channel MOSFET structure, the methods and structures are directly applicable to other MOS transistors, as well as bipolar transistors, BiCMOS, metal-semiconductor fets (mesfets), HFETs, thyristor bidirectional transistors, and other transistor structures.

As the following claims reflect, inventive aspects may lie in less than all features of a single foregoing disclosed embodiment. Thus, the claims set forth below are hereby expressly incorporated into this detailed description, with each claim standing on its own as a separate embodiment of this invention. Moreover, although some embodiments described herein include some features but not other features included in other embodiments, combinations of features of different embodiments are certainly within the scope of the invention, and form different embodiments, as would be understood by those of skill in the art.

Claims (10)

1. A method for manufacturing an insulated gate semiconductor device having a shield electrode structure, comprising the steps of:

providing a region of semiconductor material having a major surface;

forming a trench extending from the major surface into the region of semiconductor material;

forming a first dielectric layer along a surface of the trench;

forming a first conductive layer adjacent to the first dielectric layer, wherein the first conductive layer is configured as a shield electrode;

removing portions of the first dielectric layer from upper sidewall surfaces of the trench;

thereafter forming a gate dielectric layer along the upper sidewall surfaces of the trench;

forming a first spacer layer adjacent to the gate dielectric layer;

forming a second dielectric layer covering the first conductive layer;

removing the first spacer layer, wherein the gate dielectric layer remains along the upper sidewall surfaces of the trench after forming the second dielectric layer and after removing the first spacer layer; and

forming a second conductive layer adjacent to the gate dielectric layer and the second dielectric layer, wherein the second conductive layer is configured as a control electrode.

2. The method of claim 1, wherein forming the first spacer layer comprises forming the first spacer layer comprising an oxidation resistant material, and wherein removing the first spacer layer comprises etching the first spacer layer.

3. The method of claim 1, further comprising the step of forming a second spacer layer between the gate dielectric layer and the first spacer layer.

4. The method of claim 1, wherein forming the second dielectric layer comprises forming the second dielectric layer using local oxidation.

5. The method of claim 1, further comprising the steps of:

forming a first doped region within the region of semiconductor material, wherein the first doped region and trench are contiguous, and wherein the first doped region has a first conductivity type; and

a second doped region is formed adjacent to the first doped region, wherein the second doped region has a second conductivity type opposite the first conductivity type.

6. The method of claim 1, wherein the step of forming the first dielectric layer comprises the steps of:

forming a first oxide layer comprising a thermal oxide;

forming a second oxide layer comprising a deposited oxide;

removing upper portions of the first and second oxide layers along the upper sidewall surfaces of the trench to expose upper portions of the first conductive layer prior to the step of forming the gate dielectric layer; and

removing a portion of the first conductive layer to recess the first conductive layer below the upper surfaces of the first and second oxide layers.

7. A process for forming an insulated gate semiconductor device, comprising the steps of:

forming a first trench extending from the main surface in the substrate;

forming a shield electrode dielectric layer along a surface of the trench;

forming a shield electrode adjacent to the shield electrode dielectric layer, wherein the shield electrode dielectric layer separates the shield electrode from the substrate;

removing portions of the shield electrode dielectric layer from upper sidewall surfaces of the trench;

forming a gate dielectric layer along the upper sidewall surface of the trench;

forming a spacer layer along the gate dielectric layer, wherein the spacer layer comprises an oxidation resistant material;

thereafter forming a dielectric layer overlying the shield electrode using an oxidation process;

removing the spacer layer, wherein the gate dielectric layer remains along the upper sidewall surfaces of the trenches after forming the dielectric layer overlying the shield electrode and after removing the spacer layer;

forming a gate electrode adjacent to the gate dielectric layer;

forming a body region of a first conductivity type within said substrate, wherein said body region and said trench are contiguous; and

source regions of the second conductivity type are formed in spaced relation to the body regions.

8. The process of claim 7, wherein the step of forming the spacer layer comprises forming a nitride spacer layer, and wherein the step of removing the spacer layer comprises etching the nitride spacer layer, the process further comprising the step of forming a crystalline semiconductor spacer layer between the nitride spacer layer and the gate dielectric layer.

9. A method for forming a semiconductor device, comprising:

providing a substrate having a trench and a first electrode, the first electrode being in a lower portion of the trench and being isolated from the substrate by a dielectric layer formed along a surface of the trench;

removing portions of the dielectric layer along upper sidewall surfaces of the trench;

forming a gate dielectric layer along the upper sidewalls of the trench;

forming a first spacer layer along the gate dielectric layer;

forming a second spacer layer along the first spacer layer, wherein the second spacer layer comprises an oxidation resistant material;

forming an inter-electrode dielectric layer adjacent to the first electrode and a lower portion of the gate dielectric layer using a local oxidation process, wherein the local oxidation process increases a thickness of the lower portion of the gate dielectric layer;

removing the second spacer layer; and

a second electrode is formed adjacent to the gate dielectric layer.

10. The method of claim 9, wherein the gate dielectric layer remains along the upper sidewall surface of the trench after forming the inter-electrode dielectric layer and after removing the second spacer.