[go: up one dir, main page]

HK1051241B - 分布式存儲器控制和帶寬優化 - Google Patents

分布式存儲器控制和帶寬優化 Download PDF

Info

Publication number
HK1051241B
HK1051241B HK03103312.2A HK03103312A HK1051241B HK 1051241 B HK1051241 B HK 1051241B HK 03103312 A HK03103312 A HK 03103312A HK 1051241 B HK1051241 B HK 1051241B
Authority
HK
Hong Kong
Prior art keywords
memory
controller
references
memory reference
chaining bit
Prior art date
Application number
HK03103312.2A
Other languages
German (de)
English (en)
French (fr)
Other versions
HK1051241A1 (zh
Inventor
Gilbert Wolrich
Debra Bernstein
Matthew J. Adiletta
William Wheeler
Original Assignee
Intel Corporation
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US09/473,112 external-priority patent/US6560667B1/en
Application filed by Intel Corporation filed Critical Intel Corporation
Publication of HK1051241A1 publication Critical patent/HK1051241A1/zh
Publication of HK1051241B publication Critical patent/HK1051241B/zh

Links

HK03103312.2A 1999-12-28 2000-12-06 分布式存儲器控制和帶寬優化 HK1051241B (zh)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US473112 1999-12-28
US09/473,112 US6560667B1 (en) 1999-12-28 1999-12-28 Handling contiguous memory references in a multi-queue system
PCT/US2000/042663 WO2001048619A2 (en) 1999-12-28 2000-12-06 Distributed memory control and bandwidth optimization

Publications (2)

Publication Number Publication Date
HK1051241A1 HK1051241A1 (zh) 2003-07-25
HK1051241B true HK1051241B (zh) 2010-07-02

Family

ID=

Similar Documents

Publication Publication Date Title
EP1282862B1 (en) Distributed memory control and bandwidth optimization
EP1236088B1 (en) Register set used in multithreaded parallel processor architecture
US7546444B1 (en) Register set used in multithreaded parallel processor architecture
EP1214660B1 (en) Sram controller for parallel processor architecture including address and command queue and arbiter
EP1214661B1 (en) Sdram controller for parallel processor architecture
US6629237B2 (en) Solving parallel problems employing hardware multi-threading in a parallel processing environment
EP1221105B1 (en) Parallel processor architecture
EP1221086B1 (en) Execution of multiple threads in a parallel processor
US7743235B2 (en) Processor having a dedicated hash unit integrated within
US20020053017A1 (en) Register instructions for a multithreaded processor
WO2001016697A9 (en) Local register instruction for micro engine used in multithreadedparallel processor architecture
US7191309B1 (en) Double shift instruction for micro engine used in multithreaded parallel processor architecture
HK1051241B (zh) 分布式存儲器控制和帶寬優化