GB2128856A - Automatically adjustable equalizing network - Google Patents

Abstract

An automatically adjustable equalizing network comprises a number of regulating networks (I,...IV) connected in cascade. The regulating networks are controlled by the same control voltage which is derived from a peak detector (6). Each regulating network (I,...IV) is connected to a different reference voltage derived from a potential divider (11-17) arranged between supply terminals (9,18). The arrangement is such that each regulating network (I,...IV) becomes operative only after the preceding network has reached its extreme regulating position. <IMAGE>

Description

SPECIFICATION Automatically adjustable equalizing network The invention relates to an automatically adjustable equalizing network comprising a number of regulating networks connected in cascade, the regulating networks being controlled by the same control voltage which is derived from a peak detector.

Automatic equalizing networks are used, for example, in pulse code modulation transmission systems. In such a transmission system, the transmission characteristic of the transmission path, which in many cases is constituted by a cable, is a function of the distance between two succesive amplifiers and of the ambient temperature. In order to obtain as uniform and as simple as possible construction of amplifier, the equalization required for the pulse regeneration in the equalizing amplifier is realized as a fixed section which equaiizes the transmission characteristic of a transmission path of nominal length at a nominal temperature and an adjustable section for automatically equalizing the variations with respect to this nominal transmission characteristic which are caused by deviations with respect to the nominal length and the nominal temperature which always occur in practice.The adjustment signal for the automatic equalization may be obtained, for example, by means of a regulating circuit which comprises a peak detector which is connected to the output of the equalizing amplifier and whose output signal is utilized to adjust the equalizing amplifier so that the pulse signals at its output have a constant peak value.

Under given conditions, the control range desired can be so large that it can not be achieved with a single equalizing network. For example, for an 8 M bit 120 channel pulse code modulation system on symmetrical cables, an automatic equalizing system is required with a regulating range of 56 dB at 4.224 MHz. i.e. the 1/2 bit frequency. This large control range is required because the usable section lengths are strongly dependent on both geographical conditions and the near cross-talk in symmetrical cables.

For the design accuracy, the phase linearity of the equalization is of particular importance because the non-linearity of the phase with change-over between fixed patterns in data transmission gives rise to jitter in the clock frequency (change-over jitter). In order to keep the phase linear in the whole control range of the equalization, it is necessaryforthe cable damping to be equalized practically up to the bitfrequency. This means that, when a regulating sweep of 56 dB at half the frequency is desired, a regulating sweep of 79 dB-is required at the whole bit frequency. It is impossible to realize this very large control range with a single equalizing network. In such a case, several equalizing networks are conr nected in series, the amplification of these networks being adjusted simultaneously with the aid of a regulating circuit.

The fact that several networks are adjusted simultaneously has the disadvantage that in the higher part of the frequency band in which the equalization takes place the regulating errors of the various networks will be added to each other, which is undesirable.

The invention has for its object to mitigate the aforementioned problem. The invention provides an equalizing network as set forth in the opening pharagraph characterized in that each regulating network is connected to a different reference voltage so that each regulating network becomes operative only after the preceding network has reached its extreme position.

An embodiment of the invention will be described by way of example, with reference to the accompanying drawings, in which: Figure 1 shows in block schematic form an equalizing network according to the invention.

Figure 2 is a circuit diagram of a possible embodiment of the equalizing network of Figure 1.

Figure 3 shows a diagram for explanation of the operation of the equalizing network according to the invention.

The equalizing network shown in Figure 1 comprises the series arrangment of four regulating networks I to I V inclusive. The input signal to be equalized is supplied to an input 1 of the equalizing network which is connected to the input of the network I. The output signal of the network iV is supplied through a filter 7 to the output 8 of the equalizing network. The output of the filter 7 is connected through a peak detector 6 to control inputs 2, 3, 4 and 5 of the respective regulating networks I to IV inclusive. The regulating networks l, Ill lil and IV each have a reference voltage input 16, 14, 12 and 10, respectively, which are each connected to a different point on a voltage divider constituted by resistors 17, 15, 13 and 11.The voltage divider is arranged between points 18 and 9, to which the supply voltage for the equalizing network is applied. Delay voltage U1, U2 and U3 are produced across the resistors 15, 13 and 11, respectively. These delay voltages co-operate with the control signals applied to the inputs 2,3,4 and 5 in a manner such that a next regulating network becomes operative only after the preceding regulating network has reached its extreme regulating position.

As will appear hereinafter, this means that this preceding regulating network is in its faultless design position. This can be a maximum position or a minimum position, dependent upon the equalization desired. This means that in the equalizing netwo according to the invention only the regulating error of the next regulating network is of importance. All the remaining regulating networks are in the faultless design position during the regulation of the next regulating network and consequently do not contribute to the overall regulating error of the equalizing network. Since the regulating networks themselves also have D.C. amplification for the control voltage, the difference between two successive control voltages need not be more than 0.2 V. This value is not critical.To ensure that the regulating networks become operative in order of succession, the said difference is chosen to be comparatively large, for example, 0.3 Volt or more.

The high amplification in the control loop guarantees that, when the extreme position of one of the regulating networks is reached, the next regulating network nevertheless becomes operative automatically without interruptions.

In the embodiment of the equalizing network of Figure 2, the regulating network I comprises six transistors 20 to 25 inclusive, an amplifier 29, three resistors 26, 27 and 28 and five impedances 40,41, 42,43 and 44. The various reference voltages are produced by'a voltage divider comprising the series arrangement of three resistors 13, 15 and 17, which voltage divider is arranged between the points 12 and 18 of the equalizing network. The input signal Vi to be processed is supplied to the input terminal 1 of an impedance network comprising the impedances 40 to 49 inclusive. This impedance network is coupled to the two regulating networks I and 11.The output of the impedance network is applied to a filter having a prescribed transmission characteristic, for example, a Nyquistfilter, the output signal being derived from this output 8, while further a control signal is produced by means of a peak detector 6 for controlling the amplification of the two regulating networks I and lIThe regulating network I comprises an amplifier 29 having an amplification 1, whose output is connected to the junction of the impedances 44 and 45 and whose input is connected to the junction of the collectors of the two transistors 20 and 22. The junction of the two transistors 20 and 22 junction is further connected through a resistor 26 to the point 12.The emitters of the transistors 20 and 21 are connected together and, through the series arrangement of the collector-emitter path of the transistor 24 and the resistor 27, to the point 18. The base of the transistor 24 is connected to the junction of the impedances 40 and 41. The emitters of the two transistors 22 and 23 are connected together and, through the series arrangement of the collectoremitter path of the transistor 25 and the resistor 28, to the point 18. The base of the transistor 25 isconnected to the junction of the impedances 43 and 44. The junction of the impedances 41 and 43 is connected through the impedance 42 to the point 18.

The bases of the two transistors 21 and 22 are connected together and to the junction 16 ofthetwo resistors 15 and 17 of the voltage divider, which junction constitutes the reference voltage input of the regulating network I. The bases of the two transistors 20 and 23 are connected to the control input 2 of the regulating network The regulating network II comprises an amplifier 39 having an amplification 1, whose output is connected to the junction cf the impedance 49 and the input of the filter 7 and whose input is connected to the junction of the collectors of two transistors 30 and 32 and one end of a resistor 36 whose other end is connected to the point 12.The emitters of two transistors 30 and 31 are connected together through the series arrangement of the collectoremitter path of a transistor 34 and a resistor 37 to the point 18. The base of the transistor 34 is connected to the junction of the impedances 45 and 46. The emitters of the two transistors 32 and 33 are connected together and through the series arrangement of the collector-emitter path of the transistor 35 and a resistor 38 to the point 18. The base of the transistor 35 is connected to the junction of the impedances 48 and 49. The junction of the impe dances 46 and 48 is connected through the impe dance 47 to the point 18.The bases of the two transistors 31 and 32 are connected together and to the junction 14 of the two resistors 13 and 15 of the voltage divider, which junction constitutes the refer ence voltage input of the regulating amplifier lIThe bases of the two transistors 30 and 33 are connected to the control input 3 and 2 of the regulating networks land II, respectively, and through the peak detector 6 to the output 8 of the equalizing network.

The collectors of the transistors 31 and 33 are are connected together and to the point 12.

If it is assumed that the control voltage of the peak detector 6 is such that the potential at the bases of the transistors 20 and 23 is negative with respect to the potential at the bases of the transistors 21 and 22, the transistors 20 and 23 are cut off and the transistors 21 and 22 are conducting. The input signal supplied to the input 1 is supplied through the impedances 40, 41,42, and 43 and the transistors 25 and 22 to the input of the amplifier 29. The junction 50 of the impedances 43 and 44 in this case constitutes the signal input proper of the amplifiying part of the regulating network I. The overall amplifi cation is the sum of the amplifications of the transistors 25 and 22 and of the amplifier 29.The impedance 44 in this case is arranged between the output and the input of the amplifying part of the regulating network I. The input signal Vi reaches in attenuated state via the impedances 40,41,42 and 43 the signal input proper 50 of the amplifying part of the regulating network 1, while only the impe dance 44 is present in the feedback path of the amplifying part of the regulating network 1. In the embodiment shown here, a maximum attenuation will occur with respect to a nominai amplification; see Figure 3a.

If it is assumed that the control voltage of the peak detector 6 is such that the potential at the bases of the transistors 20 and 23 is positive with respect to the potential at the bases of the transistors 21 and 22, the transistors 20 and 23 are conducting and the transistors 21 and 22 are cut off. The input signal supplied to the input 1 is supplied through the impedance 40 and transistors 24 and 20 to the input of the amplifier 29. The junction 51 of the impe dances 40 and 41 in this case constitutes the signal input proper of the amplifying part of the regulating network I. The overall amplification is the sum of the amplifications of the transistors 24 and 20 and of the amplifier 29. The impedances 41,42,43 and 44 in this case are arranged between the output and the input of the amplifying.part of the regulating net work I. The input signal Vi reaches substantia!ly without attenuation through the impedance 40 the signal input proper 51 of the amplifying part of the - regulating network I, while now the impedances 41, 42,43 and 44 are present in the feedback path of the amplifying part of the regulating network I. In the embodiment shown here, a maximum amplification will occur with respect to a nominal amplification; see Figure 3b.

In all other regulating positions of the equalizing network, the input of the amplifier 29 is connected to a different point of the series arrangement of the impedances 41 and 43 located between the points 50 and 51. The nominal amplification occurs when all the transistors 20 to 23 inclusive are conducting to the same extent. When the two impedances 41 and 43 are equally large, this means that the input of the amplifier 29 is effectively connected to the junction 52 of the impedances 41 and 43.

For an ideal equalization control, in general the following relation applies: F(w) = F1 (w)+F2(w).F3( < x) (1) In this relation, Fl (w) is a nominal constant frequency-dependent damping, which may be present already in the regulation itself or otherwise may be obtained by arranging separate fixed equalizing networks and/or amplifiers before or after it. In the embodiment shown in Figure 2, F1 (w) is realized, for example, with the Nyquist filter 7. F2(w) represents the required regulating characteristic and is realized by means of the impedances 40 to 49 inclusive. F3(a) is a function which is proportional to the control voltage or current supplied by the peak detector 6.

Figure 3c shows a graph illustrating the regulating characteristic.

The regulating characteristic for a = 1 corresponds to the regulating position shown in Figure 3b; the regulating characteristic for a = 0 corresponds to the regulating position shown in Figure 3a and the regulating characteristic for 1/2 corresponds to the case in which the input of the amplifier 29 is connected to the point 52. In all these three cases, it is ensured that the regulating error is equal to 0 (three-point regulation). For all the other values of a, the regulating error A will occur, as is indicated, for example, in Figure 3c for a= 3/4 and a = 1/4.This is due to the fact that, when the transmission formula is expanded into a series, there is obtained besides the desired term F2(w).F3(a) also a series of odd higher harmonic terms of the form F2(wb3.F3(a)3+....

In an intermediate position, for example a=314, the amplification will decrease at a disproportionately higher rate at higher frequencies due to the higher harmonic terms than at lower frequencies at which the influence of these terms is considerably smaller.

When several of these regulating networks are arranged in cascade without further precautions, the regulating errors of the separate regulating,networks are added to each other, which gives rise to an overall regulating error which is no longer acceptable.

In the embodiment of Figure 2, the reference voltage input of the regulating network II is connected to a higher point 14 of the voltage divider constituted by the resistors 13, 15 and 17 than the point 16 to which the reference voltage input of the regulating network I is connected. The desired difference voltage between the two regulating networks I and II is produced across the resistor 15. This difference is proportioned so that the control space between the points 3 and 14 of the regulating network II and the control space between the points 2 and 16 of the regulating network I have no control range in common. This means that, when one of the regulating amplifiers I or II is controlled, the other regulating amplifier II or I is adjusted to one of the faultless extreme regulating positions for a = O or a = 1; see Figure 3c.Consequently, always only one regulating network is adjusted at a time, as a result of which the overall regulating error is always equal to the regulating error of this single adjusted network.

As is known, the noise factor of an equalizing network is increased by an impedance network at the input by an amount equal to the damping of this impedance network. With long cable sections, i.e.

with a low input level, it is therefore of importance that the regulating network is fixed in its maximum position at the input of the equalizing network; see Figure 3b. In this case, the impedance network is included in the feedback loop of the regulating network. This network is allowed to become opera tiveonlyafterthecable length has becomesuffi- ciently small and the succeeding regulating networks have reached their extreme minimum position (a = 0). This regulation principle is therefore of importance not only for keeping the regulating error small, but also for keeping the influence of the noise small, the latter being also determinative of the order of succession in which the regulating networks arranged in cascade are adjusted.

Claims (3)

1. An automatically adjustable equalizing network comprising a number of regulating networks connected in cascade, the regulating networks being controlled by the same direct voltage which is derived from a peak detector, characterized in that each regulating network is connected to a different reference voltage so that each regulating network becomes operative only after the preceding network has reached its extreme regulating position.

2. An automatically adjustable equalizing network as claimed in Claim 1, in which each regulating network is provided with a reference voltage input characterized in that the reference voltage inputs of the regulating networks are each connected to a different point on a voltage divider which is arranged between two supply points between which a source of supply voltage can be connected.

3. An automatically adjustable equalizing network substantially as described herein with reference to Figure 1, or to Figure 2 or to Figures 1 to 3 of the accompanying drawings.