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FR3034565B1 - Procede de fabrication d'une structure presentant une couche dielectrique enterree d'epaisseur uniforme - Google Patents

Procede de fabrication d'une structure presentant une couche dielectrique enterree d'epaisseur uniforme

Info

Publication number
FR3034565B1
FR3034565B1 FR1552651A FR1552651A FR3034565B1 FR 3034565 B1 FR3034565 B1 FR 3034565B1 FR 1552651 A FR1552651 A FR 1552651A FR 1552651 A FR1552651 A FR 1552651A FR 3034565 B1 FR3034565 B1 FR 3034565B1
Authority
FR
France
Prior art keywords
manufacturing
dielectric layer
uniform thickness
bit dielectric
bit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
FR1552651A
Other languages
English (en)
Other versions
FR3034565A1 (fr
Inventor
Carole David
Anne-Sophie Cocchi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Soitec SA
Original Assignee
Soitec SA
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Soitec SA filed Critical Soitec SA
Priority to FR1552651A priority Critical patent/FR3034565B1/fr
Priority to SG10201602464YA priority patent/SG10201602464YA/en
Priority to JP2016066013A priority patent/JP6725286B2/ja
Priority to US15/083,725 priority patent/US9929040B2/en
Priority to CN201610193183.2A priority patent/CN106024621B/zh
Priority to KR1020160038661A priority patent/KR102413439B1/ko
Publication of FR3034565A1 publication Critical patent/FR3034565A1/fr
Application granted granted Critical
Publication of FR3034565B1 publication Critical patent/FR3034565B1/fr
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • H10P90/1914—
    • H10P95/00—
    • H10P90/1906—
    • H10P90/1908—
    • H10P90/1916—
    • H10P95/062—
    • H10P95/906—
    • H10W10/012—
    • H10W10/019—
    • H10W10/061—
    • H10W10/10—
    • H10W10/13—
    • H10W10/181—
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/60—Electrodes characterised by their materials
    • H10D64/66—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes
    • H10D64/68—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes characterised by the insulator, e.g. by the gate insulator
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/60—Electrodes characterised by their materials
    • H10D64/66—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes
    • H10D64/68—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes characterised by the insulator, e.g. by the gate insulator
    • H10D64/681—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes characterised by the insulator, e.g. by the gate insulator having a compositional variation, e.g. multilayered
    • H10W72/012—
    • H10W72/01257—
FR1552651A 2015-03-30 2015-03-30 Procede de fabrication d'une structure presentant une couche dielectrique enterree d'epaisseur uniforme Active FR3034565B1 (fr)

Priority Applications (6)

Application Number Priority Date Filing Date Title
FR1552651A FR3034565B1 (fr) 2015-03-30 2015-03-30 Procede de fabrication d'une structure presentant une couche dielectrique enterree d'epaisseur uniforme
SG10201602464YA SG10201602464YA (en) 2015-03-30 2016-03-29 Process For Fabricating A Structure Having A Buried Dielectric Layer Of Uniform Thickness
JP2016066013A JP6725286B2 (ja) 2015-03-30 2016-03-29 厚さが均一な埋め込み誘電体層を有する構造を作成するためのプロセス
US15/083,725 US9929040B2 (en) 2015-03-30 2016-03-29 Process for fabricating a structure having a buried dielectric layer of uniform thickness
CN201610193183.2A CN106024621B (zh) 2015-03-30 2016-03-30 用于制造具有均匀厚度的掩埋介电层的结构的工艺
KR1020160038661A KR102413439B1 (ko) 2015-03-30 2016-03-30 균일한 두께의 매립 절연층을 가지는 구조를 제작하기 위한 방법

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
FR1552651A FR3034565B1 (fr) 2015-03-30 2015-03-30 Procede de fabrication d'une structure presentant une couche dielectrique enterree d'epaisseur uniforme

Publications (2)

Publication Number Publication Date
FR3034565A1 FR3034565A1 (fr) 2016-10-07
FR3034565B1 true FR3034565B1 (fr) 2017-03-31

Family

ID=53200171

Family Applications (1)

Application Number Title Priority Date Filing Date
FR1552651A Active FR3034565B1 (fr) 2015-03-30 2015-03-30 Procede de fabrication d'une structure presentant une couche dielectrique enterree d'epaisseur uniforme

Country Status (6)

Country Link
US (1) US9929040B2 (fr)
JP (1) JP6725286B2 (fr)
KR (1) KR102413439B1 (fr)
CN (1) CN106024621B (fr)
FR (1) FR3034565B1 (fr)
SG (1) SG10201602464YA (fr)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109742023A (zh) * 2018-11-27 2019-05-10 上海新傲科技股份有限公司 晶圆表面的平坦化方法

Family Cites Families (21)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3293736B2 (ja) * 1996-02-28 2002-06-17 キヤノン株式会社 半導体基板の作製方法および貼り合わせ基体
JP3036619B2 (ja) * 1994-03-23 2000-04-24 コマツ電子金属株式会社 Ｓｏｉ基板の製造方法およびｓｏｉ基板
JPH08274285A (ja) * 1995-03-29 1996-10-18 Komatsu Electron Metals Co Ltd Ｓｏｉ基板及びその製造方法
JPH11307472A (ja) * 1998-04-23 1999-11-05 Shin Etsu Handotai Co Ltd 水素イオン剥離法によってｓｏｉウエーハを製造する方法およびこの方法で製造されたｓｏｉウエーハ
EP1408551B1 (fr) 2001-07-17 2014-07-02 Shin-Etsu Handotai Co., Ltd. Procede de production de plaquettes de liaison
FR2843487B1 (fr) 2002-08-12 2005-10-14 Procede d'elaboration de couche mince comprenant une etape de correction d'epaisseur par oxydation sacrificielle, et machine associee
US6927169B2 (en) * 2002-12-19 2005-08-09 Applied Materials Inc. Method and apparatus to improve thickness uniformity of surfaces for integrated device manufacturing
US6916744B2 (en) * 2002-12-19 2005-07-12 Applied Materials, Inc. Method and apparatus for planarization of a material by growing a sacrificial film with customized thickness profile
JP4407127B2 (ja) * 2003-01-10 2010-02-03 信越半導体株式会社 Ｓｏｉウエーハの製造方法
EP1667207B1 (fr) 2003-09-08 2019-07-17 SUMCO Corporation Tranche collee et procede de fabrication
DE102004062356A1 (de) * 2004-12-23 2006-07-13 Siltronic Ag Halbleiterscheibe mit einer Halbleiterschicht und einer darunter liegenden elektrisch isolierenden Schicht sowie Verfahren zu deren Herstellung
JP2007149723A (ja) * 2005-11-24 2007-06-14 Sumco Corp 貼り合わせウェーハの製造方法
US7598153B2 (en) * 2006-03-31 2009-10-06 Silicon Genesis Corporation Method and structure for fabricating bonded substrate structures using thermal processing to remove oxygen species
JP2011504655A (ja) * 2007-11-23 2011-02-10 エス． オー． アイ． テック シリコン オン インシュレーター テクノロジーズ 精密な酸化物の溶解
DE102008016429A1 (de) 2008-03-31 2009-10-01 Advanced Micro Devices, Inc., Sunnyvale Verfahren zur Herstellung dünner Schichten durch einen thermisch aktivierten Prozess unter Anwendung eines Temperaturgradienten über das Substrat hinweg
JP5493345B2 (ja) 2008-12-11 2014-05-14 信越半導体株式会社 Ｓｏｉウェーハの製造方法
JP2010153488A (ja) 2008-12-24 2010-07-08 Rohm Co Ltd Ｓｏｉウエハの製造方法およびｓｏｉウエハ
FR2941324B1 (fr) * 2009-01-22 2011-04-29 Soitec Silicon On Insulator Procede de dissolution de la couche d'oxyde dans la couronne d'une structure de type semi-conducteur sur isolant.
JP5927894B2 (ja) 2011-12-15 2016-06-01 信越半導体株式会社 Ｓｏｉウェーハの製造方法
FR2998418B1 (fr) * 2012-11-20 2014-11-21 Soitec Silicon On Insulator Procede de fabrication d'un substrat de type semi-conducteur sur isolant
JP6107709B2 (ja) * 2014-03-10 2017-04-05 信越半導体株式会社 貼り合わせｓｏｉウェーハの製造方法

Also Published As

Publication number Publication date
US9929040B2 (en) 2018-03-27
SG10201602464YA (en) 2016-10-28
CN106024621A (zh) 2016-10-12
KR20160117346A (ko) 2016-10-10
KR102413439B1 (ko) 2022-06-27
JP6725286B2 (ja) 2020-07-15
JP2016192548A (ja) 2016-11-10
FR3034565A1 (fr) 2016-10-07
CN106024621B (zh) 2021-05-14
US20160293476A1 (en) 2016-10-06

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