DE69932665D1 - Verfahren zur Herstellung einer Verbindungsstruktur - Google Patents

Verfahren zur Herstellung einer Verbindungsstruktur

Info

Publication number: DE69932665D1
Authority: DE; Germany
Prior art keywords: producing; connection structure; connection
Prior art date: 1998-03-26
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.): Expired - Lifetime

Application number

DE69932665T

Other languages

English (en)

Other versions

DE69932665T2 (de

Inventor

Nobuo Aoi

Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)

Panasonic Corp

Original Assignee

Matsushita Electric Industrial Co Ltd

Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)

1998-03-26

Filing date

1999-03-24

Publication date

2006-09-21

Family has litigation

First worldwide family litigation filed litigation Critical https://patents.darts-ip.com/?family=13688026&utm_source=google_patent&utm_medium=platform_link&utm_campaign=public_patent_search&patent=DE69932665(D1) "Global patent litigation dataset” by Darts-ip is licensed under a Creative Commons Attribution 4.0 International License.

1999-03-24 Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd

2006-09-21 Publication of DE69932665D1 publication Critical patent/DE69932665D1/de

2006-12-14 Application granted granted Critical

2006-12-14 Publication of DE69932665T2 publication Critical patent/DE69932665T2/de

2019-03-25 Anticipated expiration legal-status Critical

Status Expired - Lifetime legal-status Critical Current

Classifications

- H10W20/071—
- H10W20/0698—
- H10W20/074—
- H10W20/076—
- H10W20/081—
- H10W20/087—
- H10W20/088—
- H10W20/096—

DE69932665T 1998-03-26 1999-03-24 Verfahren zur Herstellung einer Verbindungsstruktur Expired - Lifetime DE69932665T2 (de)

Applications Claiming Priority (2)

Application Number	Priority Date	Filing Date	Title
JP7937198		1998-03-26
JP7937198		1998-03-26

Publications (2)

Publication Number	Publication Date
DE69932665D1 true DE69932665D1 (de)	2006-09-21
DE69932665T2 DE69932665T2 (de)	2006-12-14

Family

ID=13688026

Family Applications (1)

Application Number	Title	Priority Date	Filing Date
DE69932665T Expired - Lifetime DE69932665T2 (de)	1998-03-26	1999-03-24	Verfahren zur Herstellung einer Verbindungsstruktur

Country Status (3)

Country	Link
US (2)	US6197696B1 (de)
EP (1)	EP0945900B1 (de)
DE (1)	DE69932665T2 (de)

Families Citing this family (33)

* Cited by examiner, † Cited by third party
Publication number	Priority date	Publication date	Assignee	Title
US6197696B1 (en) *	1998-03-26	2001-03-06	Matsushita Electric Industrial Co., Ltd.	Method for forming interconnection structure
TW437040B (en) *	1998-08-12	2001-05-28	Applied Materials Inc	Interconnect line formed by dual damascene using dielectric layers having dissimilar etching characteristics
US6071809A (en) *	1998-09-25	2000-06-06	Rockwell Semiconductor Systems, Inc.	Methods for forming high-performing dual-damascene interconnect structures
JP3888794B2 (ja)	1999-01-27	2007-03-07	松下電器産業株式会社	多孔質膜の形成方法、配線構造体及びその形成方法
TW444252B (en) *	1999-03-19	2001-07-01	Toshiba Corp	Semiconductor apparatus and its fabricating method
US6461955B1 (en) *	1999-04-29	2002-10-08	Texas Instruments Incorporated	Yield improvement of dual damascene fabrication through oxide filling
US6329280B1 (en) *	1999-05-13	2001-12-11	International Business Machines Corporation	Interim oxidation of silsesquioxane dielectric for dual damascene process
JP4094174B2 (ja)	1999-06-04	2008-06-04	株式会社ルネサステクノロジ	半導体装置の製造方法
US6251770B1 (en)	1999-06-30	2001-06-26	Lam Research Corp.	Dual-damascene dielectric structures and methods for making the same
KR20020025237A (ko)	1999-08-25	2002-04-03	마이클 골위저, 호레스트 쉐퍼	적어도 하나의 금속화 평면을 구비한 집적회로의 생산 방법
JP3348706B2 (ja) *	1999-09-29	2002-11-20	日本電気株式会社	半導体装置の製造方法
JP2001102447A (ja) *	1999-09-30	2001-04-13	Mitsubishi Electric Corp	コンタクト構造の製造方法
US6329281B1 (en) *	1999-12-03	2001-12-11	Agere Systems Guardian Corp.	Methods for fabricating a multilevel interconnection for an integrated circuit device utilizing a selective overlayer
KR100575227B1 (ko) *	2000-04-28	2006-05-02	동경 엘렉트론 주식회사	반도체 장치 및 그 제조 방법
WO2001099184A2 (en) *	2000-06-21	2001-12-27	Infineon Technologies North America Corp.	Dual damascene process utilizing a low-k dual dielectric
US7122900B2 (en) *	2000-06-26	2006-10-17	Renesas Technology Corp.	Semiconductor device and method manufacturing the same
US6472332B1 (en) *	2000-11-28	2002-10-29	Xerox Corporation	Surface micromachined structure fabrication methods for a fluid ejection device
US6677680B2 (en) *	2001-02-28	2004-01-13	International Business Machines Corporation	Hybrid low-k interconnect structure comprised of 2 spin-on dielectric materials
TW544855B (en) *	2001-06-25	2003-08-01	Nec Electronics Corp	Dual damascene circuit with upper wiring and interconnect line positioned in regions formed as two layers including organic polymer layer and low-permittivity layer
US6992391B2 (en) *	2001-09-28	2006-01-31	Intel Corporation	Dual-damascene interconnects without an etch stop layer by alternating ILDs
JP2004186439A (ja) *	2002-12-03	2004-07-02	Sanken Electric Co Ltd	半導体装置およびその製造方法
US6884338B2 (en) *	2002-12-16	2005-04-26	3M Innovative Properties Company	Methods for polishing and/or cleaning copper interconnects and/or film and compositions therefor
US7147767B2 (en) *	2002-12-16	2006-12-12	3M Innovative Properties Company	Plating solutions for electrochemical or chemical deposition of copper interconnects and methods therefor
US6858124B2 (en) *	2002-12-16	2005-02-22	3M Innovative Properties Company	Methods for polishing and/or cleaning copper interconnects and/or film and compositions therefor
JP3715626B2 (ja) *	2003-01-17	2005-11-09	株式会社東芝	半導体装置の製造方法および半導体装置
US20050082089A1 (en) *	2003-10-18	2005-04-21	Stephan Grunow	Stacked interconnect structure between copper lines of a semiconductor circuit
JP2006130868A (ja) *	2004-11-09	2006-05-25	Canon Inc	インクジェット記録ヘッド及びその製造方法
KR100641553B1 (ko) *	2004-12-23	2006-11-01	동부일렉트로닉스 주식회사	반도체 소자에서 패턴 형성 방법
US7531448B2 (en) *	2005-06-22	2009-05-12	United Microelectronics Corp.	Manufacturing method of dual damascene structure
DE102006048740A1 (de) *	2006-10-12	2008-04-17	Henkel Kgaa	Tönungsschaum
KR102068677B1 (ko)	2013-04-10	2020-01-22	삼성전자 주식회사	반도체 소자 제조 방법
US20140342553A1 (en) *	2013-05-14	2014-11-20	United Microelectronics Corp.	Method for Forming Semiconductor Structure Having Opening
CN105789111B (zh) *	2014-12-18	2019-03-12	中芯国际集成电路制造(上海)有限公司	半导体结构的形成方法

Family Cites Families (15)

* Cited by examiner, † Cited by third party
Publication number	Priority date	Publication date	Assignee	Title
US5110712A (en)	1987-06-12	1992-05-05	Hewlett-Packard Company	Incorporation of dielectric layers in a semiconductor
EP0425787A3 (en)	1989-10-31	1993-04-14	International Business Machines Corporation	Method for fabricating high circuit density, self-aligned metal lines to contact windows
US5651855A (en)	1992-07-28	1997-07-29	Micron Technology, Inc.	Method of making self aligned contacts to silicon substrates during the manufacture of integrated circuits
JPH06291193A (ja)	1993-04-02	1994-10-18	Mitsubishi Electric Corp	半導体装置およびその製造方法
JP2773613B2 (ja)	1993-11-30	1998-07-09	日本電気株式会社	半導体装置の製造方法
JPH08139194A (ja)	1994-04-28	1996-05-31	Texas Instr Inc <Ti>	半導体デバイス上に電気接続を作製する方法および該方法により作製された電気接続を有する半導体デバイス
KR970007174B1 (ko) *	1994-07-07	1997-05-03	현대전자산업 주식회사	반도체 소자의 금속배선 형성방법
US5635423A (en) *	1994-10-11	1997-06-03	Advanced Micro Devices, Inc.	Simplified dual damascene process for multi-level metallization and interconnection structure
JPH0964034A (ja)	1995-08-18	1997-03-07	Toshiba Corp	半導体装置およびその製造方法
JPH09153545A (ja)	1995-09-29	1997-06-10	Toshiba Corp	半導体装置及びその製造方法
US5702982A (en) *	1996-03-28	1997-12-30	Taiwan Semiconductor Manufacturing Company, Ltd.	Method for making metal contacts and interconnections concurrently on semiconductor integrated circuits
US6107191A (en) *	1997-11-07	2000-08-22	Lucent Technologies Inc.	Method of creating an interconnect in a substrate and semiconductor device employing the same
TW368741B (en) *	1998-02-26	1999-09-01	United Microelectronics Corp	Manufacturing method for dual damascene
US6197696B1 (en) *	1998-03-26	2001-03-06	Matsushita Electric Industrial Co., Ltd.	Method for forming interconnection structure
US6083822A (en) *	1999-08-12	2000-07-04	Industrial Technology Research Institute	Fabrication process for copper structures

1999
- 1999-03-23 US US09/274,114 patent/US6197696B1/en not_active Expired - Lifetime
- 1999-03-24 EP EP99105946A patent/EP0945900B1/de not_active Expired - Lifetime
- 1999-03-24 DE DE69932665T patent/DE69932665T2/de not_active Expired - Lifetime
2001
- 2001-01-09 US US09/756,242 patent/US6287973B2/en not_active Expired - Lifetime

Also Published As

Publication number	Publication date
US20010001739A1 (en)	2001-05-24
EP0945900A1 (de)	1999-09-29
EP0945900B1 (de)	2006-08-09
DE69932665T2 (de)	2006-12-14
US6287973B2 (en)	2001-09-11
US6197696B1 (en)	2001-03-06

Publication	Publication Date	Title
DE69932665D1 (de)	2006-09-21	Verfahren zur Herstellung einer Verbindungsstruktur
DE69906491D1 (de)	2003-05-08	VERFAHREN ZUR HERSTELLUNG EINER SiCOI-STRUKTUR
ATE259315T1 (de)	2004-02-15	Verfahren zur herstellung einer stossanfängeranordnung
DE69730940D1 (de)	2004-11-04	Verfahren zur herstellung einer halbleiteranordnung
DE69826934D1 (de)	2004-11-18	Verfahren zur Herstellung einer Doppel-Damaszener Struktur
DE69823027D1 (de)	2004-05-13	Verfahren zur herstellung einer waschmittelzusammensetzung
DE69935810D1 (de)	2007-05-24	Verfahren zur herstellung einer laminierten struktur
DE60030949D1 (de)	2006-11-09	Verfahren zur herstellung einer karte
DE69619691D1 (de)	2002-04-11	Verfahren zur herstellung einer beugungsstruktur
ATA186898A (de)	1999-11-15	Verfahren zur herstellung einer cellulosecarbamatlösung
DE69801560D1 (de)	2001-10-11	Verfahren zur herstellung einer katalysatorzusammenstellung
DE69840399D1 (de)	2009-02-12	Verfahren zur Herstellung einer Gate-Elektrode
DE60031761D1 (de)	2006-12-21	Verfahren zur herstellung einer harzzusammensetzung
DE69940737D1 (de)	2009-05-28	Verfahren zur herstellung einer halbleiteranordnung
DE59914827D1 (de)	2008-09-18	Verfahren zur herstellung einer bond-draht-verbindung
DE69701890D1 (de)	2000-06-08	Verfahren zur herstellung einer abbindenden zusammensetzung
DE69607546D1 (de)	2000-05-11	Verfahren zur Herstellung einer Schaltungsanordnung
ATE205201T1 (de)	2001-09-15	Verfahren zur herstellung einer benzimidazolverbindung
DE69701731D1 (de)	2000-05-25	Verfahren zur herstellung einer waschmittelzusammensetzung
DE69934680D1 (de)	2007-02-15	Verfahren zur herstellung einer schicht
DE69827966D1 (de)	2005-01-05	Verfahren zur herstellung einer querfaserbahn
DE69840320D1 (de)	2009-01-22	Verfahren zur Herstellung einer Gateelektrode
DE60032660D1 (de)	2007-02-15	Verfahren zur Herstellung einer planaren Heterostruktur
DE59800621D1 (de)	2001-05-17	Verfahren zur Herstellung einer mikromechanischen Halbleiteranordnung
DE69942186D1 (de)	2010-05-12	Verfahren zur herstellung einer halbleiteranordnung

Legal Events

Date	Code	Title	Description
2007-08-30	8364	No opposition during term of opposition
2009-05-07	8327	Change in the person/name/address of the patent owner	Owner name: PANASONIC CORP., KADOMA, OSAKA, JP