[go: up one dir, main page]

DE60333484D1 - Umkonfiguration der programmierbaren logik einer integrierten schaltung - Google Patents

Umkonfiguration der programmierbaren logik einer integrierten schaltung

Info

Publication number
DE60333484D1
DE60333484D1 DE60333484T DE60333484T DE60333484D1 DE 60333484 D1 DE60333484 D1 DE 60333484D1 DE 60333484 T DE60333484 T DE 60333484T DE 60333484 T DE60333484 T DE 60333484T DE 60333484 D1 DE60333484 D1 DE 60333484D1
Authority
DE
Germany
Prior art keywords
configuration
integrated circuit
programmable logic
programmable
logic
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE60333484T
Other languages
English (en)
Inventor
Derek R Curd
Punit S Kalra
Richard J Leblanc
Vincent P Eck
Stephen W Trynosky
Jeffrey V Lindholm
Trevor J Bauer
Brandon J Blodget
Scott P Mcmillan
Philip B James-Roxby
Prasanna Sundararajan
Eric R Keller
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Xilinx Inc
Original Assignee
Xilinx Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US10/377,857 external-priority patent/US6920627B2/en
Application filed by Xilinx Inc filed Critical Xilinx Inc
Application granted granted Critical
Publication of DE60333484D1 publication Critical patent/DE60333484D1/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00Digital computers in general; Data processing equipment in general
    • G06F15/76Architectures of general purpose stored program computers
    • G06F15/78Architectures of general purpose stored program computers comprising a single central processing unit
    • G06F15/7867Architectures of general purpose stored program computers comprising a single central processing unit with reconfigurable architecture

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Logic Circuits (AREA)
DE60333484T 2002-12-13 2003-12-12 Umkonfiguration der programmierbaren logik einer integrierten schaltung Expired - Lifetime DE60333484D1 (de)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US10/319,051 US6907595B2 (en) 2002-12-13 2002-12-13 Partial reconfiguration of a programmable logic device using an on-chip processor
US10/377,857 US6920627B2 (en) 2002-12-13 2003-02-28 Reconfiguration of a programmable logic device using internal control
PCT/US2003/039610 WO2004055986A2 (en) 2002-12-13 2003-12-12 Reconfiguration of the programmable logic of an integrated circuit

Publications (1)

Publication Number Publication Date
DE60333484D1 true DE60333484D1 (de) 2010-09-02

Family

ID=32506545

Family Applications (1)

Application Number Title Priority Date Filing Date
DE60333484T Expired - Lifetime DE60333484D1 (de) 2002-12-13 2003-12-12 Umkonfiguration der programmierbaren logik einer integrierten schaltung

Country Status (2)

Country Link
US (1) US6907595B2 (de)
DE (1) DE60333484D1 (de)

Families Citing this family (104)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7356620B2 (en) * 2003-06-10 2008-04-08 Altera Corporation Apparatus and methods for communicating with programmable logic devices
TWI220738B (en) * 2002-12-20 2004-09-01 Benq Corp Method for effectively re-downloading data to a field programmable gate array
US7984434B1 (en) * 2003-05-21 2011-07-19 Altera Corporation Nondestructive patching mechanism
US6842034B1 (en) * 2003-07-01 2005-01-11 Altera Corporation Selectable dynamic reconfiguration of programmable embedded IP
US7080226B1 (en) * 2003-07-02 2006-07-18 Xilinx, Inc. Field programmable gate array (FPGA) configuration data path for module communication
US7167025B1 (en) 2004-02-14 2007-01-23 Herman Schmit Non-sequentially configurable IC
US8581610B2 (en) * 2004-04-21 2013-11-12 Charles A Miller Method of designing an application specific probe card test system
US7126372B2 (en) * 2004-04-30 2006-10-24 Xilinx, Inc. Reconfiguration port for dynamic reconfiguration—sub-frame access for reconfiguration
US7330050B2 (en) 2004-11-08 2008-02-12 Tabula, Inc. Storage elements for a configurable IC and method and apparatus for accessing data stored in the storage elements
US7315918B1 (en) * 2005-01-14 2008-01-01 Xilinx, Inc. Processor block placement relative to memory in a programmable logic device
US7512850B2 (en) 2005-07-15 2009-03-31 Tabula, Inc. Checkpointing user design states in a configurable IC
US7598768B1 (en) * 2005-08-05 2009-10-06 Xilinx, Inc. Method and apparatus for dynamic port provisioning within a programmable logic device
US8407658B2 (en) * 2007-02-01 2013-03-26 International Business Machines Corporation Methods, systems, and computer program products for using direct memory access to initialize a programmable logic device
KR100893527B1 (ko) * 2007-02-02 2009-04-17 삼성전자주식회사 재구성 가능 멀티 프로세서 시스템에서의 매핑 및 스케줄링방법
US7839162B2 (en) 2007-06-27 2010-11-23 Tabula, Inc. Configurable IC with deskewing circuits
US8344755B2 (en) 2007-09-06 2013-01-01 Tabula, Inc. Configuration context switcher
WO2009039462A1 (en) * 2007-09-19 2009-03-26 Tabula, Inc. Method and system for reporting on a primary circuit structure of an integrated circuit (ic) using a secondary circuit structure of the ic
JP2009129046A (ja) * 2007-11-21 2009-06-11 Panasonic Corp リコンフィギュラブル回路,リコンフィギュラブル回路の機能変更方法および通信装置
US8069329B1 (en) * 2008-01-28 2011-11-29 Lattice Semiconductor Corporation Internally triggered reconfiguration of programmable logic devices
WO2010016857A1 (en) 2008-08-04 2010-02-11 Tabula, Inc. Trigger circuits and event counters for an ic
US9448964B2 (en) 2009-05-04 2016-09-20 Cypress Semiconductor Corporation Autonomous control in a programmable system
US8487655B1 (en) 2009-05-05 2013-07-16 Cypress Semiconductor Corporation Combined analog architecture and functionality in a mixed-signal array
US8179161B1 (en) 2009-05-05 2012-05-15 Cypress Semiconductor Corporation Programmable input/output circuit
US9612987B2 (en) 2009-05-09 2017-04-04 Cypress Semiconductor Corporation Dynamically reconfigurable analog routing circuits and methods for system on a chip
WO2011123151A1 (en) 2010-04-02 2011-10-06 Tabula Inc. System and method for reducing reconfiguration power usage
US8650514B2 (en) 2010-06-23 2014-02-11 Tabula, Inc. Rescaling
US8788987B2 (en) 2010-06-23 2014-07-22 Tabula, Inc. Rescaling
US8760193B2 (en) 2011-07-01 2014-06-24 Tabula, Inc. Configurable storage elements
US9148151B2 (en) 2011-07-13 2015-09-29 Altera Corporation Configurable storage elements
US9203397B1 (en) 2011-12-16 2015-12-01 Altera Corporation Delaying start of user design execution
US8713409B1 (en) 2012-06-18 2014-04-29 Xilinx, Inc. Bit error mitigation
US8786310B1 (en) * 2012-08-17 2014-07-22 Xilinx, Inc. Partially programming an integrated circuit using control memory cells
US8633730B1 (en) 2012-08-17 2014-01-21 Xilinx, Inc. Power control using global control signal to selected circuitry in a programmable integrated circuit
CN103699333A (zh) * 2012-09-27 2014-04-02 中国航天科工集团第二研究院二O七所 一种海量数据存储控制模块
US9000801B1 (en) 2013-02-27 2015-04-07 Tabula, Inc. Implementation of related clocks
US9811618B1 (en) * 2013-03-07 2017-11-07 Xilinx, Inc. Simulation of system designs
DE102013208629A1 (de) * 2013-05-10 2014-11-13 Dr. Johannes Heidenhain Gmbh Positionsmesseinrichtung
EP2963541B1 (de) 2014-06-30 2017-01-25 dSPACE digital signal processing and control engineering GmbH Implementierung einer Konstanten in FPGA-Code
DE102015110729A1 (de) 2014-07-21 2016-01-21 Dspace Digital Signal Processing And Control Engineering Gmbh Anordnung zur teilweisen Freigabe einer Debuggingschnittstelle
US9576095B1 (en) 2014-07-30 2017-02-21 Altera Corporation Partial reconfiguration compatibility detection in an integrated circuit device
JP2016035692A (ja) * 2014-08-04 2016-03-17 キヤノン株式会社 画像処理装置、システム、情報処理方法及びプログラム
US10013363B2 (en) 2015-02-09 2018-07-03 Honeywell International Inc. Encryption using entropy-based key derivation
US9740809B2 (en) * 2015-08-27 2017-08-22 Altera Corporation Efficient integrated circuits configuration data management
DE102015121128B4 (de) * 2015-11-03 2018-01-04 Dspace Digital Signal Processing And Control Engineering Gmbh Verfahren und Vorrichtung zum beschleunigten Zugriff auf Signale eines programmierbaren Logikbausteins
US11099894B2 (en) 2016-09-28 2021-08-24 Amazon Technologies, Inc. Intermediate host integrated circuit between virtual machine instance and customer programmable logic
US10338135B2 (en) 2016-09-28 2019-07-02 Amazon Technologies, Inc. Extracting debug information from FPGAs in multi-tenant environments
US10162921B2 (en) 2016-09-29 2018-12-25 Amazon Technologies, Inc. Logic repository service
US10282330B2 (en) 2016-09-29 2019-05-07 Amazon Technologies, Inc. Configurable logic platform with multiple reconfigurable regions
US10250572B2 (en) 2016-09-29 2019-04-02 Amazon Technologies, Inc. Logic repository service using encrypted configuration data
US10642492B2 (en) 2016-09-30 2020-05-05 Amazon Technologies, Inc. Controlling access to previously-stored logic in a reconfigurable logic device
US10824786B1 (en) 2016-10-05 2020-11-03 Xilinx, Inc. Extend routing range for partial reconfiguration
US10708073B2 (en) 2016-11-08 2020-07-07 Honeywell International Inc. Configuration based cryptographic key generation
US11115293B2 (en) * 2016-11-17 2021-09-07 Amazon Technologies, Inc. Networked programmable logic service provider
US10303648B1 (en) 2017-05-19 2019-05-28 Xilinx, Inc. Logical and physical optimizations for partial reconfiguration design flow
CN110506393B (zh) 2017-05-26 2023-06-20 弗莱克斯-罗技克斯技术公司 具有逻辑瓦片的虚拟阵列的fpga及其配置和操作的方法
EP3639370A4 (de) 2017-06-13 2020-07-29 Flex Logix Technologies, Inc. Taktverteilungs- und -erzeugungsarchitektur für logische kacheln einer integrierten schaltung und verfahren zum betrieb davon
US10348308B2 (en) 2017-07-01 2019-07-09 Flex Logix Technologies, Inc. Clock architecture, including clock mesh fabric, for FPGA, and method of operating same
US10558777B1 (en) 2017-11-22 2020-02-11 Xilinx, Inc. Method of enabling a partial reconfiguration in an integrated circuit device
US10990552B1 (en) 2018-04-03 2021-04-27 Xilinx, Inc. Streaming interconnect architecture for data processing engine array
US10824584B1 (en) 2018-04-03 2020-11-03 Xilinx, Inc. Device with data processing engine array that enables partial reconfiguration
US11016822B1 (en) 2018-04-03 2021-05-25 Xilinx, Inc. Cascade streaming between data processing engines in an array
US10635622B2 (en) 2018-04-03 2020-04-28 Xilinx, Inc. System-on-chip interface architecture
US11113223B1 (en) 2018-04-03 2021-09-07 Xilinx, Inc. Dual mode interconnect
US10866753B2 (en) 2018-04-03 2020-12-15 Xilinx, Inc. Data processing engine arrangement in a device
US11061673B1 (en) 2018-04-03 2021-07-13 Xilinx, Inc. Data selection network for a data processing engine in an integrated circuit
US11379389B1 (en) 2018-04-03 2022-07-05 Xilinx, Inc. Communicating between data processing engines using shared memory
US10747531B1 (en) 2018-04-03 2020-08-18 Xilinx, Inc. Core for a data processing engine in an integrated circuit
US10579559B1 (en) 2018-04-03 2020-03-03 Xilinx, Inc. Stall logic for a data processing engine in an integrated circuit
US10747690B2 (en) 2018-04-03 2020-08-18 Xilinx, Inc. Device with data processing engine array
US11567881B1 (en) 2018-04-03 2023-01-31 Xilinx, Inc. Event-based debug, trace, and profile in device with data processing engine array
US11372803B2 (en) 2018-04-03 2022-06-28 Xilinx, Inc. Data processing engine tile architecture for an integrated circuit
US10686447B1 (en) 2018-04-12 2020-06-16 Flex Logix Technologies, Inc. Modular field programmable gate array, and method of configuring and operating same
US10608641B2 (en) 2018-07-20 2020-03-31 Xilinx, Inc. Hierarchical partial reconfiguration for programmable integrated circuits
US11301295B1 (en) 2019-05-23 2022-04-12 Xilinx, Inc. Implementing an application specified as a data flow graph in an array of data processing engines
US11188312B2 (en) 2019-05-23 2021-11-30 Xilinx, Inc. Hardware-software design flow with high-level synthesis for heterogeneous and programmable devices
US11449347B1 (en) 2019-05-23 2022-09-20 Xilinx, Inc. Time-multiplexed implementation of hardware accelerated functions in a programmable integrated circuit
US10891132B2 (en) 2019-05-23 2021-01-12 Xilinx, Inc. Flow convergence during hardware-software design for heterogeneous and programmable devices
US10891414B2 (en) 2019-05-23 2021-01-12 Xilinx, Inc. Hardware-software design flow for heterogeneous and programmable devices
US10651853B1 (en) 2019-05-23 2020-05-12 Xilinx, Inc. Timing insulation circuitry for partial reconfiguration of programmable integrated circuits
US10990547B2 (en) * 2019-08-11 2021-04-27 Xilinx, Inc. Dynamically reconfigurable networking using a programmable integrated circuit
US10977018B1 (en) 2019-12-05 2021-04-13 Xilinx, Inc. Development environment for heterogeneous devices
US11055106B1 (en) 2019-12-18 2021-07-06 Xilinx, Inc. Bootstrapping a programmable integrated circuit based network interface card
US11443091B1 (en) 2020-07-31 2022-09-13 Xilinx, Inc. Data processing engines with cascade connected cores
US11496418B1 (en) 2020-08-25 2022-11-08 Xilinx, Inc. Packet-based and time-multiplexed network-on-chip
US11288222B1 (en) 2020-09-28 2022-03-29 Xilinx, Inc. Multi-die integrated circuit with data processing engine array
US11922223B1 (en) 2021-02-08 2024-03-05 Xilinx, Inc. Flexible data-driven software control of reconfigurable platforms
US11520717B1 (en) 2021-03-09 2022-12-06 Xilinx, Inc. Memory tiles in data processing engine array
US11336287B1 (en) 2021-03-09 2022-05-17 Xilinx, Inc. Data processing engine array architecture with memory tiles
US11456951B1 (en) 2021-04-08 2022-09-27 Xilinx, Inc. Flow table modification for network accelerators
US11606317B1 (en) 2021-04-14 2023-03-14 Xilinx, Inc. Table based multi-function virtualization
US11886789B1 (en) 2021-07-07 2024-01-30 Xilinx, Inc. Block design containers for circuit design
EP4348433A1 (de) 2021-08-20 2024-04-10 Xilinx, Inc. Mehrfachüberlagerungen zur verwendung mit einem datenverarbeitungsarray
CN113760820B (zh) * 2021-09-15 2022-04-22 北京中科胜芯科技有限公司 一种超大规模fpga芯片的数据配置和回读方法
US11610042B1 (en) 2021-09-28 2023-03-21 Xilinx, Inc. Scalable scribe regions for implementing user circuit designs in an integrated circuit using dynamic function exchange
US12026444B2 (en) 2021-11-09 2024-07-02 Xilinx, Inc. Dynamic port handling for isolated modules and dynamic function exchange
EP4198750B1 (de) * 2021-12-17 2025-09-10 dSPACE GmbH Verfahren zur datenkommunikation zwischen teilbereichen eines fpgas
US12158849B2 (en) 2021-12-17 2024-12-03 Dspace Gmbh Method for data communication between subregions of an FPGA
US11848670B2 (en) 2022-04-15 2023-12-19 Xilinx, Inc. Multiple partitions in a data processing array
US12244518B2 (en) 2022-05-13 2025-03-04 Xilinx, Inc. Network-on-chip architecture for handling different data sizes
US12164451B2 (en) 2022-05-17 2024-12-10 Xilinx, Inc. Data processing array interface having interface tiles with multiple direct memory access circuits
US12079158B2 (en) 2022-07-25 2024-09-03 Xilinx, Inc. Reconfigurable neural engine with extensible instruction set architecture
US12248786B2 (en) 2022-08-08 2025-03-11 Xilinx, Inc. Instruction set architecture for data processing array control
US12176896B2 (en) 2022-12-07 2024-12-24 Xilinx, Inc. Programmable stream switches and functional safety circuits in integrated circuits
US12353717B2 (en) 2022-12-22 2025-07-08 Xilnix, Inc. Localized and relocatable software placement and NoC-based access to memory controllers

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5212652A (en) * 1989-08-15 1993-05-18 Advanced Micro Devices, Inc. Programmable gate array with improved interconnect structure
US6078735A (en) * 1997-09-29 2000-06-20 Xilinx, Inc. System and method for generating memory initialization logic in a target device with memory initialization bits from a programmable logic device
US6096091A (en) 1998-02-24 2000-08-01 Advanced Micro Devices, Inc. Dynamically reconfigurable logic networks interconnected by fall-through FIFOs for flexible pipeline processing in a system-on-a-chip
US6262596B1 (en) * 1999-04-05 2001-07-17 Xilinx, Inc. Configuration bus interface circuit for FPGAS
JP3743487B2 (ja) * 1999-07-14 2006-02-08 富士ゼロックス株式会社 プログラマブル論理回路装置、情報処理システム、プログラマブル論理回路装置への回路の再構成方法、プログラマブル論理回路装置用の回路情報の圧縮方法
US6629311B1 (en) * 1999-11-17 2003-09-30 Altera Corporation Apparatus and method for configuring a programmable logic device with a configuration controller operating as an interface to a configuration memory
US6493862B1 (en) 2000-07-25 2002-12-10 Xilinx Inc. Method for compressing an FPGA bitsream
US6526557B1 (en) * 2000-07-25 2003-02-25 Xilinx, Inc. Architecture and method for partially reconfiguring an FPGA

Also Published As

Publication number Publication date
US20040113655A1 (en) 2004-06-17
US6907595B2 (en) 2005-06-14

Similar Documents

Publication Publication Date Title
DE60333484D1 (de) Umkonfiguration der programmierbaren logik einer integrierten schaltung
DE60328426D1 (de) Gestaltung der Verschlusselemente
DE60218932D1 (de) Integrierte Schaltkreisstruktur
DE60336204D1 (de) Integrierte Schaltung mit programmierbaren Schmelzsicherungsarray
DE60236568D1 (de) Strahlkreislaufanordnung
DE60218087D1 (de) Strahlkreislaufanordnung
DE60220053D1 (de) Schaltkreis
DE60230568D1 (de) Integrierte Radiofrequenz-Schaltkreise
EP1571680A4 (de) Elektronisches teil mit externer elektrode
DE60333289D1 (de) Chip verbunden mit einer integrierten schaltung
DE60322149D1 (de) Ladungsleseschaltung
DE60227475D1 (de) Halbleiterbauelement
DE602004031698D1 (de) Integrierte Halbleiterschaltung
DE10238843B8 (de) Halbleiterbauelement
DE602004029302D1 (de) Stromrichterschaltung
DE60218046D1 (de) Anlaufschaltung
DE60203191D1 (de) Verbindungsschaltkreis
DE60122381D1 (de) Hochfrequenz-halbleiterbauelement
DE60314962D1 (de) Halbleiterschaltkreis
DE60227632D1 (de) Sperrung der Funktion in einer integrierten Schaltung
DE60204532D1 (de) Oszillatorschaltung
DE60225790D1 (de) Halbleiterbauelement
DE60221625D1 (de) Integrierte Halbleiterschaltung
DE60309530D1 (de) Einschalt-Rücksetzschaltung
DE50202252D1 (de) Wandlerschaltung