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DE60316931D1 - System und verfahren zum erzeugen einer referenzspannung durch mitteln der von zwei komplementär programmierten dual bit referenzzellen gelieferten spannungen - Google Patents

System und verfahren zum erzeugen einer referenzspannung durch mitteln der von zwei komplementär programmierten dual bit referenzzellen gelieferten spannungen

Info

Publication number
DE60316931D1
DE60316931D1 DE60316931T DE60316931T DE60316931D1 DE 60316931 D1 DE60316931 D1 DE 60316931D1 DE 60316931 T DE60316931 T DE 60316931T DE 60316931 T DE60316931 T DE 60316931T DE 60316931 D1 DE60316931 D1 DE 60316931D1
Authority
DE
Germany
Prior art keywords
generating
reference voltage
dual bit
voltages delivered
complementary
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE60316931T
Other languages
English (en)
Other versions
DE60316931T2 (de
Inventor
Michael A Vanbuskirk
Darlene G Hamilton
Pau-Ling Chen
Kazuhiro Kurihara
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Spansion LLC
Original Assignee
Spansion LLC
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Spansion LLC filed Critical Spansion LLC
Application granted granted Critical
Publication of DE60316931D1 publication Critical patent/DE60316931D1/de
Publication of DE60316931T2 publication Critical patent/DE60316931T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/26—Sensing or reading circuits; Data output circuits
    • G11C16/28—Sensing or reading circuits; Data output circuits using differential sensing or reference cells, e.g. dummy cells
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/56—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
    • G11C11/5621—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency using charge storage in a floating gate
    • G11C11/5642—Sensing or reading circuits; Data output circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/56—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
    • G11C11/5671—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency using charge trapping in an insulator
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
    • G11C16/0466—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells with charge storage in an insulating layer, e.g. metal-nitride-oxide-silicon [MNOS], silicon-oxide-nitride-oxide-silicon [SONOS]
    • G11C16/0475—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells with charge storage in an insulating layer, e.g. metal-nitride-oxide-silicon [MNOS], silicon-oxide-nitride-oxide-silicon [SONOS] comprising two or more independent storage sites which store independent data
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/30—Power supply circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/14—Power supply arrangements, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/14—Dummy cell management; Sense reference voltage generators
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2211/00—Indexing scheme relating to digital stores characterized by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C2211/56—Indexing scheme relating to G11C11/56 and sub-groups for features not covered by these groups
    • G11C2211/563—Multilevel memory reading aspects
    • G11C2211/5634—Reference cells

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Read Only Memory (AREA)
  • Semiconductor Memories (AREA)
  • Non-Volatile Memory (AREA)
DE60316931T 2002-04-12 2003-03-03 System und verfahren zum erzeugen einer referenzspannung durch mitteln der von zwei komplementär programmierten dual bit referenzzellen gelieferten spannungen Expired - Lifetime DE60316931T2 (de)

Applications Claiming Priority (5)

Application Number Priority Date Filing Date Title
US37236102P 2002-04-12 2002-04-12
US372361P 2002-04-12
US136173 2002-05-01
US10/136,173 US6799256B2 (en) 2002-04-12 2002-05-01 System and method for multi-bit flash reads using dual dynamic references
PCT/US2003/006589 WO2003088261A1 (en) 2002-04-12 2003-03-03 System and method for generating a reference voltage based on averaging the voltages of two complementary programmed dual bit reference cells

Publications (2)

Publication Number Publication Date
DE60316931D1 true DE60316931D1 (de) 2007-11-29
DE60316931T2 DE60316931T2 (de) 2008-07-24

Family

ID=29254029

Family Applications (1)

Application Number Title Priority Date Filing Date
DE60316931T Expired - Lifetime DE60316931T2 (de) 2002-04-12 2003-03-03 System und verfahren zum erzeugen einer referenzspannung durch mitteln der von zwei komplementär programmierten dual bit referenzzellen gelieferten spannungen

Country Status (9)

Country Link
US (2) US6799256B2 (de)
EP (1) EP1495471B1 (de)
JP (1) JP2005526341A (de)
KR (1) KR100953208B1 (de)
CN (1) CN100555456C (de)
AU (1) AU2003228271A1 (de)
DE (1) DE60316931T2 (de)
TW (1) TWI286755B (de)
WO (1) WO2003088261A1 (de)

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US7808818B2 (en) 2006-01-12 2010-10-05 Saifun Semiconductors Ltd. Secondary injection for NROM
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Also Published As

Publication number Publication date
DE60316931T2 (de) 2008-07-24
WO2003088261A1 (en) 2003-10-23
EP1495471A1 (de) 2005-01-12
KR20050003365A (ko) 2005-01-10
TWI286755B (en) 2007-09-11
KR100953208B1 (ko) 2010-04-15
AU2003228271A1 (en) 2003-10-27
US20030208663A1 (en) 2003-11-06
JP2005526341A (ja) 2005-09-02
US7103706B1 (en) 2006-09-05
CN100555456C (zh) 2009-10-28
TW200402064A (en) 2004-02-01
CN1647215A (zh) 2005-07-27
EP1495471B1 (de) 2007-10-17
US6799256B2 (en) 2004-09-28

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