DE60307425D1 - Schaltung für logische operationen und verfahren für logische operationen - Google Patents
Schaltung für logische operationen und verfahren für logische operationenInfo
- Publication number
- DE60307425D1 DE60307425D1 DE60307425T DE60307425T DE60307425D1 DE 60307425 D1 DE60307425 D1 DE 60307425D1 DE 60307425 T DE60307425 T DE 60307425T DE 60307425 T DE60307425 T DE 60307425T DE 60307425 D1 DE60307425 D1 DE 60307425D1
- Authority
- DE
- Germany
- Prior art keywords
- logical operations
- procedures
- circuit
- logical
- operations
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 238000000034 method Methods 0.000 title 1
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
- H03K19/185—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using dielectric elements with variable dielectric constant, e.g. ferro-electric capacitors
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/22—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using ferroelectric elements
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1006—Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
- H03K19/16—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using saturable magnetic devices
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/02—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements
- G11C11/16—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect
- G11C11/165—Auxiliary circuits
- G11C11/1659—Cell access
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C2207/00—Indexing scheme relating to arrangements for writing information into, or reading information out from, a digital store
- G11C2207/10—Aspects relating to interfaces of memory device to external buses
- G11C2207/104—Embedded memory devices, e.g. memories with a processing device on the same die or ASIC memory designs
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Computing Systems (AREA)
- General Engineering & Computer Science (AREA)
- Mathematical Physics (AREA)
- Power Engineering (AREA)
- Dram (AREA)
- Static Random-Access Memory (AREA)
- Mram Or Spin Memory Techniques (AREA)
- Semiconductor Memories (AREA)
- Logic Circuits (AREA)
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2002018661 | 2002-01-28 | ||
| JP2002018661 | 2002-01-28 | ||
| PCT/JP2003/000568 WO2003065582A1 (en) | 2002-01-28 | 2003-01-22 | Logical operation circuit and logical operation method |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| DE60307425D1 true DE60307425D1 (de) | 2006-09-21 |
| DE60307425T2 DE60307425T2 (de) | 2006-12-14 |
Family
ID=27653920
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| DE60307425T Expired - Lifetime DE60307425T2 (de) | 2002-01-28 | 2003-01-22 | Schaltung für logische operationen und verfahren für logische operationen |
Country Status (7)
| Country | Link |
|---|---|
| US (1) | US7450412B2 (de) |
| EP (1) | EP1471643B1 (de) |
| JP (1) | JP4105099B2 (de) |
| CN (1) | CN1291553C (de) |
| DE (1) | DE60307425T2 (de) |
| TW (1) | TWI267851B (de) |
| WO (1) | WO2003065582A1 (de) |
Families Citing this family (14)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE10320701A1 (de) | 2003-05-08 | 2004-12-23 | Siemens Ag | Bauelement mit einer in ihrer Funktionalität konfigurierbaren Schaltungsanordnung, insbesondere Logikschaltungsanordnung |
| JP3853766B2 (ja) * | 2003-07-25 | 2006-12-06 | ローム株式会社 | 論理演算回路および論理演算装置 |
| KR100612884B1 (ko) | 2004-12-30 | 2006-08-14 | 삼성전자주식회사 | 자기 논리 소자와 그 제조 및 동작 방법 |
| DE102005036066B3 (de) * | 2005-08-01 | 2006-09-21 | Siemens Ag | Bauelement mit einer in ihrer Funktionalität konfigurierbaren Schaltungsanordnung |
| TW201217993A (en) * | 2010-10-20 | 2012-05-01 | Huafan University | employing operation on decomposed matrices to reduce operation amount for single matrix per unit time for light-weighting matrix operation process in simpler operation circuit |
| US9106223B2 (en) * | 2013-05-20 | 2015-08-11 | Semiconductor Energy Laboratory Co., Ltd. | Signal processing device |
| TWI549090B (zh) * | 2014-08-29 | 2016-09-11 | 華梵大學 | Portable sensing operation device |
| WO2016190880A1 (en) * | 2015-05-28 | 2016-12-01 | Intel Corporation | Ferroelectric based memory cell with non-volatile retention |
| JP6696853B2 (ja) * | 2016-07-29 | 2020-05-20 | 株式会社ジャパンディスプレイ | 力検出装置 |
| CN109542839B (zh) * | 2019-01-18 | 2024-09-03 | 清华大学 | 融合非易失多值存储与逻辑运算功能的动态可控器件单元 |
| CN112133339B (zh) * | 2020-08-12 | 2023-03-14 | 清华大学 | 基于铁电晶体管的存内按位逻辑计算电路结构 |
| US11764255B2 (en) * | 2021-04-28 | 2023-09-19 | National Central University | Memory circuit, memory device and operation method thereof |
| CN114280998B (zh) * | 2021-12-29 | 2024-03-29 | 北京超弦存储器研究院 | 一种逻辑运算控制电路、方法、装置及介质 |
| JP7541190B2 (ja) | 2022-01-10 | 2024-08-27 | 之江実験室 | コンピュートインメモリトランジスタによるブール論理の実現方法、ユニット及び回路 |
Family Cites Families (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5038323A (en) * | 1990-03-06 | 1991-08-06 | The United States Of America As Represented By The Secretary Of The Navy | Non-volatile memory cell with ferroelectric capacitor having logically inactive electrode |
| JP3457106B2 (ja) * | 1995-10-13 | 2003-10-14 | ローム株式会社 | スイッチング用半導体素子、プログラム可能な機能装置およびプログラム可能な機能装置の動作方法 |
| US5808929A (en) * | 1995-12-06 | 1998-09-15 | Sheikholeslami; Ali | Nonvolatile content addressable memory |
| US5982683A (en) * | 1998-03-23 | 1999-11-09 | Advanced Micro Devices, Inc. | Enhanced method of testing semiconductor devices having nonvolatile elements |
| DE60239588D1 (de) * | 2001-12-28 | 2011-05-12 | Fujitsu Semiconductor Ltd | Programmierbare Logikschaltung mit ferroelektrischem Konfigurationsspeicher |
| JP3553554B2 (ja) * | 2002-03-05 | 2004-08-11 | ローム株式会社 | スイッチマトリックス回路、論理演算回路およびスイッチ回路 |
| JP3853766B2 (ja) * | 2003-07-25 | 2006-12-06 | ローム株式会社 | 論理演算回路および論理演算装置 |
-
2003
- 2003-01-22 DE DE60307425T patent/DE60307425T2/de not_active Expired - Lifetime
- 2003-01-22 CN CNB03802859XA patent/CN1291553C/zh not_active Expired - Fee Related
- 2003-01-22 US US10/502,265 patent/US7450412B2/en not_active Expired - Fee Related
- 2003-01-22 JP JP2003565049A patent/JP4105099B2/ja not_active Expired - Lifetime
- 2003-01-22 WO PCT/JP2003/000568 patent/WO2003065582A1/ja not_active Ceased
- 2003-01-22 EP EP03734829A patent/EP1471643B1/de not_active Expired - Lifetime
- 2003-01-27 TW TW092101736A patent/TWI267851B/zh not_active IP Right Cessation
Also Published As
| Publication number | Publication date |
|---|---|
| WO2003065582A1 (en) | 2003-08-07 |
| TWI267851B (en) | 2006-12-01 |
| JPWO2003065582A1 (ja) | 2005-05-26 |
| EP1471643A4 (de) | 2005-04-27 |
| US20050146922A1 (en) | 2005-07-07 |
| CN1625838A (zh) | 2005-06-08 |
| CN1291553C (zh) | 2006-12-20 |
| US7450412B2 (en) | 2008-11-11 |
| JP4105099B2 (ja) | 2008-06-18 |
| TW200302479A (en) | 2003-08-01 |
| EP1471643A1 (de) | 2004-10-27 |
| DE60307425T2 (de) | 2006-12-14 |
| EP1471643B1 (de) | 2006-08-09 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| 8364 | No opposition during term of opposition |