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DE60300777D1 - Nichtflüchtiger redundanzadressen-speicher - Google Patents

Nichtflüchtiger redundanzadressen-speicher

Info

Publication number
DE60300777D1
DE60300777D1 DE60300777T DE60300777T DE60300777D1 DE 60300777 D1 DE60300777 D1 DE 60300777D1 DE 60300777 T DE60300777 T DE 60300777T DE 60300777 T DE60300777 T DE 60300777T DE 60300777 D1 DE60300777 D1 DE 60300777D1
Authority
DE
Germany
Prior art keywords
address memory
redundancy address
volatile redundancy
volatile
memory
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE60300777T
Other languages
English (en)
Other versions
DE60300777T2 (de
Inventor
Heinz Hoenigschmid
Hans-Heinrich Viehmann
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Qimonda AG
Original Assignee
Infineon Technologies AG
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Infineon Technologies AG filed Critical Infineon Technologies AG
Publication of DE60300777D1 publication Critical patent/DE60300777D1/de
Application granted granted Critical
Publication of DE60300777T2 publication Critical patent/DE60300777T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/02—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements
    • G11C11/16—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/02—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements
    • G11C11/16—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect
    • G11C11/165—Auxiliary circuits
    • G11C11/1659—Cell access
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C17/00—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards
    • G11C17/14—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards in which contents are determined by selectively establishing, breaking or modifying connecting links by permanently altering the state of coupling elements, e.g. PROM
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/70—Masking faults in memories by using spares or by reconfiguring
    • G11C29/72—Masking faults in memories by using spares or by reconfiguring with optimized replacement algorithms
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/70—Masking faults in memories by using spares or by reconfiguring
    • G11C29/78—Masking faults in memories by using spares or by reconfiguring using programmable devices
    • G11C29/785—Masking faults in memories by using spares or by reconfiguring using programmable devices with redundancy programming schemes
    • G11C29/789—Masking faults in memories by using spares or by reconfiguring using programmable devices with redundancy programming schemes using non-volatile cells or latches

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • For Increasing The Reliability Of Semiconductor Memories (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)
  • Semiconductor Memories (AREA)
DE60300777T 2002-02-19 2003-02-18 Nichtflüchtiger redundanzadressen-speicher Expired - Lifetime DE60300777T2 (de)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US79774 1998-05-15
US10/079,774 US6801471B2 (en) 2002-02-19 2002-02-19 Fuse concept and method of operation
PCT/EP2003/001630 WO2003071554A2 (en) 2002-02-19 2003-02-18 Non-volatile redundancy adresses memory

Publications (2)

Publication Number Publication Date
DE60300777D1 true DE60300777D1 (de) 2005-07-07
DE60300777T2 DE60300777T2 (de) 2006-05-11

Family

ID=27733094

Family Applications (1)

Application Number Title Priority Date Filing Date
DE60300777T Expired - Lifetime DE60300777T2 (de) 2002-02-19 2003-02-18 Nichtflüchtiger redundanzadressen-speicher

Country Status (8)

Country Link
US (1) US6801471B2 (de)
EP (1) EP1476880B1 (de)
JP (1) JP2005518628A (de)
KR (1) KR100613535B1 (de)
CN (1) CN100505106C (de)
DE (1) DE60300777T2 (de)
TW (1) TWI277098B (de)
WO (1) WO2003071554A2 (de)

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US20060245230A1 (en) * 2005-04-29 2006-11-02 Ambroggi Luca D Memory module and method for operating a memory module
KR100716667B1 (ko) * 2005-04-29 2007-05-09 주식회사 하이닉스반도체 반도체 기억 소자의 리던던시 회로
US7761773B2 (en) * 2005-06-30 2010-07-20 Sigmatel, Inc. Semiconductor device including a unique identifier and error correction code
US7973349B2 (en) 2005-09-20 2011-07-05 Grandis Inc. Magnetic device having multilayered free ferromagnetic layer
US7777261B2 (en) * 2005-09-20 2010-08-17 Grandis Inc. Magnetic device having stabilized free ferromagnetic layer
US7859034B2 (en) * 2005-09-20 2010-12-28 Grandis Inc. Magnetic devices having oxide antiferromagnetic layer next to free ferromagnetic layer
US7362644B2 (en) * 2005-12-20 2008-04-22 Magic Technologies, Inc. Configurable MRAM and method of configuration
KR100819005B1 (ko) 2007-02-16 2008-04-03 삼성전자주식회사 저항체를 이용한 비휘발성 메모리 장치
KR100909902B1 (ko) * 2007-04-27 2009-07-30 삼성전자주식회사 플래쉬 메모리 장치 및 플래쉬 메모리 시스템
US7957179B2 (en) * 2007-06-27 2011-06-07 Grandis Inc. Magnetic shielding in magnetic multilayer structures
US7760538B1 (en) * 2008-03-04 2010-07-20 Xilinx, Inc. Non-volatile SRAM cell
US7894248B2 (en) 2008-09-12 2011-02-22 Grandis Inc. Programmable and redundant circuitry based on magnetic tunnel junction (MTJ)
CN101510445B (zh) * 2009-03-19 2012-11-21 无锡中星微电子有限公司 存储器坏块表的保存方法以及装置
CN102714061A (zh) * 2009-11-20 2012-10-03 拉姆伯斯公司 用于dram故障校正的位替代技术
US8547736B2 (en) * 2010-08-03 2013-10-01 Qualcomm Incorporated Generating a non-reversible state at a bitcell having a first magnetic tunnel junction and a second magnetic tunnel junction
US8848422B2 (en) 2011-04-25 2014-09-30 Panasonic Corporation Variable resistance nonvolatile memory device and driving method thereof
US8638596B2 (en) * 2011-07-25 2014-01-28 Qualcomm Incorporated Non-volatile memory saving cell information in a non-volatile memory array
KR20130021760A (ko) 2011-08-23 2013-03-06 삼성전자주식회사 자기터널접합 브레이크 다운을 이용한 안티퓨즈 회로, 및 이를 포함하는 반도체 장치
KR101938210B1 (ko) 2012-04-18 2019-01-15 삼성전자주식회사 낸드 플래시 메모리, 가변 저항 메모리 및 컨트롤러를 포함하는 메모리 시스템의 동작 방법
US9734921B2 (en) 2012-11-06 2017-08-15 Rambus Inc. Memory repair using external tags
KR20160062809A (ko) * 2014-11-25 2016-06-03 삼성전자주식회사 재쓰기를 이용하여 로우 비트 에러 레이트를 개선하는 메모리 시스템 및 그에 따른 재쓰기 방법
US10395748B2 (en) * 2016-06-15 2019-08-27 Micron Technology, Inc. Shared error detection and correction memory
DE102016112765B4 (de) * 2016-07-12 2024-04-25 Infineon Technologies Ag Magnetspeicherbauelement und Verfahren zum Betreiben desselben
KR102587648B1 (ko) * 2018-07-23 2023-10-11 삼성전자주식회사 적층형 메모리 장치, 이를 포함하는 메모리 시스템 및 적층형 메모리 장치의 테스트 방법
CN110895645B (zh) * 2018-09-12 2022-04-19 长鑫存储技术有限公司 目标修正码确定方法、装置、电子设备及存储介质
CN113495674B (zh) 2020-04-01 2023-10-10 长鑫存储技术有限公司 读写方法及存储器装置
CN113495671B (zh) 2020-04-01 2023-10-17 长鑫存储技术有限公司 读写方法及存储器装置
CN113495672B (zh) 2020-04-01 2023-08-11 长鑫存储技术有限公司 读写方法及存储器装置
CN113495675B (zh) 2020-04-01 2023-08-11 长鑫存储技术有限公司 读写方法及存储器装置
CN113495677B (zh) * 2020-04-01 2023-10-10 长鑫存储技术有限公司 读写方法及存储器装置
EP3964941B1 (de) 2020-04-01 2024-02-28 Changxin Memory Technologies, Inc. Lese-schreib-verfahren und speichervorrichtung
EP3985494B1 (de) 2020-04-01 2024-01-17 Changxin Memory Technologies, Inc. Lese-schreib-verfahren und speichervorrichtung
EP3936996A4 (de) 2020-04-01 2022-07-06 Changxin Memory Technologies, Inc. Lese-schreib-verfahren und speichervorrichtung
EP3964940A4 (de) 2020-04-01 2022-08-17 Changxin Memory Technologies, Inc. Lese-/schreib-verfahren und speichervorrichtung

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JP2914171B2 (ja) * 1994-04-25 1999-06-28 松下電器産業株式会社 半導体メモリ装置およびその駆動方法
US5771195A (en) * 1995-12-29 1998-06-23 Sgs-Thomson Microelectronics, Inc. Circuit and method for replacing a defective memory cell with a redundant memory cell
US5758056A (en) * 1996-02-08 1998-05-26 Barr; Robert C. Memory system having defective address identification and replacement
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JP2956634B2 (ja) * 1997-01-27 1999-10-04 日本電気株式会社 半導体記憶装置の冗長アドレス選択方式および半導体記憶装置
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KR100413762B1 (ko) * 2001-07-02 2003-12-31 삼성전자주식회사 뱅크 수를 가변할 수 있는 반도체 장치 및 그 방법
US7219271B2 (en) * 2001-12-14 2007-05-15 Sandisk 3D Llc Memory device and method for redundancy/self-repair
US6567300B1 (en) * 2002-02-22 2003-05-20 Infineon Technologies, Ag Narrow contact design for magnetic random access memory (MRAM) arrays
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Also Published As

Publication number Publication date
TW200303553A (en) 2003-09-01
US6801471B2 (en) 2004-10-05
WO2003071554A3 (en) 2003-12-24
CN1636250A (zh) 2005-07-06
DE60300777T2 (de) 2006-05-11
CN100505106C (zh) 2009-06-24
EP1476880B1 (de) 2005-06-01
WO2003071554A2 (en) 2003-08-28
EP1476880A2 (de) 2004-11-17
JP2005518628A (ja) 2005-06-23
TWI277098B (en) 2007-03-21
KR100613535B1 (ko) 2006-08-16
US20030156469A1 (en) 2003-08-21
KR20040083525A (ko) 2004-10-02

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8327 Change in the person/name/address of the patent owner

Owner name: QIMONDA AG, 81739 MUENCHEN, DE