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DE602006003316D1 - Herstellungsverfahren für halbleitergehäuse und mit diesem verfahren hergestellte gehäuse - Google Patents

Herstellungsverfahren für halbleitergehäuse und mit diesem verfahren hergestellte gehäuse

Info

Publication number
DE602006003316D1
DE602006003316D1 DE602006003316T DE602006003316T DE602006003316D1 DE 602006003316 D1 DE602006003316 D1 DE 602006003316D1 DE 602006003316 T DE602006003316 T DE 602006003316T DE 602006003316 T DE602006003316 T DE 602006003316T DE 602006003316 D1 DE602006003316 D1 DE 602006003316D1
Authority
DE
Germany
Prior art keywords
housings
resin layer
manufacturing
semiconductor
manufactured
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE602006003316T
Other languages
English (en)
Inventor
Veen Nicolaas J Van
Ronald Dekker
Coen C Tak
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Koninklijke Philips NV
Original Assignee
Koninklijke Philips Electronics NV
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Koninklijke Philips Electronics NV filed Critical Koninklijke Philips Electronics NV
Publication of DE602006003316D1 publication Critical patent/DE602006003316D1/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H10W70/614—
    • H10P72/74—
    • H10W70/093—
    • H10P72/7418—
    • H10P72/7424—
    • H10P72/7434—
    • H10W44/248—
    • H10W72/0198—
    • H10W90/00—

Landscapes

  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Control Of Vending Devices And Auxiliary Devices For Vending Devices (AREA)
  • Bipolar Transistors (AREA)
  • Crystals, And After-Treatments Of Crystals (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
DE602006003316T 2005-03-02 2006-02-27 Herstellungsverfahren für halbleitergehäuse und mit diesem verfahren hergestellte gehäuse Expired - Fee Related DE602006003316D1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
EP05101593 2005-03-02
PCT/IB2006/050599 WO2006092754A2 (en) 2005-03-02 2006-02-27 A method of manufacturing a semiconductor packages and packages made

Publications (1)

Publication Number Publication Date
DE602006003316D1 true DE602006003316D1 (de) 2008-12-04

Family

ID=36577514

Family Applications (1)

Application Number Title Priority Date Filing Date
DE602006003316T Expired - Fee Related DE602006003316D1 (de) 2005-03-02 2006-02-27 Herstellungsverfahren für halbleitergehäuse und mit diesem verfahren hergestellte gehäuse

Country Status (8)

Country Link
US (1) US20080150118A1 (de)
EP (1) EP1856728B1 (de)
JP (1) JP2008532307A (de)
CN (1) CN100514591C (de)
AT (1) ATE412251T1 (de)
DE (1) DE602006003316D1 (de)
TW (1) TW200711081A (de)
WO (1) WO2006092754A2 (de)

Families Citing this family (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1905083A2 (de) * 2005-07-01 2008-04-02 Koninklijke Philips Electronics N.V. Elektronische einrichtung
EP1949441A2 (de) * 2005-11-11 2008-07-30 Koninklijke Philips Electronics N.V. Chip-baugruppe und herstellungsverfahren dafür
JP4956128B2 (ja) * 2006-10-02 2012-06-20 ルネサスエレクトロニクス株式会社 電子装置の製造方法
US8093689B2 (en) * 2007-07-02 2012-01-10 Infineon Technologies Ag Attachment member for semiconductor sensor device
US8114708B2 (en) * 2008-09-30 2012-02-14 General Electric Company System and method for pre-patterned embedded chip build-up
TW201114003A (en) * 2008-12-11 2011-04-16 Xintec Inc Chip package structure and method for fabricating the same
US8072041B2 (en) * 2009-04-08 2011-12-06 Finisar Corporation Passivated optical detectors with full protection layer
CN104133314B (zh) 2009-05-02 2019-07-12 株式会社半导体能源研究所 显示设备
US8212340B2 (en) * 2009-07-13 2012-07-03 Advanced Semiconductor Engineering, Inc. Chip package and manufacturing method thereof
US8952519B2 (en) * 2010-01-13 2015-02-10 Chia-Sheng Lin Chip package and fabrication method thereof
JP5521862B2 (ja) * 2010-07-29 2014-06-18 三菱電機株式会社 半導体装置の製造方法
US10446442B2 (en) * 2016-12-21 2019-10-15 Globalfoundries Inc. Integrated circuit chip with molding compound handler substrate and method
KR20180136148A (ko) * 2017-06-14 2018-12-24 에스케이하이닉스 주식회사 범프를 구비하는 반도체 장치
DE102019100130B4 (de) * 2018-04-10 2021-11-04 Infineon Technologies Ag Ein halbleiterbauelement und ein verfahren zum bilden eines halbleiterbauelements
KR102435517B1 (ko) * 2018-04-12 2022-08-22 에스케이하이닉스 주식회사 칩 스택 패키지
KR102545168B1 (ko) * 2019-03-26 2023-06-19 삼성전자주식회사 인터포저 및 이를 포함하는 반도체 패키지

Family Cites Families (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2599893B1 (fr) * 1986-05-23 1996-08-02 Ricoh Kk Procede de montage d'un module electronique sur un substrat et carte a circuit integre
US5386623A (en) * 1990-11-15 1995-02-07 Hitachi, Ltd. Process for manufacturing a multi-chip module
US5336928A (en) * 1992-09-18 1994-08-09 General Electric Company Hermetically sealed packaged electronic system
EP1041624A1 (de) * 1999-04-02 2000-10-04 Interuniversitair Microelektronica Centrum Vzw Transfermethode ultra-dünner Substrate und Anwendung zur Herstellung von Mehrlagen-Dünnschichtstrukturen
US6242282B1 (en) * 1999-10-04 2001-06-05 General Electric Company Circuit chip package and fabrication method
US6734534B1 (en) * 2000-08-16 2004-05-11 Intel Corporation Microelectronic substrate with integrated devices
US6720270B1 (en) * 2000-09-13 2004-04-13 Siliconware Precision Industries Co., Ltd. Method for reducing size of semiconductor unit in packaging process
US6586276B2 (en) * 2001-07-11 2003-07-01 Intel Corporation Method for fabricating a microelectronic device using wafer-level adhesion layer deposition
TW517361B (en) * 2001-12-31 2003-01-11 Megic Corp Chip package structure and its manufacture process
JP4100936B2 (ja) * 2002-03-01 2008-06-11 Ｎｅｃエレクトロニクス株式会社 半導体装置の製造方法
US6798057B2 (en) * 2002-11-05 2004-09-28 Micron Technology, Inc. Thin stacked ball-grid array package
JP4056854B2 (ja) * 2002-11-05 2008-03-05 新光電気工業株式会社 半導体装置の製造方法
US7180149B2 (en) * 2003-08-28 2007-02-20 Fujikura Ltd. Semiconductor package with through-hole
WO2005117096A1 (ja) * 2004-05-31 2005-12-08 Sharp Takaya Electronics Industry Co., Ltd. 回路モジュールの製造方法、及びその方法により製造された回路モジュール

Also Published As

Publication number Publication date
CN100514591C (zh) 2009-07-15
US20080150118A1 (en) 2008-06-26
TW200711081A (en) 2007-03-16
WO2006092754A3 (en) 2007-01-18
ATE412251T1 (de) 2008-11-15
WO2006092754A2 (en) 2006-09-08
JP2008532307A (ja) 2008-08-14
EP1856728A2 (de) 2007-11-21
EP1856728B1 (de) 2008-10-22
CN101133484A (zh) 2008-02-27

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee