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WO2008126468A1 - 半導体装置及び半導体装置の製造方法 - Google Patents

半導体装置及び半導体装置の製造方法 Download PDF

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Publication number
WO2008126468A1
WO2008126468A1 PCT/JP2008/052326 JP2008052326W WO2008126468A1 WO 2008126468 A1 WO2008126468 A1 WO 2008126468A1 JP 2008052326 W JP2008052326 W JP 2008052326W WO 2008126468 A1 WO2008126468 A1 WO 2008126468A1
Authority
WO
WIPO (PCT)
Prior art keywords
wiring
semiconductor device
topmost layer
pad
super connect
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/JP2008/052326
Other languages
English (en)
French (fr)
Inventor
Shintaro Yamamichi
Katsumi Kikuchi
Jun Sakai
Hikaru Kouta
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to US12/593,824 priority Critical patent/US8004085B2/en
Priority to JP2009508949A priority patent/JPWO2008126468A1/ja
Publication of WO2008126468A1 publication Critical patent/WO2008126468A1/ja
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

Links

Classifications

    • H10W20/435—
    • H10W20/427—
    • H10W72/20—
    • H10W74/137—
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1901—Structure
    • H01L2924/1904—Component type
    • H01L2924/19041—Component type being a capacitor
    • H10W72/242—
    • H10W72/252—
    • H10W72/9226—
    • H10W72/923—
    • H10W72/9415—
    • H10W72/942—
    • H10W72/952—

Landscapes

  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Semiconductor Integrated Circuits (AREA)

Abstract

　半導体装置は、素子配線２と素子最上層配線４とスーパーコネクト配線１０とバンプ７とを具備する。素子配線２は、半導体基板１上に複数の絶縁層５０を介して設けられる。素子最上層配線４は、素子配線２上に実質上同等のプロセス装置を用いて形成される。スーパーコネクト配線１０は、素子最上層配線４上に絶縁層５０の５倍以上の厚さを有するスーパーコネクト絶縁層９を介して設けられ、素子配線２及び素子最上層配線４の３倍以上の厚さを有する。バンプ７は、スーパーコネクト配線１０上に形成される。素子最上層配線４は、信号用パッド４ｓと電源用パッド４ｖとグランド用パッド４ｇを備える。信号用パッド４ｓの面積は、電源用パッド４ｖ及びグランド用パッド４ｇの面積よりも小さい。
PCT/JP2008/052326 2007-03-30 2008-02-13 半導体装置及び半導体装置の製造方法 Ceased WO2008126468A1 (ja)

Priority Applications (2)

Application Number Priority Date Filing Date Title
US12/593,824 US8004085B2 (en) 2007-03-30 2008-02-13 Semiconductor device and method of manufacturing semiconductor device
JP2009508949A JPWO2008126468A1 (ja) 2007-03-30 2008-02-13 半導体装置及び半導体装置の製造方法

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2007092727 2007-03-30
JP2007-092727 2007-03-30

Publications (1)

Publication Number Publication Date
WO2008126468A1 true WO2008126468A1 (ja) 2008-10-23

Family

ID=39863625

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/JP2008/052326 Ceased WO2008126468A1 (ja) 2007-03-30 2008-02-13 半導体装置及び半導体装置の製造方法

Country Status (3)

Country Link
US (1) US8004085B2 (ja)
JP (1) JPWO2008126468A1 (ja)
WO (1) WO2008126468A1 (ja)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPWO2010026956A1 (ja) * 2008-09-02 2012-02-02 日本電気株式会社 半導体装置及びその製造方法
JP2013187218A (ja) * 2012-03-06 2013-09-19 Lapis Semiconductor Co Ltd 半導体集積装置
JP2015079892A (ja) * 2013-10-17 2015-04-23 住友電気工業株式会社 電極パッド構造

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* Cited by examiner, † Cited by third party
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JP4538764B2 (ja) * 2008-07-24 2010-09-08 カシオ計算機株式会社 半導体装置およびその製造方法
US8653662B2 (en) * 2012-05-02 2014-02-18 International Business Machines Corporation Structure for monitoring stress induced failures in interlevel dielectric layers of solder bump integrated circuits
EP3155666B1 (en) 2014-06-16 2021-05-12 Intel IP Corporation Metal on both sides with clock gated power and signal routing underneath
US11251156B2 (en) 2015-12-23 2022-02-15 Intel Corporation Fabrication and use of through silicon vias on double sided interconnect device
DE102018109028B4 (de) 2017-06-30 2023-09-07 Taiwan Semiconductor Manufacturing Co., Ltd. Halbleitervorrichtung mit Abschirmstruktur zur Verringerung von Übersprechen und Verfahren zur Herstellung derselben
US10269728B2 (en) * 2017-06-30 2019-04-23 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device with shielding structure for cross-talk reduction
US10396053B2 (en) 2017-11-17 2019-08-27 General Electric Company Semiconductor logic device and system and method of embedded packaging of same
US10276523B1 (en) * 2017-11-17 2019-04-30 General Electric Company Semiconductor logic device and system and method of embedded packaging of same
US10566301B2 (en) 2017-11-17 2020-02-18 General Electric Company Semiconductor logic device and system and method of embedded packaging of same
KR102704110B1 (ko) * 2019-08-09 2024-09-06 삼성전자주식회사 두꺼운 금속층 및 범프를 갖는 반도체 소자들

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JP2002212782A (ja) * 2000-11-14 2002-07-31 Hitachi Maxell Ltd 電気メッキ構造及び当該電気メッキ構造を有する配線基板
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JP3226703B2 (ja) * 1994-03-18 2001-11-05 株式会社日立製作所 半導体装置及びその製法
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JP2002212782A (ja) * 2000-11-14 2002-07-31 Hitachi Maxell Ltd 電気メッキ構造及び当該電気メッキ構造を有する配線基板
JP2002353614A (ja) * 2001-05-29 2002-12-06 Fujitsu Ltd 多層配線層を有する基板及びその製造方法
JP2003060053A (ja) * 2001-08-10 2003-02-28 Fujitsu Ltd 半導体チップ及びそれを用いた半導体集積回路装置及び半導体チップ選択方法
JP2004056036A (ja) * 2002-07-24 2004-02-19 Sony Corp 半導体装置の製造方法

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPWO2010026956A1 (ja) * 2008-09-02 2012-02-02 日本電気株式会社 半導体装置及びその製造方法
JP2013187218A (ja) * 2012-03-06 2013-09-19 Lapis Semiconductor Co Ltd 半導体集積装置
JP2015079892A (ja) * 2013-10-17 2015-04-23 住友電気工業株式会社 電極パッド構造

Also Published As

Publication number Publication date
US8004085B2 (en) 2011-08-23
US20100117228A1 (en) 2010-05-13
JPWO2008126468A1 (ja) 2010-07-22

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