DE3002492A1 - NON-SELF-EXTINGUISHING STORAGE DEVICE AND METHOD FOR OPERATING THIS DEVICE - Google Patents

Description

Non-self-erasing memory device and method of operating that device .

The present invention relates primarily to the field of MOS RAM memory systems and, more particularly, to new static RAM systems, die, a circular element with an integrated floating gate include. The abbreviation "MOS" results from the term "metal-oxide-semiconductor". The abbreviation "-.RAM" was derived from the term "random access memory".

Many static RAM arrangements use bistable semiconductor circuits, such as flip-flop circles, as memory cells for storing binary data ("1" and "0"). To be in such Static memory cells to store information must have an electrical current from an electrical supply source continuously in one of the two cross-coupled Circular branches flow and, in comparison, from the other

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Be separate from branches. Two (binary) distinguishable memory states for information storage are thereby created / which depend on which branch is leading and which Branch is not conductive. Such semiconductor memory cells are therefore referred to as "volatile" or self-extinguishing because when the electrical power or the supply voltage is removed becomes, the current discriminating the memory state stops flowing in the current-carrying branch, and therefore because the Information in this cell is lost. This self-erasing is a major disadvantage of conventional ones Storage systems and considerable efforts have been made to develop circular elements and structures with which it can be achieved that semiconductor circuits do not have a self-extinguishing effect when the supply voltage is removed will. Examples of publications are listed below:

E. Harari, et al, "A 256-Bit Nonvolatile Static RAM", 1978 IEEE International Solid State Circuits Conference Digest, pp. 108-109; F. Berenga, et al. "E ² -PROM TV Synthesizer", 1978 IEEE International Solid State Circuit Conference Digest,

Pp. 196-197; M. Hörne et al., "A Military Grade 1024-bit Nonvolatile Semiconductor RAM ", IEEE Trans. Electron Devices, VoI. ED-25, No. 8, (1978), pp. 1061-1065; Y. Uchida, et al., "1K Nonvolatile Semiconductor Read / Write RAM," IEEE Trans. Electron Devices, Vol. ED-25, No. 8, (1978), pp. 1065-1070; D. Frohmann, "A Fully-Decoded 2048-Bit Electrically Programmable MOS-ROM ", 1971 IEEE International Solid State Circuits Conference Digest, pp. 80-81; US Patent No. 3,660,819; US Patent No. 4,099 196; US Patent No. 4,500 142, Dimaria et al., 0. "Interface Effects and High Conductivity in Oxides Grown from Polycrystalline Silicon ", Applied Phys. letters (1975), pp. 505-507; R.M. Anderson, et al.," Evidence for Surface Asperity Mechanism of Conductivity in Oxide Grown on Polycrystalline Silicon ", J. of Appl. Phys., Vol. 48, No. 11 (1977), pp. 4834-4836.

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Facilities on a structure with a MOS floating gate are traditionally used for systems that retain data over an extended period of time can. A floating gate is an island of conductive material that rests on the substrate is electrically isolated but capacitively coupled to the substrate. This island forms the gate of a MOS transistor. Depending on the presence or absence of charge on this floating gate, the MOS transistor conductive ("on") or non-conductive ("off") and thus forms the basis for storing binary "V" or "0" data by a storage device. This data corresponds to the presence or absence of the charge on the floating gate. There are numerous facilities for creating signal

15. Charge to the floating gate and remove the signal charge known from the floating gate. Once there is a charge on the gate, it remains permanent trapped because the floating gate is completely surrounded by an insulating material which, with respect to a discharge of the floating gate acts as a barrier. Charge can be applied to the floating gate in that a "hot" or live electron injection and / or tunnel mechanisms can be used. This allows cargo to be transported from the floating gate are removed so that it is exposed to radiation (UV light, X-rays) that a Avalanche injection comes into effect or that so-called tunnel effects are used. The term "tunneling" is used used here in the broadest sense, so that also ax emission of an electron from the surface of a conductor into a . adjacent insulator is enclosed by the energy barrier.

Static RAM memories that are not self-erasing are known to be which is a non-self-extinguishing element with a floating gate

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3Q02492

-8- ■. ■

in which a very thin gate oxide is used. However, such devices have a number of Disadvantages. The charge is bidirectional to an element with a floating gate and from an element with a floating gate tunneled through a relatively thin, (50 to 200 A) oxide, its reliable manufacture with a reasonable Integrity can be difficult. Because the very thin oxide allows tunneling in two directions, the non-self-erasing RAM cell may be exposed to malfunctions that cause the contents of the memory to be lost walk. In particular, such problems can include limitations in the number of read cycles and disturbances in the memory contents of a cell caused by the operation of neighboring cells. Other non-self-erasing RAM devices do not use floating gates, but an MNOS structure (metal-nitride-oxide-semiconductor) in which Charge is retained at the boundary between a silicon nitride and a silicon dioxide layer. Such However, MNOS facilities are also subject to disturbances,

2 Z which not only limit the write cycles, but also the read cycles. These disturbances limit the widespread use of MNOS devices.

It is desirable to couple a non-self-erasing element to 2Ξ a RAM circuit in order to prevent self-erasing

to effect in a semiconductor memory device. However, known coupled devices have numerous significant disadvantages. For example, such a coupling can be carried out in that an imbalance 3 Z of the conductance is introduced, which is caused by the non-self-extinguishing element directly between the two branches of a cross-coupled static RAM cell. Such an imbalance in the conductance causes the static,

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3Q02A92

Cross-coupled RAM cell carries an increased direct current, which must be overcome if the cell is in normal RAM operation is working. Such imbalances can lead to edge disturbances when writing and for the entire memory circuit Reading enter. In addition, such boundary disturbances lead to manufacturing limitations and testing problems "

Another important factor relating to the coupling of the non-self-erasing elements to static RAM cells is to give a compactness and simplicity to the structure of the device, since these factors the size and affect the cost of the district. Known interface systems disadvantageously tend to be complex Interface in relation to the control signals and their own transistors require, resulting in a considerable size of not self-erasing static RAM circuits and correspondingly high costs.

Numerous known non-self-erasing static RAM devices also tend to suffer from high current requirements and high operating voltages. These requirements place limits and complicate the performance and speed for the facility building the circle. Numerous known non-self-erasing static RAM devices use the semiconductor substrate as the main element in programming the non-self-erasing memory components, which is creating of high voltages on the supply line of the RAM to include in the non-self-erasing element to be able to store, so that it becomes difficult to understand the structure and the manufacturing process of the RAM cell from the structure and to optimize and separate the manufacturing process of the non-self-extinguishing element independently. In addition, if in The data contained in the non-self-erasing memory element is called up to the RAM line, this data can be sent to the RAM cell in a complementary form or in a different

opposite state to the state with which it was originally written in the non-self-erasing element have been created. Therefore if a binary "O" passed through a conductive first branch and a non-conductive second branch of such a conventional flip-flop RAM cell is shown in the non-self-erasing Element is written and subsequently written back to the RAM cell, the first branch of the RAM cell will not conductive and the second branch conductive, which corresponds to the representation of a binary "1". This "retrieval in the complementary Form instead of direct retrieval in the real form represents a major disadvantage, that of one's own circles must be countered or which the user of the storage system must take into account in another way. 15th

It is therefore an object of the present invention to provide improved, non-self-erasing static memory cells with random access and storage facilities. Another object of the present invention is to non-self-erasing static RAM devices and memory arrangements specify such devices that are balanced in terms of conductance or direct current, and the static RAM cells in the coupling relationship between static RAM cells and non-self-erasing ones Components of the cells can impart a capacitive or dynamic imbalance. Another task of the present invention is non-self-erasing static memory cells and devices with random Specify access in which a static RAM part and a non-self-erasing part of the memory cell are separated from each other can be optimized separately. Another object of the present invention is to provide a compact, highly Dimensions of densely packed, non-self-extinguishing, static RAM cell that is relatively simple and not expensive to manufacture is. Another object of the present invention

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is to provide a non-self-erasing static RAM that will not draw essentially any direct current from the high voltage supply source during programming.
5

The following is a description of the present invention and its embodiments explained in connection with the figures. It shows:

Figure 1 is a plan view of an embodiment of an inventive, non-self-erasing, static memory cell with random access, with metal contacts and interconnection have not yet been applied,

Figure 2 is a semi-schematic plan view of the non-self-extinguishing Cell element of the memory cell of Figure 2,

FIG. 3 is a cross-section along line 3-3 of FIG

Figure 2, shown not self-extinguishing cell elements, which is still in production,

FIG. 4 shows a cross section through that shown in FIG not self-extinguishing cell element along

the line 4-4, where the element is still in production, and

FIG. 5 shows a schematic circuit diagram of the non-self-erasing static memory cell of FIG. 1.

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In general, the present invention relates to one
non self-erasing semiconductor memory device with
a bi-stable, self-erasing semiconductor memory cell
for storing binary data in the form of one of two states of the memory circuit, with an addressing device for reading out binary data from the bistable self-erasing semiconductor memory cell and for writing binary data into the bistable self-erasing semiconductor memory cell and with a non-self-erasing memory element for storing binary data in the form of
a level of two electrical charge levels one
Floating gates, regardless of the memory state of the
self-erasing memory cell. The devices also contain a device for capacitive coupling of the self-erasing memory cell to the memory element with the

Floating gate and for the unchanged transfer of the memory state of the bistable memory cell to the element with the floating gate as a predetermined memory state of the
Floating gates together with a device for capacitive coupling of the element with the floating gate to the self-erasing semiconductor memory cell for the unchanged transfer of the memory state of the floating gate of the not
self-extinguishing element to the self-extinguishing cell after applying electrical power to the self-

erasing memory cell. The device for unchanged transfer of the memory state of the bistable memory cell to the element with the floating gate and the device for unchanged transfer of the memory state of the element with the floating gate to the bistable memory cell are operated in such a way that after the unchanged transfer of the original memory state of the circle of bistable
Cell into the element with the floating gate and then after the unchanged transfer of the memory state of the element with the floating gate to the self-erasing cell, the bistable cell is returned to its original memory state. With the bistable self-extinguishing

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Memory cells can desirably be static cross-coupled MOS flip-flops with four or six Trading transistors. In accordance with the present invention, the devices are desirably arranged in a memory array, such as a random access memory array according to conventional practice.

Having described the invention in terms of a general form has been / is now in particular with regard to those in the Figures 1 to 5 illustrated specific embodiment described. An embodiment of a non-self-erasing, static, memory cell is shown in FIGS random access according to the present invention. The illustrated cell 10 contains a self-extinguishing, static, bistable flip-flop memory cell 12 and an electrically changeable element 14 that is not self-erasing with a floating gate. The cell 10 shown forms part of an x-y addressable memory with random Access and the self-erasing memory cell 12 can therefore be referred to below as a static RAM cell, although such cells can be used in connection with the construction of other memory arrays.

The figure * 1 shows essentially one in the correct proportion close inspection of the design of a chip. Numerous known non-self-erasing static RAM arrangements tend to be also for the design of the device 10, which has the polysilicon electrode structure of the cell of the arrangement. The circle, which is schematic for the arrangement 10, is shown in FIG and for the purpose of clearly describing the present invention are the circular elements of the assembly 1 shown in a somewhat simplified form in FIGS. As shown in Figure 1, this is The layout for the cell 10 is relatively compact. The layout can be a unit of a random access arrangement, which has similar adjoining cells which, as shown, generally have relative cell dimensions.

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wise, using five-micron design rules and the dimensions of a cell unit are approximately 82.5 μι 79 μΐη.

In FIG. 2, there are η-implanted regions of the silicon substrate 11 represented by a solid line and cross hatching. About the numerous layers of polysilicon To illustrate the overlapping structure of the arrangement 10 are the successively deposited polysilicon layers represented by different lines. The pattern of the first silicon layer 50 is indicated by solid lines with additional points. The second polysilicon layer 52 is through solid lines marked with additional "x" marks. Finally, there is the third layer of polysilicon 54 represented by dashed lines. Areas of buried contacts 61, 62 that form the polysilicon layer connecting to the n-channel zone are shown by tight dashed lines. 3hden Figures 1 and 2 are areas that connect with the metallization, represented by crossed squares.

In the schematic illustration of FIG. 5, the illustrated static RAM cell 12 and the arrangement can also be used the random access in which the cell is located are generally conventional in construction. The RAM cell can thereby be read out and this cell can be written into by opening the cell in a suitable manner is addressed to determine or change its current state in accordance with conventional practice. It happens this through suitable connections to the RAM arrangement and through chip interface circuits, such as the memory line 100, the line 112 with the potential Vss, the line 104 with the potential Vcc, the Y data line 106 and the

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BATH ORIGINAL

~ ¹⁵ ~ 3Q02492

complementary Y data line 108. In these lines it is metal lines that carry power and signals via the arrangement (Figure 2) and make a connection to the individual cells, as shown by the X markings in the cable paths. at In the illustrated embodiment, the potential Vss can be around 0 volts, and the potential Vcc around 5 volts and the substrate potential Vbb around -3 volts.

·

The static RAM cell component 12 is dynamic by a or capacitive imbalance coupled to the non-self-erasing element 14 with the floating gate. This coupling enables the storage of the current memory content of the self-erasing, static RAM cell 12 in the non-self-erasing one Element 14 upon an operator command. A device for capacitive coupling is also provided, the contents of the non-self-erasing element 14 with the floating gate into the self-erasing, static RAM cell element 12 to be read in if this is desired after the appropriate circular elements have been operated. The memory contents the static RAM cell 12 and the non-self-erasing element 14 can normally be independent of one another, when you transfer from the special command to the unchanged disregards. In particular, the current storage content of the RAM cell 10 is not stored in the non-self-erasing memory element stored when the device for cell addressing and writing is being used to write into the RAM cell 12. Instead, the memory content of the static RAM cell 0 is only saved in the non-self-erasing element 14 by operation of the capacitively transmitted circuit is saved after a special "Save" command, as will be explained in more detail below is described »In essence, therefore, occurs that which is not self-extinguishing Storage element 14 appears to the system 10 as a programmable shadow ROM (shadow ROM).

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As shown in FIG. 5, the device 10 may include a static RAM cell 12 with six transistors of conventional design and a non-self-erasing memory element 14 with an electrically changeable floating gate. The memory element 14 with the floating gate is an element of the type described in the application filed at the same time as “Substrate-coupled memory cell with a floating gate ...; ¹ ”.

An important element of the non-self-erasing memory cell component of the present devices consists in the electrically isolatable bias electrode which is in the substrate is arranged on the substrate surface in the vicinity of a floating gate and with respect to the substrate an opposite one Has conductivity type. The bias electrode may be arranged in the area that is partially below an electrode for storing and erasing is arranged, and these electrodes are insulated from one another by an oxide, which is arranged both below the floating gate and below the electrode for erasing or saving. Because the The bias electrode has an opposite conductivity to the substrate, it can be of the substrate electrical, through a pn transition effect under the influence a blocking potential can be separated. A device can be provided in the arrangements with which Help isolate the bias electrode in this way. A major function of the bias electrode is therein, by capacitive effect, the floating gate during the Electron injection to the floating gate (i.e. during a write cycle) and during an electron emission from the Bias the floating gate (i.e., during an erase cycle) in an appropriate manner.

The potential of the bias electrode can be determined by a circuit element or a circuit device can be controlled. In this element or in this device it can be by a transistor arranged in the substrate of the arrangement

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acting which connects the bias electrode in a predetermined reference voltage source when the transistor is turned on is. When the switching element (e.g., the switching transistor) is turned off, the bias electrode becomes with respect to the programming electrode, which is arranged below the floating gate, sufficiently positive made so that electrons from the programming electrode to the floating gate or tunnel. It will The floating gate potential is changed by making it more negative. This negative change in the potential of the Floating gates through the application of electrons can be detected by a suitable sensing device, such as a MOS transistor, can be determined. In a similar manner, the erase / storage electrode, at least partially the floating gate overlaps and is insulated from the floating gate, brought to a predetermined positive potential so that electrons tunnel from the floating gate to the erase / storage electrode. This way the floating gate can be brought to a relatively more positive voltage by suitable means such as a sensing transistor, can be determined.

There can be an automatic self-regulating compensation circuit physically in the memory device as a feature Area can be formed over which the floating gate and the bias electrode and the substrate coincide to the Current pulse to form in the floating gate during a write operation when electrons are transferred from the program gate to the Floating gate flow. One such circular feature tries the 0 voltage on the tunnel oxide between the asperities of the To minimize programming gates and the floating gate. However, after a large number of operating cycles higher voltages are required in order to write into the floating gate as a result of the charges trapped in the oxide. For these conditions, this circle automatically

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automatically by the fact that he, if this is required, a provides additional voltage. It is the combination that consists in applying a minimum voltage on the floating gate, to provide a shaping of the current pulse and its own voltage to compensate for the trapped charges, which represents a main element for extending the number of useful cycles in the devices according to the invention. aside from that These features were implemented in a very compact manner, taking into account the electrical semiconductor nature of the bias electrode and their arrangement in the surface of the semiconductor substrate can be used. Works in that regard the bias electrode as a variable capacitive coupling device when in an electrically isolated state. The coupling device capacitively couples a main part of the potential of the erase / storage electrode to the Floating gate as a function of the floating gate potential. With this connection, the capacitive coupling of the Potential of the erase / storage electrode to the floating gate is used to create a potential between the floating gate and of the programming electrode to generate sufficient electrons from the programming r-electrode to the floating gate transferred to. However, the capacitance of the capacitive coupling device is variable, so that the part of the potential of the quenching / Storage electrode, which is coupled to the floating gate, decreases with the decrease in the potential of the floating gate, and with an increasing difference between the potential of the bias electrode and the floating gate even more characteristic decreases. Accordingly, the transfer of charge from the programming electrode takes effect the floating gate so that the capacitive coupling and consequently also the transfer of charge to the floating gate decrease.

As shown in the figures, the cell structure of the device 10 is based on a layered monocrystalline p-type silicon substrate 11 is produced, which in the illustrated embodiment 10 can have an acceptor doping level,

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SAD ORIGINAL

that is in the range of about 1x10 to about 1x10 atoms per cm. An electrically insulated floating gate 2 made of polysilicon is provided in the vicinity of the substrate and capacitively coupled to a bias electrode 7 in the substrate. The bias electrode 7 is in the substrate 11 formed and has the opposite conductivity type like the substrate 1.1. In Embodiment 10, the bias electrode 7 may be a donor impurity

17 levels in a range of about 1x10 atoms per cm. The bias electrode 13 can be manufactured by conventional manufacturing techniques such as Diffusion or ion implantation can be generated. In the illustrated embodiment, it can be carried out by ion implantation donor contamination at implant density

12 15 2

from 1x10 to 1x10 atoms per cm up to a thickness of about 1 μπι be made.

The variable capacitance of an electrode with respect to a depletion region can be a function of the potential between the electrode and the substrate (BoyIe and Smith (1970), "Charge Coupled Semiconductor Devices", Bell Systems Technical Journal, 49, pages 587-593). In the illustrated embodiment, the variable capacitance CC2 of the floating gate 2 with respect to the bias electrode 7 essentially by the equation:

CC2 = I2C _O

ο (Δ VV _FB ) B
30th

be expressed. C represents the maximum capacity value (per cm) of the capacitor, which is formed by the adjacent surfaces of the floating gate 2. This capacity is determined as:

. - K.NX

X '

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3002 * 92

where £ is the dielectric constant of the silicon dioxide region 5 between the floating gate 2 and the bias electrode 7 means. The value χ is the Thickness of the dielectric region 5 between the floating gate 2 and the bias electrode 7. q means the Electron charge. K means the relative dielectric constant of silicon. K, is the relative one

Dielectric constant of area 21, which is the bias electrode 7 and the floating gate 2 separates. N is the doping density of the bias electrode 7. The term AV is the potential Vl, the bias electrode 7 minus the potential V "^ of the floating gate 2, where ΔV is approximately greater than zero and where V is the flat band voltage.

Accordingly, CC2 can vary from a value almost equal to C (a constant) for a very high doping density (N) to a value almost zero for a very small doping density (N), with other parameters being constant. The capacitance CC2 therefore becomes smaller as the floating gate begins to receive electrons and becomes more negative. However, when 4V is less than zero, the capacitance CC2 is essentially at its relative constant, maximum value C '. The variable capacitance CC2 controls the voltage that couples the floating gate 12 to the zone 7 of the bias electrode. The potential difference between the programming electrode and the floating gate, which drives the tunnel current, can therefore advantageously be controlled by the controller 0 of the doping density N in the biasing electrode.

The illustrated memory cell 12 with random access has the conventional MOS-RAM design, the two cross-coupled-static Contains inverter circuits that are interconnected to provide a static flip-flop memory element to form six transistors. In this regard, this includes

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RAM memory element 12 cross-coupled flip-flop transistors 27, 28, which are each connected to depletion transistors 31, 32 for "pulling up" via respective data nodes 29, 30. The flip-flop transistors 27, 28 are connected in a suitable manner to ground terminals 24, while the depletion transistors 31, 32 are connected to one terminal of the supply voltage source Vcc. The "X" select transistors 33, 34 of the array ("row" or "word" transistors) are in a similar manner to the data nodes 29, 30 in the overall memory arrangement of which the device 10 forms a part, connected for the purpose of selection. The selection of cell 12 in the arrangement of cells can be accomplished by applying a potential Vcc to the gate of one of the X address transistors 33, 34 and is applied to one of the Y address lines ("column line") which lead to the complementary data output nodes 35, 36

thereby causing the X address transistor to turn on and therefore connecting the flip-flop nodes of the addressed cell 12 to the bit lines Y and Y of the memory array in accordance with conventional RAM operation and design practice.

Reading out of the addressed cell 12 is carried out by that both bit lines are held at the potential Vcc through high value resistors. Dependent on from the state of the flip-flop (one of the transistors 27, 28 is on, the other is off) flows in Current in one or the other of the bit lines and the readout can be accomplished in that the Differential currents can be measured. The writing in the cell 12 can thereby be carried out in a conventional manner, that the cell 12 is addressed as if to be read out and a bit line is held at a potential Vcc, while the other bit line is at the substrate potential Vss is brought.

Cell 12 can be accessed in this way via the word-X-Transis-

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gates 33, 34 with data and complementary data that appear at the Y-node ³ 3ind dem.Y-node 36, an access can be created. Conventional RAM read and write operations are accordingly performed by data nodes 35,36. The cross-coupled, static flip-flop is through

the transistors 27, 28, 31 and 32 are formed, which as long as power (Vcc) is continuously applied to the terminal 26 of the cell 12, have complementary states which appear at the nodes and 30.
10

Static RAM cell 12 may be constructed by conventional, known semiconductor processes and photolithographic Techniques are carried out. While in the illustrated embodiment 10, a special structure of the static RAM's is shown, it is determined that another suitable " Construction can be applied. For example, those shown in embodiment 10 may be depletion arrangements Transistors 31 and 3 2 in other embodiments suitable resistors are replaced. 20th

As indicated, the RAM cell is not self-erasing Storage element 14 coupled. The illustrated non-self-extinguishing cell element 14 has a floating gate 2, means for transferring electrons into the floating gate and means for removing electrons from the floating gate. The cell element 14 also has an automatic, self-regulating circle that tries to increase the number of useful write cycles in the non-self-erasing element 14. When operating forms 0 the transfer of electrons to the floating gate to generate a relative negative potential storage state on the floating gate and removing electrons from the floating gate to produce a relative positive Potential storage state the basis for storage in the non-self-erasing storage device 14. The charge transfer to the floating gate and the removal of charge from the floating gate is accomplished by electron tunneling.

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digits. This essentially leads to the fact that no direct current from the programming supply source with the high Tension is drawn. The small current requirement on the high voltage supply source makes it possible to generate this voltage on the chip and this represents a significant advance. The tunnel current is supported by sharp, insular asperities present in the non-self-extinguishing element, so that relatively thick oxides can be used to separate the tunnel members of the cell and yet generate substantial tunnel currents to and from the floating gate at reasonable voltages. Another quality of the bumps is that they tend to increase the tunnel current mainly in a singular direction conduct. They do not show any symmetrical current flow properties in two directions for reversed fields. A consequence of this is that the non-self-extinguishing element 14 against a loss of the memory status due to an unwanted premature discharge of its electronic charge as a result a readout operation or the operation of an adjacent cell is relatively immune. Since the embodiment of the illustrated non-self-erasing memory element controlled by tunnel properties between polysilicon elements that are physically located above the substrate that contains the static RAM cell, which in large measure is controlled by phenomena in the substrate, the static RAM and the non-self-erasing elements can be independent be optimized. It can therefore use this combination of the static RAM cell and the non-self-erasing Elements can easily be used in conjunction with different technologies.

When the capacitive coupling is carried out, one of the nodes 29 of the RAM cell 12 becomes capacitive via a capacitive one Circular element 23 with a capacitance C1 and a transistor coupled to the non-self-erasing memory element 14. The complementary data node 30 is similar

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copy

BATH ORIGINAL

-24- 3002402

capacitively coupled to the non-self-extinguishing element 14 and through a transistor 20 to the capacitive circuit element 17, which has a capacitance C2. The numerous other circular coupling elements are described in more detail below. But it is important to note that the static RAM cell 12 is only capacitive with the non-self-erasing Element 14 is coupled. There is no offset direct current load on data nodes 29 or 30 of the flip-flop applied by the interface with the non-self-erasing element, so that the static RAM cell 12 is essentially has evaded in the steady state. This represents a significant improvement over the prior art and leads to improved working and operational limits. The electrodes and floating gate structure of the device is shown in Figure 1, while Figure 2 is a simplified topographical view of the RAM cell 12 and the represents non-self-extinguishing element 14, the numerous Components of the static RAM cell 12 and the non-self-erasing electrically changeable component of device 10 are shown, along with the appropriate relative sizes of the various transistors and Capacity elements. Figures 3 and 4 show cross sections through selected elements of Figure 2. It is a Process step followed in the manufacture of the device, which is called "source-drain doping", with additional dielectric- and metallization ^ layers according to a conventional one Process engineering and a conventional embodiment of the arrangement are used to make the device to complete. The structure and operation of the non-self-extinguishing element 14 is generally correct with the disclosure of the patent application from the same day "substrate-coupled memory cell with a floating gate ... * match, with various additional elements that make up the interface to form the static RAM cell 12 are provided.

To produce the non-self-extinguishing cell 14, in the preferred embodiment 10, three layers 50,

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and 54 made of polysilicon in association with various substrate elements and separating dielectric layers are used. Although the device 10 shown, which is not self-extinguishing Cell 14 contains, in an n-channel MOS technology is manufactured, other manufacturing methods and embodiments or possibilities can be used.

The structure of the non-self-extinguishing element as shown in FIGS. 2 to 4 is produced on a p-type silicon substrate 11 which also contains a bias electrode 7 of the opposite conductivity type to the substrate 11. The bias electrode can be introduced by conventional techniques such as a diffusion step or an ion implantation step. A thermal oxide 4, which can be grown by conventional techniques until it is about 12,000 Å thick, is provided on the substrate 11 for insulation reasons in the cell. The thermal oxide is then etched and reoxidized in the areas of the floating gate and the electrodes of the non-self-extinguishing element, so that thinner oxide layers 5, 6 are produced in order to isolate the substrate dielectrically from the three sequentially deposited, formed by conventional photolithographic techniques, to isolate etched and oxidized polysilicon layers that form the programming electrode 1, the floating gate 2, the erase / storage electrode 3 and other circular elements and connecting lines. These thermal oxide layers 5, 6, which separate the polysilicon layers from the substrate, are grown in the preferred embodiment by conventional techniques until they are approximately 1000 Å thick. The values of the substrate doping and the oxide thickness below the control gates of the various transistors, such as the coupling transistor 8 _; can be selected in accordance with conventional design techniques to produce a desired threshold voltage, and the gate of the transistors, such as transistor 8, can be formed from any polysilicon layer that is compatible with the structure

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fit together in the cell.

The first polysilicon layer is oxidized at approximately 1000 ⁰ C and a similar process is performed on the second layer of polysilicon to produce bumps 56 on the upper surfaces of the polysilicon layers as zägezahnartigen in Figures 3 and 4 by the Lines is shown. The asperities generated under such conditions have an area density

9 2

of about 5x10 per cm, an average width the base of 456 A and an average height of 762 A. The bumps create very high fields, when relatively small voltages are applied between overlapping or adjacent polysilicon layers. if the bumps are relatively negatively biased, these fields are sufficient to transfer electrons into the relatively thick oxide layers 42, 43, 44 (which have a thickness of 800 to 1000 Å) to inject, while on average one relatively small voltage (e.g. 25 volts or less) is applied across the oxide. If only an adjacent surface of the polysilicon layer 5 has unevenness, a diode-like effect is caused because the tunneling of the Electrons from the flat surface will not be magnified if the bumps are relatively positively biased. the Manufacturing conditions for the asperities can vary over a wide range and are not limited to that specified above special example limited. As shown, the various layers 50, 52, 54 are made of polysilicon, which form the electrodes and the floating gate of the device 10, from one another by dielectric layers of silicon dioxide isolated. As shown in FIGS. 2, 3 and 4, the overlapping area 18, 43 is between the floating gate 2 and the programming electrode 1 around the area in which electrons are passed through the separation oxide from the Tunneling the programming electrode to the floating gate when there is a sufficiently large, relatively positive voltage on the floating gate is present. The overlapping area 25 between the erase / store gate and the floating gate 2 is the area in FIG

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the electrons tunnel through the isolation oxide 42 from the floating gate, if a sufficiently large, relatively positive one Voltage is applied to the gate 3. The gate 3 overlaps the area 7 by a coupling capacitor 21 of the capacitance CC3 to form, by the overlap area and the thickness of the insulation 6, the voltage difference of the erase / memory gate 3 with respect to the bias electrode 7 and the gating density N of the bias electrode. The floating gate 2 also overlaps with the bias electrode 7 and forms a coupling capacitor 22 with a Capacitance CC2 defined by the overlap area, the thickness the insulation 5, the voltage difference of the floating gate 2 with respect to the bias voltage of the electrodes 7 and the doping density N is formed. Area 9 is a normal strength doped area normally used during the process step is generated, in which the source-drain regions of the various transistors are formed. The capacitance element 25 with the capacitance CE, the capacitance element 19 with the capacitance Csub and the capacitance element 18 with a capacitance Cj »are formulated as shown in the figures is. In addition, these capacities are determined by the properties of various structural elements of the facility realized. In this context, it is noted that the dividing capacitor or the split capacitor 23, the has a total capacitance C1, between the first polysilicon layer and forming the third polysilicon layer. This capacitor works together with the capacitance of the gate of the transistor 8 that the node 29 during a cycle in which the power is switched on, (the Applying power at a potential Vcc) rises more slowly than node 30, provided that transistor 20 is off is in a non-conductive state. The capacitor 17 with the capacitance C2 is between the first polysilicon layer and the substrate area. The total capacity of the capacitance C2 and the capacity of the gate of the transistor

• Tor 20 is adjusted so that it is substantially greater than the total capacity of the capacitance C1 and the capacity of the gate

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3002482

of transistor 8 to cause node 30 at Application of voltages increases more slowly than the node 29. The capacitor 18 with a capacitance Cp is between the floating gate made of polysilicon of the transistor 20 and the first polysilicon layer 50. This capacitor forms a structure for tunneling electrons from the programming electrode 1 of the first polysilicon layer 50 to the floating gate 2. Tunneling occurs when a sufficiently large electric field across the capacitor 18 is developed during programming ^. The quenching capacitor 25 with a capacitance CE is between the Erase / storage electrode 3 and the third polysilicon layer and the floating gate 2 are present. This capacitor 25 forms a structure that allows electrons to tunnel from the floating gate 2 to the erase / storage electrode 3 ("Xöschen") enables.

Tunneling occurs when a sufficiently large electric field is developed across capacitor 25. The condenser also couples some potential during the programming process to the floating gate. The capacitor 21 with a capacitance CC3 exists between the erase / storage electrode 3 and the n-bias electrode made in the substrate by implantation 7. This capacitor creates the coupling through an electrical potential to the floating gate the capacitor 22 when the transistor 8 is turned off. The capacitor 22 with a capacitance CC2 exists between the floating gate 2 and the η region of the bias electrode 7 implanted in the substrate. When the transistor 8 is in a non-conductive state, couples the electrical potential from the erase / storage electrode 3 (via capacitor 21> to bias electrode 7, and then from bias electrode 7 to floating gate 2 (over capacity 22). When a voltage is applied to the electrode 3, when the transistor 8 is in a conductive state State is, the bias electrode 7 is held at ground potential and the capacitance 22 holds the floating gate potential small, so that a large field on the capacitor 25

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^ 29-

can be developed. The capacitor 19, which has a capacitance Csub, is an undesired one parasitic p-n junction capacitor, the capacitor 22 and the capacitor 21 from the erase / storage electrode 3 decoupled during programming. This capacitor should be minimized. As indicated, acts the transistor 8 is a transistor which senses or determines the state of the RAM cell 12 and the not self-erasing element 14 gives the command to program as a function of 0 on the memory state of the RAM cell 12 or clear to transfer the memory status of the RAM cell unchanged. The transistor 20 is a Tiansistor which transmits the state of the self-extinguishing element 14 to the RAM cell 12. The functions these capacities ^ of the capacitor 21, of the capacitor 22, of capacitor 17 and transistors 8 and 20 will be in connection with the description of the operation of the cell Developed.

By using a process of fabricating an n-channel silicon gate and having three layers of polysilicon, a manufacturable _/ compact, easy-to-operate, non-self-erasing static RAM device 10 can be constructed as shown An arrangement of the storage devices can be used as a conventional RAM with the possibility of data storage when the power is lost ("failure protection") or as a self-erasing RAM together with a non-self-erasing ROM The cell can store two independent bits of data, one in the RAM area 12 and one in the non-self-erasing portion 14 of each cell.

It is important to note that the RAM cell 12 can function independently of the ROM cell 14 and that a

030031/0828

non-self-erasing storage does not necessarily occur with every conventional RAM write cycle. Instead occurs the non-self-erasing storage only when a storage command is given to the memory arrangement. In RAM arrangements of the device 10, the assemblies can be used as a system to convert a RAM data pattern into the appropriate to introduce non-self-extinguishing elements with the floating gates. In this connection the corresponding Part of the non-self-erasing element of the An-order as an electrically changeable read-only memory (ROM) work or work. In the following description, the non-self-extinguishing element 14 is used for simplicity referred to as ROM for the sake of it. Because in the non-self-erasing ROM element 14 data for a future call to the RAM cell can be stored, the operation of this data storage can desirably be used in the event of a total loss of power or in other such circumstances, where a conventional RAM would lose its data so that it could not be retrieved. 20th

In addition, because the RAM portion 12 and ROM portion 14 of the cell are "transparent" with respect to one another, the RAM area can be operated essentially independently of the data status of the ROM area. As a result of this feature and because the RAM area transmits the true data status of the ROM area unchanged after the power is switched on an arbitrary initial program, as is conventional in mask programmable ROM memories is automatically entered into the RAM area of the arrangement of a memory arrangement of the devices 10, when the system is powered up again. The stored data or the program of the ROM can essentially can be retained indefinitely for repeated retrieval to the corresponding RAM cells. When operating the facility 10, during which a supply voltage of the potential Vcc is applied to the RAM cell 12, the memory status in-

030031/0828

Halt of the static RAM area 12 can be transferred unchanged into the ROM area 14 in that a single memory pulse "store" of about 25 volts is applied to the erase / storage electrode 3 by a suitable control circuit (not shown) which is so constructed that it is on the chip or off the chip. When the supply voltage is removed from the RAM cell 12, the ROM 14 maintains this data essentially indefinitely, or the ROM 14 maintains this data unchanged until it is changed. When the operating voltage (Vcc) is reapplied to the static RAM cell 12, it automatically transmits the data of the ROM part 14 in a non-destructive and unchanged manner. The RAM cell 12 " ^{therefore remembers" 5} "in which state it is or in what state it was left when the supply voltage was removed; or more precisely, when the command pulse "Save" of 25 volts last appeared.

During operation, the node 29 of the bistable RAM cell either at a higher or a lower electrical potential, with node 30 being the state of the opposite Has electrical potential. The capacitive coupling device for coupling the RAM cell 12 to the non-self-erasing element 14 is capable of saving the state the RAM cell 12th to sense or determine, On based on this determination, the capacitive coupling device determines whether * electrons on the floating gate injected or whether electrons must be removed from the gate 2 in order to keep the memory state of the RAM cell 12 unchanged transferred to. In this regard, it is noted that when node 29 is high, transistor 18 is conducts and the drain region of the transistor 8, the large inversion plate (η-type) of the capacitors 21 and 22 to ground couples. When the "store" pulse of about 25 volts is applied to the erase / storage electrode 3, a develops electric field on capacitor 25, which is large enough to allow electrons to move from floating gate 2 to the electrode

030031/0828

~ ³² '30Q2492

can tunnel. The floating gate 2 is again the gate of the transistor 20 if the entire circuit 10 is now is switched off, the entire voltage is removed, and when then the supply voltage Vcc for the RAM again is turned on to approximately 5 volts, the state of the non-self-erasing element 14 is unchanged on the RAM cell 12 transferred. In this connection, it is noted that the depletion type load transistors 31 and 32 are trying to pull up knots 29 and 30, respectively. However, because transistor 20 conducts (its gate is positively charged) and because the capacitance of the node 30 plus the capacitance C2 of the capacitor T 7 plus the capacitance of the gate of the transistor is greater than the capacitance of the node 29 plus the capacitance C1 of the capacitor 23 plus the capacitance of the gate of the transistor 8, in the illustrated embodiment, the knot is "pulled up more slowly than the knot 29. If the knot 29 reaches approximately 1 volt, the cross-coupled amplifier turns on and sets node 29 high and the node low level.

On the other hand, when node 29 is initially low, transistor 8 is off (non-conductive) and large n-inversion plate of the capacitors 21 and 22 of the bias electrode 7 can float. When a "store" pulse of about 25 volts is applied to the erase / storage electrode 3, couples the capacitor 21 potential through the capacitor 22 to the floating gate 2. The voltage pulse "store" of 25 volts also couples somewhat to floating gate 2 through capacitor 25. The net effect is to create a field on the 0 capacitor 18 is created, which is large enough to cause electrons to enter the floating gate 2 from the Tunnel programming electrode 1 and charge the floating gate negatively. With a negative floating gate, transistor is 2Q excluded (not conductive).

030031/0828

The entire circuit can then be disconnected from the supply voltage and the supply voltage Vcc can then be switched on. As before, transistors 31 and 32 try to pull nodes 29, 30 up, respectively. In this case, however, the capacitance of the node is plus the capacitance C1 of the capacitor 23 plus the capacitance of the gate of transistor 8 is greater than the capacitance of node 30 (transistor 20 is off). The node 3 will therefore go slightly higher than node 29 and will therefore cause the cross-coupled amplifier to turn on and sets node 30 high and node 29 low as it did when a store command pulse was previously received appeared to transmit the state of the RAM to the element 14 with the floating gate unchanged.

It follows accordingly that in the operation of the device 10 when the RAM cell 12 is in a certain memory state (node 29 is high and node 30 is low or node 29 is low and node 30 is high), the ROM area 14 carries this state unchanged in such a way that after the supply voltage is switched on the area 12 of the RAM cell directly transfers the same state back unchanged from the area of the ROM.

In order to be able to call up data from the non-self-erasing ROM cell 14 to the RAM cell 12 when the voltage supply Vcc is switched on (again), there should be numerous capacity relationships be fulfilled. To transfer data from ROM cell 14 to RAM cell 12 under circuit conditions to which the Transistor 20 is turned off, should be the capacitance C1 of the capacitor 23 plus the capacitance of the Gates of transistor 8 must be large enough to ensure that node 29 is always pulled up more slowly than node 30 and causes the cross-coupled amplifier of RAM cell 12 to make node 29 low (off) and node high level (on).

030031/0828

In order to be able to retrieve data for the RAM cell 12 from the ROM cell 14 under conditions in which the transistor 20 is on, the capacitance C2 of the capacitor plus the capacitance of the gate of the transistor 20 should be in one sufficient i-Iafie must be greater than the capacitance C1 of the Capacitor 23 plus the capacitance of the gate of transistor 8 to cause the cross-coupled amplifier of the RAM cell 12 sets node 30 low and node 29 high. The following are representative Capacitance values of these capacities are given for the illustrated embodiment 10:

Node 29 approximately 0.10 picofarads

Node 30 (with transistor 20 on) 2Q about 0.20 picofarads

Node 30 (with transistor 20 off) about 0.05 picofarads.

The described non-self-erasing static RAM cell has as a result of one in the non-self-erasing Establishing existing self-regulating and compensating circuit further advantages, and trying to reduce the number of To increase the usage cycles in the non-self-extinguishing device, as described in the above-mentioned patent application "Substrate-coupled memory cell with a floating gate" 0 is described on the same day. As has been shown, an arrangement can comprise a number of such storage devices can be formed in a simple manner on a substrate of a chip, with suitable auxiliary circuits and interconnections to form a non-self-erasing addressable RAM memory device are provided. The data of the entire RAM area of the arrangement can easily be transferred to the corresponding ROM area of the arrangement and transferred to the RAM arrangement after the supply voltage of the RAM arrangement has been switched on changes to be transferred back.

030031/0823

In the invention includes a non-self-erasing semiconductor cell a memory with random access, a static RAM cell and a non-self-erasing memory element, that with the static RAM cell through capacity coupling can be connected in such a way that the contents of the RAM cell are directly and unchanged to the non-self-erasing Element can be transferred and that the contents of the non-self-erasing memory cell after the application of the Supply voltage to the RAM cell can be transmitted to the RAM cell unchanged. In the case of the non-self-extinguishing The storage element can be a cell with a substrate-coupled floating gate that is self-regulated and has increased tunnel currents due to unevenness.

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Claims (12)

Patent attorneys Dipl.-Ing. H. ^ 'eickwann, Dtvl.-Phys. Dr. K. Fincke Dipl.-Ing. R A. ¥ eickmann, Dipl.-Chem. B. Huber DR.ING.H.LISKA 3002492 SOOQ MUNICH U, DEN PO Box 860820 MÜHLSTRASSE 22, CALL NUMBER 98 3921/22 38042 XICOR, I2JC. Alexander Court los Altos, California, T.St.A. Ficht self-erasing memory device and method of operating this device. Claims Non-self-erasing memory device with a self-erasing one Semiconductor memory cell for storing binary data, with a device for reading out from the self-erasing memory cell and for writing into the self-erasing memory cell, and with a non-self-erasing memory cell Storage device, characterized in that the non-self-erasing storage device (14) is an electrically insulated floating gate conductor (2) for storing binary data in the form of an electrical charge level of two different electrical charge levels on the floating gate conductor (2) that a device for capacitive Coupling the self-erasing memory cell (12) to the not 030031/0828 self-erasing memory device (14) and unchanged Transferring the memory state of the bistable memory cell (27, 28, 31, 32} to the floating gate component in the form a predetermined electrical charge level of the electrical charge level of the floating gate conductor {2} is provided, and that a further device for capacitive coupling of the floating gate conductor (2) of the non-self-erasing memory device {14} to the self-erasing memory cell (12) for the unchanged transfer of the memory status of the floating gate (2} to the self-extinguishing memory cell (12) after applying an electrical supply voltage to the self-extinguishing one Storage cell (12) is provided, 2. Storage device according to claim 1, characterized in that that a bistable, cross-coupled memory flip-flop (27, 28, 31, 32) is provided as the self-erasing memory cell. 3. Storage device according to claim 1, characterized in that a static memory cell with random access is provided as the memory cell, the six n-channel transistors on- -, knows. 4. Storage device according to claim 1, characterized in that a static memory cell with random access is provided as the memory cell, which has four n-channel transistors. 5. Storage device according to claim 1, characterized in that a static memory cell with random access is provided as the memory cell, which has six CMOS / SoS transistors. 6. Storage device according to claim 1, characterized in that A static memory cell with random access is provided as the memory cell, the six CMOS transistors with substrate connection having. 030031/0828 3QQ2492 7. Memory device according to claim 1, characterized in that a dynamic memory cell is provided as the self-erasing memory cell. 8. Storage device according to claim 1, characterized in that the non-self-erasing memory device (14) has a plurality of electrodes and that at least two of these Electrodes and the floating gate (2) are formed with three layers of polysilicon. 9. Memory device according to claim 1, characterized in that bumps are provided in order to improve the flow of electrons to the floating gate conductor (2) and from the floating gate conductor (2) of the non-self-erasing memory device (14). 10. Storage device according to claim 1, characterized in that the application of a single control signal voltage for storage to the cell causes the contents of the self-erasing Memory cell are transferred into the non-self-erasing memory device. 11. Storage device according to claim 1, characterized in that an integrated circuit arrangement having a plurality of cells with self-erasing memory cells and non-self-erasing memory cells Storage facilities is provided. 12. Procedure for non-self-erasing storage of binary Information in an integrated semiconductor circuit, characterized in that one of the binary memory states is one self-releasing semiconductor memory cell with information stored in it capacitively sensed or determined is that a given electrical charge level is dielectrically isolated from two electrical charge levels on one Floating gate conductor according to the capacitively determined 030031/0828 Memory state of the self-erasing memory cell is generated without the memory state of the self-erasing memory cell is changed that subsequently one charge level of the two charge levels of the floating gate conductor is capacitively sensed or is determined, and that the memory state of the two memory states is generated in the self-erasing memory cell, which corresponds to the gate conductor. 030031/0828