DE2559261A1 - Pulse counter with large counting range - has divider's new dividing factor stored when main counter overflows - Google Patents

Abstract

The pulse counter, with large counting range, consists of a divider and a main counter following it. The counter has a device to switch over the divider to a higher dividing factor and to reset the main counter to 100 when it overflows and to store the corresponding dividing factor. This device contains an exponential counter that counts forwards one step each time the main counter overflows. The contents of the exponential counter as well as the main counter are displayed. The complete counter can be housed in one unit.

Description

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The invention relates to an electronic counter with a large counting range (large counting capacity), especially for pulse counting and time measurement.

When counting and especially when measuring time, an adjustment of the Counting device to the expected number of input pulses required so of small to very large pulse numbers all significant digits and only these can be recorded and processed. With small numbers, the digits have higher digits Valence, in the case of large those of low value no importance and should can be omitted or suppressed.

Such an adaptation of the measuring range to the measured variable increases the expenditure on equipment reduced and the measurement simplified.

It is known for this purpose counting devices different, the number of digits adapted to the respective task, in some cases with different advantages to establish fixed partial ratios. However, this leads to a large variety of types. It is also known to achieve a large measuring range and reduce the Output to the significant digits in a uniform measuring device, the division ratio to make the prescaler adjustable.

To do this, however, a switch must be provided and actuated before the measurement will. Furthermore, for its correct actuation, the measurement result must be obtained before the measurement be known in its magnitude.

Finally, the value of the output measurement result is not from the output, but only from the switch position.

The invention is based on the object of providing counters for wide measuring ranges to standardize without the disadvantages of a manual measuring range switch.

According to the invention, this object is characterized by what is set out in the main claim Measures resolved.

Features of preferred embodiments are in the subclaims marked.

The advantages that can be achieved with the invention are, in particular, that the counter by exponential notation with only a few display or default positions covers a wide counting range without manual intervention to switch between ranges to require. This results in a counter or timer with automatic range switching. A uniform meter type is therefore suitable for many applications and can be used in Quantities are produced that integrate the electronic counting circuit make it economical.

The combination with an operating mode control section and a time standard results in an easily programmable universal time control device with a wide time range.

The invention is explained below using two exemplary embodiments explained in more detail with the help of 4 figures. FIG. 1 shows a block diagram of a first embodiment Figure 2 is a block diagram of a further embodiment FIG. 3 shows a detail from FIG. 2, FIG. 4 time diagrams for the function of the counter according to FIG Figure 2.

FIG. 1 shows an embodiment of the invention with an exponent counter and display. The counter here consists of a prescaler with three decades (1,2,3j, a multiplexer% -4), a main counter with three decades (6,7,), an exponent counter (5), four decoders with rows (9 to 12) and a four-digit number display (13 to 16).

A reset signal RST (18) acts on all counting levels of pre, main and exponent counter at the same time and keeps it at zero. Counting signals are only effective if no reset signal is applied. A counting signal Z (17) is fed to the first decade (1) of the prescaler and the multiplexer (4).

The multiplexer (4) also receives the carry signals from the three Prescaler decades (1,2,3) supplied. The output signal (19) of the multiplexer is effective to the first decade (6) of the main counter. The carry signal (20) of the last, The most significant decade (8) of the main counter affects the exponent counter (5).

The binary coded output signals of the decades (;, 7, 8) of the main counter and the xronentenzähler (5) act on decoder circuits (9 to 12) and their Output signals on numeric displays (13 to 16), each consisting of 7 segments, for example exist.

The prescaler with multiplexer, consisting of three decades (1,2,3) (4) gives after every single, every 10th, every 100th

or every 1000th count signal (17) an increment signal (19) to the Main counter consisting of three decades (6,7,8), depending on the status of the exponent counter (9). The decoders (9 to 12) transmit the status of the exponent and main counter on the display (13 to 16). The three positions on the left indicate the mantissa that right the exponent to the root 10, i.e. the number of zeros.

When the exponent counter is zero, the multiplexer (4) gives each individual counting pulse to the main counter until it reaches 999. The display shows 999 0, i.e. 999x10 ° = 999.

The main counter switches on the next count pulse due to an overflow signal (20) sets the exponent counter to 1 and resets itself to 100. The display then shows 100 1, i.e.

100 x 101 = 1000.

From now on, the multiplexer sends every 10th counting pulse (17) to the main counter continue until it reaches 999 again and the display shows 999 1 accordingly 999 x 101 = 9990. After a further 10 counting pulses, the main counter switches through an overflow signal moves the exponent counter to 2 and resets itself to 100 return. The display then shows 100 2, i.e.

100 x 102 = 10,000.

From now on the main counter counts every 100th counting pulse after the next Overflow signal every 1000th counting pulse up to the maximum level of 999 3 accordingly 999 000. After 106 pulses the counter starts again from zero.

Figure 2 shows another embodiment of the invention with default and operating mode control and with time standard for use as a time switch.

Prescaler (1,2,3), multiplexer (4), exponent counter (5) and main counter (6,7,8) have the same function as in the exemplary embodiment according to FIG. 1. The output signals (31 to 34) of the exponent and main counter are used in a comparator (21) with Compared to the default signals (23 to 26). If the actual value (counter reading) is equal and nominal value (default), the comparator outputs an equality signal G (29) to a Operating mode control section (22). Linked depending on operating mode identification signals (27) he equals signal G and a trigger signal T (28) to form an output signal A (30) and a reset signal RST (18) for all counters.

Figure 3 shows an embodiment of the operating mode control part.

A set-reset flip-flop (37) controls with its inverted output % the reset RST (18) of all counters. It is set dynamically by an off the trigger signal T (28) and the counting signal Z (17) through the controllable input logic element (36) derived set signal S (38). It is reset by the equality signal G (29) from the comparator. The reset signal RST (18) thus emits the set signal S to free the run of the counter and blocks it again when the counter reaches the specified Has reached.

The reset signal RST (18) is with the trigger signal T (28) im controllable output logic element (35) linked to the output signal A (30). The logic elements (35 and 36) form, jointly controlled by the operating mode identification signals (2), the following links: Linking input-output operating mode Linking 1. Switch-on delay S = T + A = TRST 2. Switch-off delay S = T + A = T + RST 3rd signal shift S = T ++ TS A = gRST + RST 4th single pulse S = T A = RST 5th signal shortening S = T A = T RST 6th signal extension S = T A = T + RST 7th clock S = T ++ T R * Z A = T7T T the switch-on edge, Ts the switch-off edge of the trigger signal T.

Figure 4 shows the time course of the output signal A in the different operating modes depending on the preset time V and the trigger signal T. Two variants are shown: The trigger signal T1 is longer than the specification V, the trigger signal T2 is shorter. Output signal A1 (solid) refers to 1, output signal A2 (dashed) on T2.

Part of the diagram a) shows the signal curve with a switch-on delay by V counts. The starting edge of the trigger signal indicates the running of the counter free. The output signal begins when the specification V is reached (equality of the counter reading and the setpoint) and ends with the end edge of the trigger signal T. A trigger signal T2, which is shorter than the specification V, does not trigger an output signal.

Diagram part b) shows the signal curve for a switch-off delay. The end edge of the trigger signal enables the counter to run. The output signal A begins with the trigger signal T and ends when the specification V is reached.

Diagram part c) shows the signal shift. The initial and the The end edge of the trigger signal enables the counter to run.

The output signal begins when the specification is reached after the start edge and ends when the specification is reached after the end edge of the trigger signal T. On short trigger signal T2 does not trigger an output signal.

Diagram part d) shows a single pulse. The starting edge of the trigger signal enables the counter to run. The output signal begins with the trigger signal and ends when the target is reached. The output signal is independent of the duration of the trigger signal.

Diagram part e) shows the signal shortening. The starting edge of the The trigger signal enables the counter to run. The output signal begins with the Trigger signal and ends when the specification is reached, but at the latest with the end edge of the trigger signal.

Diagram part f) shows the signal extension. The starting edge of the The trigger signal enables the counter to run. The output signal begins with the Trigger signal and ends when the specification is reached, but at the earliest with the end edge of the trigger signal.

Diagram part g) shows the signal curve when operated as a clock generator. The starting edge of the trigger signal enables the counter to run. The output signal starts with the trigger signal and ends when the specification is reached. It starts with the next counting pulse again, provided the trigger signal is still present.

The same object can be achieved on the basis of the same general inventive concept also by a reversal of the arrangement characterized in claims 1 to 4 to solve. Especially with default counters, the can only be switched to full decimal places Divider can also be connected downstream of the main counter.

L e r s e i t e

Claims (4)

Claim: Electronic counter with a large counting range from a multi-digit prescaler and a downstream multi-digit main counter with overflow output, especially for pulse counting and time measurement by means (4,5) for switching the prescaler (1,2,3) to one place higher dividing ratio and to reset the main counter (6,7,8) to the state 100 ... when the main counter overflows and to save the respective partial ratio. 2. Electronic counter according to claim 1, characterized in that that these means (4,5) have an exponent counter (5), which at each overflow counts one step further. 3. Electronic counter according to claim 2, characterized in that that the reading of the exponent counter (>) as well as that of the main counter (6,7,) is shown. 4. Electronic counter according to claim 2, characterized in that that a comparator (21) the state of the exponent counter ()) and the main counter (6,7,8) with an externally specified target value (specification signals 23-26) and emits a signal (29) if they are equal. ). Electronic counter according to claim 4, characterized by a Operating mode control part (22), which outputs the equality signal (29) on the input side the comparator (21), the operating mode characterizing signals (27) and a trigger signal (28) is supplied and on the output side by a reset signal RST (18) Enables the counter to run and resets it, as well as depending on the counter specification (23-26) and the input signals (27,28) an output signal according to one of at least two of the following operating modes are: a) The starting edge of the trigger signal enables the counter to run. The output signal starts at Reaching the specification V (equality of the counting level and the target value) and ends with the end edge of the trigger signal T (switch-on delay by V counting pulses). b) The end edge of the trigger signal enables the counter to run. The output signal begins with the trigger signal and ends when the specification is reached V (switch-off delay by V counting pulses). c) The beginning and the end edge of the trigger signal start the process of the counter free. The output signal begins when the specification is reached after Start edge and ends when the specification is reached after the end edge of the trigger signal (Signal shift by V counting pulses). d) The starting edge of the trigger signal indicates the running of the counter free. The output signal begins with the trigger signal and ends when the Specification (single signal of V counting pulses duration). e) The starting edge of the trigger signal indicates the running of the counter free. The output signal begins with the trigger signal and ends when it is reached the specification, but at the latest with the end edge of the trigger signal (signal shortening to V counting pulses). f) The starting edge of the trigger signal indicates the running of the counter free. The output signal begins with the trigger signal and ends when it is reached the specification, but at the earliest with the end edge of the trigger signal (signal extension on V counting pulses). g) The starting edge of the trigger signal indicates the running of the counter free. The output signal begins with the trigger signal and ends when the Specification. It starts again with the next counting pulse, provided the trigger signal still pending (astable clock generator with a period of V counting pulses).