DE3211058A1 - Pulse-counting method which saves storage space, and circuit arrangement for carrying out the method - Google Patents

Abstract

A pulse-counting method which saves storage space, in which, after a number a<k> of generator pulses have been input, further pulses are divided down in a counter by connecting to its input a controllable pulse sequence divider with the divider a<pn> variable in n and are thus counted in bursts, the factor n of the exponent of the divider being incremented by one after in each case a<k>-a<k-p> bursts: a<p(n+1)>. The invention is used in logic analysers. <IMAGE>

Description

Memory-saving pulse counting method and switching

processing arrangement for performing the method The invention relates to a memory-saving pulse counting method and a circuit arrangement for Exercise of the procedure.

Physical quantities, such as time or distance, have to be registered numerically then depends on the width (bit word length) of a medium containing the numerical value on the quantity of the physical quantity, i.e. its measurement number. So must z. B. with a mechanical counter with a tenfold increase in the value to be recorded the meter width can be extended by one digit. For a binary counter means a doubling of the numerical value to be recorded increases the number of digits by a steep. Lin binary coded decimal counter (BCD) must be used for tenfold its capacity can be increased by four digits.

Have to alternate small and then very large with a medium Values are recorded, the width of the recording medium is for the maximum value the size to be saved. The recording media are counters, registers, Read / write memory and the like in question. Especially for such great values that are to be recorded in binary form can be enormous widths or bit word lengths become necessary. However, this large width is not used when in between or in the majority only small or very small measured values are required.

The object of the invention is to provide a counter to create, which can record extremely large values with sufficient accuracy can, but with small storage values not a wasteful excess of capacity having.

According to the invention, the object is that in one Counter after a number of ak generator impulses have arrived, additional impulses by upstream connection a controllable pulse train scaler with the n variable divider aPn stocky and thus counted in bundles, whereby after each ak - akP bundles the factor n of the exponent of the divider is increased by one aP (n + 1) In the following becomes a counting range section, within which the generator pulse train in each case is divided with a constant divisor, called the divider range.

Each of these divider areas contains an equal number of bundles, where the number aPn of the generator pulses combined into a bundle from the divider range to divider range is getting bigger. In each divider range, the corresponds to Number of generator pulses combined into bundles, the bundle content, the in applied to this divider range. n can be used as the progressive number of Divider areas are considered.

The constant number of bundles allotted to each closed divider range results from the number of generator pulses processed within a closed divider range, divided by the number of generator pulses allotted to a bundle within the same closed divider range, j It is in the equation print.

From the fact that in the counter within the divider ranges only complete Bundles are counted, there is an uncertainty for each with an incomplete Divider range finished counting. It can, so to speak, in the pulse train coaster up to stuck to a bundle less one pulse generator pulses that are not in the meter more will appear. This is the greatest possible absolute error. The one generator pulse is neglected in the following, so that the largest absolute error in each case is a complete bundle is considered.

A maximum relative error is possible at the beginning of a new divider range, because there the largest possible absolute error (bundle) must be set in relation to the counter content present in the divider range that was closed last. In the case of a count that is already further advanced within a partial range, during which at least one bundle has already been counted, the relative error naturally becomes smaller because it relates to a larger counter content. In terms of formulas, the maximum relative error results: more accurate, Accordingly, the maximum relative error is constant over the entire counting range of the counter because it is independent of n if one pulse per bundle is neglected.

Because of the simple implementation of pulse reduction and counting with binary elements and when considering the error, according to which this with p grows exponentially and decreases exponentially with k, it is important for a 2, substitute 2 for p and 10 for k. With these numerical values the result is a maximum relative error of: 2-8 = 0.0039 # 4 # This maximum relative error, with which a practical example of the present counting method is afflicted, makes this sufficiently accurate for many purposes.

One embodiment of the invention allows using a 13 bit wide counter numbers from 1 to 5. 108 to be included.

Outputs are useful for changing the pulse train reduction of the pulse train scaler is controlled by a decoder connected to the counter.

The pulse train reduction can also take place in that the pulse train reduction is controlled by a second counter which receives the overflow signals of the number the bundle counts within the third counter which detects the divider areas.

The invention is explained in more detail using three figures.

FIG. 1 shows a circuit arrangement for carrying out the method as a block diagram.

In FIG. 2 there are four lines of pulse diagrams for clarification the errors occurring in the present procedure are shown.

Figure 3 illustrates an embodiment of the invention in which in particular The details of the decoder are recognizable.

In Figure 1 is an input of a controllable pulse train reducer 1 connected to a pulse generator, not shown. Output signals of the Pulse train sub-seters 1 are aw count input of a binary counter 2.

Bit outputs of the binary counter 2 are sent to a memory (not shown) connectable. The same bit outputs are at the corresponding inputs of a Decoder 3 and memory for specified counter readings. Output signals from the decoder 3 apply control inputs of the controllable pulse train scaler 1. Start / stop pulses can be applied to the corresponding inputs of the binary counter 2 and the decoder 3.

At the beginning of a count, the generator pulses are sent from the pulse train reducer not influenced and so get directly into the binary counter 2 until there is a predetermined one Number of pulses has accrued. In one embodiment, this number is with 21 ° = 1,024 fixed. This number is recognized by the decoder 3, which then sends the turns on the first divider range of the controllable pulse train reducer with F. The divisor is generally formed according to expression 1. The divider range will always be then pn switched, in other words, the next larger reduction selected, if 2 impulses have arrived in the counter 210 - 21 °. The counter readings of the counter 2, in which the pulse train scaler 1 has to be switched, are in the decoder 3 are preprogrammed and recognized by him.

In the following table those which can be recorded with a counter of 13 bits are shown Pulse numbers shown. In the left column are the generator pulses, The divisor set is in the second column from the left, and in the third Column are the counter readings recognized by the decoder in decimal representation and in the right column the counter readings are shown in binary representation.

Generator pulses divider decoded decoded counter counts levels (decimal) (binary) 1,024 = 210 1,024 100 0000 0000 22 4,096 = 212 1,792 111 0000 0000 24 16,384 = 214 2,560 1010 0000 0000 26 65,536 = 216 3,328 1101 0000 0000 28 262,144 = 218 4,096 1 0000 0000 0000 210 1,048,576 = 220 4,864 1 0011 0000 0000 212 4,194,304 = 222 5,632 1 0110 0000 0000 214 16,777,216 = 224 6,400 1 1001 0000 0000 216 67.108.864 = 226 7.168 1 1100 0000 0000 218 268.435.456 = 228 7.936 1 1111 0000 0000 220 1.073.741.824 = 230 8.704 10 0010 0000 0000 rs it can be seen that the difference in the decoded meter readings from divider range to divider range remains constant at 768.

The present counting method represents a kind of compression of pulse numbers in which those in the left column in from 210 to -230 Power of two generator pulses given in the two the the last columns in decimal and binary listed compressed numerical values.

In the following the reverse translation or expansion of the compressed Numbers in the original values will be discussed. A count S of the compressed Numbers represents a sum obtained from the linear portion 1,024 of n. 768 and consists of a remainder that is less than 768. This accumulation enables a clear expansion of normally stored compressed meter readings. The technical realization of the expansion is not the subject of the present Invention.

It can, while the compression is in real time, in several steps that are not particularly limited in time take place. It is only meant to be set out here that these steps are unambiguous and of appropriate computing circuits executable.

The linear component of 1,024 must first be subtracted from the compressed numerical value. Then divide the difference by 768. A whole part n of the quotient can thus be determined: n specifies how often the number 768 has to be multiplied by a power of two, the exponent of which is increased by 2 starting with 2. This is the inverse process to the counter-dependent generator pulse train reductions. A re-expanded number ZD is thus initially composed of the linear component 1,024 and partial sums, each of which consists of the following products: 768. 22; 768 2; 768 26 ....,. 768 22n There is also a remainder R t 768, which is multiplied by the power of two 22 (n + 1). The remainder is given by: R = S - 1,024 - n. 768 The sum for the expanded number ZD then results in: It is evident that the remainder R contains only closed bundles. Generator pulses that have entered the pulse train reducer and the number of which is less than the content of a bundle are lost in the present method. However, as the error analysis made at the beginning shows, this error is kept within sufficiently narrow limits for many applications.

In FIG. 2, in lines a, b and c, the bundle formation is in the last closed and shown in a non-closed divider area. the Line d shows the bundles of the two divider ranges counted by the counter. In the Line a does not cause an error because there are two in the incomplete divider area completed bundles are available.

In line b, on the other hand, there is a third, incomplete bundle three generator pulses are shown, which are lost if after entering the coaster the count is canceled. In line c the error is greater, because the bundle, which is almost complete with the exception of two generator pulses, is lost. the in lines a to c, three cases represent all three of the expansion to the same residual value R. The gen- rator impulses of the opened Bundles of lines b and c are therefore lost in the compressed count and can no longer be reconstructed even in the event of a subsequent expansion.

The value of the loss of generator pulses at an within of an incomplete bundle of aborted counting runs as a result of the structuring of the entire counting area into individual divider areas and bundles periodically in two ways.

A large period coincides with the counting ranges and a small period Period with the bundles. The maximum value of the relative error within the large Period is at the beginning of a divider range. The maximum error decreases towards the end of the divider range to about a quarter of its original value. Within of an unfinished bundle, there is a maximum error at the end of the opened bundle.

Another error consideration applies to the average error within three decades of the original number of generator pulses, i.e. the uncompressed number Z. Per decade 200 values were selected for Z, such that is, that is, that the individual Z-value is about 1.16?) larger than its predecessor. This gives a mathematically relatively even distribution.

This resulted in an average error of: 1.15% per ovo in the Decade from 105 ... 104 1.10 0 / ovo in the decade from 106 ... 107 0.95 0 / oo in the Deliad from 108 ... 109 It remains to be mentioned that with one Summation of any number compressed according to the present method, possibly stored and re-expanded pulse numbers that range from 1 to 5. 108, the total error cannot be greater than the maximum relative error of the present counting method can be: ZTotal = F1 'Z1 + F2. Z2 + F3 Z3 + ... + Fn, Zn, where F1 ... n = error factor (0.996 ... 1,000). Is used for F1 n F is set, the above equation can be written in the following formula: ZTotal = F (Z1 + Z2 + Z3 + .. + Zn) That means that even if for F the maximum Error is assumed, the error in the summation is also only F.

In FIG. 3, the counting input of a 13-bit binary counter 31 is via a OR gate 32 with 11 inputs and 11 AND gates connected to these inputs 33 ... 43 connected to the outputs of a controllable pulse train reducer 45. tine input terminal of the frequency divider is connected to one not shown Pulse generator. The AND gates each have two inputs; one of these entrances is in each case at the corresponding outputs of the frequency divider. The second inputs of AND gates 33 ... 42 are connected to outputs of EX-OR gates 46 ... 54 connected. The EX-OR gates 46 ... 54 each have two inputs. These Singänge are connected to Q outputs of flip-flop elements 56 ... 65, uni so that in each case the first input of an EX-OR gate a preceding flip-flop and the second input on a subsequent flip-flop lies. Set inputs of the flip-flops are connected to outputs of NAND gates 68 ... 78, their inputs with corresponding bit outputs of the binary counter 31 in connection stand.

As can be seen from the last column of the table on page 6, the binary-coded counter readings do not differ in the lowest 8 bits. As a result, these do not have to be decoded. The inputs of the NAND gates 68 ... 78 are only connected to the 6 bits with the greatest significance. The decoding begins with the two three-way NAND gates 68 and 69. This is followed by two four-way NAND gates 70 and 71. For decoding the other relevant counter readings, NAND gate 72 ... 77 with 5 inputs required. The last NAND gate 78 that the Overflow detection of the counter 31 is used, has 6 inputs. Whenever one of the to decoding counter readings of the counter 31 is reached and thus the corresponding NAND gate input condition is met, one of the flip-flops 56 ... 65 set. Z. B. reached the fourth count to be decoded, it would then the flip-flops 56 ... 59 are set. The counting rate is reduced via the AND gate with two inputs 33 ... 43, the outputs of which are all switched to the OR gate 32 are. The AND gates are controlled via the chain circuit made up of EX-OR gates 46 ... 54. If none of the counter readings to be decoded has been reached, so too still none of the flip-flops set, then the AND gate 33 is because of its inverting Switch on the undivided generator pulse sequence at the input. When I reached the first The counter reading to be decoded is set to the flip-flop 56. This becomes the AND gate 33 blocked and the UfSD-Gntter 34 released via the jX-0DF'R gate lE, so that a pulse train divided by the divider 4 to the Counter 31 is passed on. When the second count to be decoded is reached the flip-flop 57 is set. The EX-OR gate 46 is thus on at its output lead logical "O" signal and thus block the AND gate 34. For that there is EX-OR gate 47 with a logical "1" output signal the AND gate 35 free, whereby the generator pulse train divided by 16 reaches the counter.

Only one of the EX-OR gates can be logically connected to its output Carry out a "1" signal and thus enable one of the AND gates. If after decoding of the first four relevant counter readings, for example, the flip-flops 56 ... 59 are set, the EX-OR gate 46 has an "O" signal again at its output, likewise the EX-OR gates 47 and 48. In contrast, the EX-OR gate 49 at its Output back to logic "1", while EX-OR gates 50 ... 54 are still an output lead logically "O".

The general rule for this circuit is that if n flip-flops are set are, an EX-ODEK gate n releases an AND gate n + 1 and thus the corresponding Reduced pulse train to the counter 31 switched through. With this approach the corresponding switching elements are counted starting from the left. Via a start / stop line 80 counters and flip-flops can be reset.

5 claims 3 figures Blank page

Claims (5)

Claims Memory-saving pulse counting method, d a -du r c h e k e n n n z e i c h n e t that in a counter after a number has arrived a k generator pulses further pulses by connecting a controllable pulse train reducer stepped down with the divisor apn, which is variable in n, and thus counted in bundles after each ak - ak-p bundles the factor n of the exponent of the divisor is increased by one: ap (n + 1). 2. Counting method according to claim 1, d a d u r c h g e -k e n n z e i c h n e t that outputs of the pulse train scaler (i) from one to the counter (2) connected decoder (3) are controlled. 3. Counting method according to claim 1, d a d u r c h g e -k e n n z e i c h n e t that the pulse train divider (1) is controlled by a second counter which is the overflow signals of the number of bundles within the divider ranges counting third counter. 4. Counting method according to claim 1 or one of the preceding claims, d a d u r c h e k e n n -z e i c h n e t that a = 2, p = 2 and k = 10 are set will. 5. Circuit arrangement for performing the method according to one of the preceding claims, d a d u r c h e k e n n n z e i c h n e t that before the Counting input of a binary counter (31) connected to a pulse train reducer (45) is, whose individual reduction stages are controlled by a decoder Gate circuits (w ... 43) are connected to a counting input of the counter (31), where bit outputs of the counter are at inputs -'es decoder (68 ... 78).