DE2002564B2 - Receiver for a telemetry system - Google Patents

Description

The invention relates to a receiver for a telemetry system for detecting occurrence of signals with a certain one output

, 0 frequency representing the resolving state, where the receiver a square-wave converter circuit for converting the received signal into a square-wave pulse train having.

With a known receiver of this type (Lite-

-, 5 raturstelle »The telemetry III« by Dipl.-Ing. S. John and G. Bergmann, Verlag G. Braun, Karlsruhe, 1963, pages 33 to 36) is used as a transmitting device a flip-flop is used which controls an oscillator via a keying circuit in such a way that this emits one of two possible frequencies depending on the switching status of the toggle switch. At the recipient these signals are passed through a filter that enables the transmission frequency to be recognized. The use of filters is for reasons of

_fa5 space requirements and the costs are undesirable in many cases and represent a considerable effort. The invention is based on the object of creating a receiver of the type mentioned above,

where the detection of signals is different Frequency is possible without the use of complex filters.

This object is achieved according to the invention in that the square pulse train is a first delay circuit can be fed that the pulses of the square pulse train and the output signal of the first Delay circuit can be fed to a first gate, the output signal of which is the input of a second delay circuit can be fed that the pulses of the square-wave pulse train and the output signal the second delay circuit can be fed to a second gate and that the delays the delay circuits are chosen so that their output signals with the pulses of the Square pulses coincide in time at the specific frequency representing the triggering state.

Further advantageous refinements and developments of the invention emerge from the subclaims.

Due to the inventive design of the receiver, the occurrence of signals with a specific frequency at the input of the receiver without the use of complex filters can be detected and output signals are generated if one of the frequencies for which the receiver is designed to appear at the entrance of this receiver.

The invention is described below with reference to Ausführungsbeispieisn shown in the drawing explained in more detail. It shows

Fig. 1A is a block diagram of a transmitter for use with the receiver for a telemetry arrangement;

IB shows a block diagram of an embodiment of the receiver,

FIG. 2 shows a group of waveforms for explaining the mode of operation of the receiver according to FIG Fig. IB,

Figure 3 is a circuit diagram of the delay circuit used in the receiver.

The telemetry arrangement shown in FIGS. 1A and 1B uses seven channels in the audio frequency range with center frequencies from 600 Hz to 3480 Hz with a spacing of 480 Hz; the information from all transmitter units via a common two-wire control line 3 via suitable Separating circles are transmitted to the corresponding recipients, although of course also alternatively the Transfer could be made by Fnr.fc.

Since all transmitters and receivers work in the same way, there is only one transmitter unit and one Receiving unit shown; the transmitter shown should, for example, have a center frequency of 2040 Hz exhibit. Frequency shift keying modulation and the information transmitted by the transmitter are used here is either as a continuous AC signal 100 Hz below the center frequency (Ready signal) or as a changing AC signal 100 Hz below and above (Trigger signal) transmitted at the above-mentioned center frequency, the first signal then transmitted when the protected or monitored line is in good working order while Yes, the last-mentioned signal is transmitted when an error occurs.

If one is found influencing the management

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Error, a trigger contact 4 is closed in the transmitter unit. Closing this contact sets a time control device 5 in operation, which controls and uses an astable multivibrator 6 NAND gate 8 opens for a predetermined period of time during which the output of the Multivibrator changes between positive and negative levels, whereby the duty cycle can be changed. The time control device resets itself automatically and can during this period independently of the Be in operation period during which contact 4 is closed; alternatively, the timing device either during this period or during the period during which the contact is closed, depending on which period is longer.

The alternating pulse output variable is sent directly to one input of a bistable multivibrator 9 and applied via an inverter 10 to a further input, so that the output variable of this bistable Switching between two levels changes according to the multivibrator 6 during the timing period. During the entire period when the timing device is not in operation, the NAND grid8 remains closed and it becomes a constant potential is applied to the bistable circuit 9, so that its output is at only one level remains.

An oscillator 12 is controlled by the bistable circuit 9 and oscillates at the standby frequency, 2040 Hz minus 100 Hz when the bistable circuit 9 is at its one level; the oscillator 12, on the other hand, oscillates at the trigger frequency, 240 Hz plus 100 Hz if the bistable circuit 9 is at its other level. In this way, during which period changes during which the timing device is in operation, the frequency of the oscillator successively between 2140 Hz and 1940 Hz for e.g. 20 msec and 60 msec, as determined by the multivibrator 6, in the switched-off state of the timing device (Standby mode) the oscillator, on the other hand, only generates the standby frequency of 1940 Hz and its output is applied to the control line via a filter circuit 13.

Those moments at which the oscillator frequency changes from one to the other are controlled in such a way that they always occur at a certain point in the output waveform at which the switching shocks are minimal; This is achieved by applying the oscillator output to a Schmitt trigger 14, which only triggers "On" when the instantaneous amplitude of the sine waveform assumes a certain level, which is expediently the positive zero transition, with trigger 14 then "Off" triggers when the amplitude drops below this level. The output of the Schmitt trigger is differentiated by RC circuits which are connected to each input of the bistable circuit 9; the diodes D ensure that the input pulses from the NAND gate 8 do not influence this bistable circuit until the moment has come when the Schmitt trigger is "on".

A filter 15 is provided on the receiving side, which effects the adaptation to the control line and in the corresponding frequency range a passband

owns. The received signals are amplified in circuit 16 and square in circuit 17 shaped, then differentiated at 18 and finally to a monostable multivibrator 19 created.

The output of this monostable multivibrator 19 is separately sent directly to a standby frequency-N AND gate 20, first and second trigger frequency NAND gates 21, 22 (i.e. first and second gate for the trigger frequency) applied and differentiated separately at 23, 24 and then on a monostable multivibrator 25 or a "blanking" NAND gate 26 is applied.

For the standby frequency, the output of the monostable multivibrator 25 is differentiated at 28, inverted in the inverter 29 and as the other input variable to the standby frequency gate 20 applied, with each output variable occurring at the gate 20 for the "off" keying of a bistable multivibrator 30 serves.

Another circuit acts on this bistable circuit 30, namely one on the output variable of the gate 20 responsive Zeitstcuerstufe. This Zcitsleucrstufc has a monostable multivibrator 31, whose output variable is integrated at 32 and via a driver stage 33 to block the Trigger frequency gate 21, 22 is used, and also keeps the bistable circuit 30 in the "off" state. The integrated Output is also applied to a timing control circuit 35, which after a predetermined Delay period these circuits, i. H. the gutters 21, 22 and the bistable circuit 30 again opens. The purpose of this timer circuit is to effectively prevent a Trip occurs when a standby frequency is present; such a trigger could for example due to faults or interference or incorrect operation, etc. occur where the Tripping frequency of the Bercitschaftsfrequenz etc. is superimposed; But it is the purpose of the time control stage also to only allow a trip if

a) the standby frequency was previously available and

b) the trigger frequency follows the standby frequency within a certain period.

The route of the trigger frequency is described below. Each output of the tactile gate 26 is applied to a monostable multivibrator 37, the output variable of which is differentiated at 38 in one Inverter 39 is inverted and applied to the first trigger frequency gate 21 as a different input variable. The output of the monostable multivibrator 37 is also differentiated at 40 by one to control another monostable multivibrator 41, the output variable as a further input variable the gate 26 is asserted; Finally, another input variable to this gate 26 is received from the other Output of the monostable circuit 37 applied.

Each output variable of the gate 21 is fed to a monostable multivibrator 42, its Output variable in turn differentiated at 43 in an inverter 44 and inverted as a further input variable is applied to the second trip frequency gate 22. This gate 22 is another Input variable supplied by a limiting circuit which has a Schmitt trigger 45 which receives its input variable directly from the filter 15 and is then keyed in to this gate

to lock when the noise or other stray signals increase the level of the Bctricbssignalc by a certain Exceed value.

The output of this gate 22 is used to put the bistable circuit 30 in its "on": state zn bring.

Each output of this bistable circuit 30 is integrated at 46 and sent to a delay circuit 47 is applied, the function of which is to provide an output trigger 48 under triggering conditions in the energized state to hold, namely during those periods when the standby frequency is present alternating in time with the trigger frequency. In detail, there is a trigger condition (In the tripping state) the transistor 49 (Fig. 3) is non-conductive and causes the transistor 50 to over Diode 51 becomes conductive and energizes the relay. At the same time, a capacitor 52 is connected through a resistor 53 charged. Now, during the 60 msec period during which the work frequency is ( the trigger frequency follows, the transistor 49 is conductive, so that the transistor 50 now does not have the Diode 51 is driven; however, the voltage drop at the collector of this transistor 49 is over the Capacitor 52 transferred to turn off another transistor 54, so that transistor 50 is now through diode 55 remains conductive.

The time constant of the capacitor 52 and its associated resistors is chosen so that the Transistor 50 remains conductive for a period extending over at least two modulation cycles.

To understand how the logic circuit of the receiver works and how it responds to the tripping and to explain the frequency of operation further, reference is made in the following to the waveforms shown in FIG. 2, where the order of the signals a trip condition is shown during the presence.

2a shows the standby frequency obtained before the occurrence of an error, then the error results, the trigger frequency (20 msec), the standby frequency (60 msec), the trigger frequency (20 msec), whereupon the training frequency is restored.

Fig. 2b shows the output of the differentiating circuit 18, which coincides with the negative going zero crossings of the applied signal; In contrast, FIG. 2c shows the output variable of the monostable multivibrator 19.

In this context it should be remembered that the output of this monostable multivibrator 19 is applied directly to one input of the gate 20 and also switches the multivibrator 25 (FIG. 2d) to the "on" state, the output of the multivibrator 25 following Differentiation and inversion is applied to the other input of the gate 20 (Fig. 2c). It should also be mentioned here that the reversal of the monostable circuit 25 is followed by a limited period, for example half a cycle, during which its "inertia" is sufficient to prevent the differentiated input variable of the monostable circuit 19 from causing it to be switched on again. A coincidence between the waveforms 2c and 2e occurs only at the range frequency and the resulting negative output variable of the gate 20 is shown in FIG. 2f; this output variable

is applied directly to the bistable circuit 30 to bring it into the "off" state, and it will also fed to the timing stage, where it puts the monostable circuit 31 (FIG. 2g) in the "on" state brings.

The integrated output of this monostable circuit 31 samples the driver 33 almost instantaneously (for example with a 0.5 msec delay), the output variable (Fig. 2 h) decreases to the gate 21, 22 to block and to keep the bistable circuit 30 ι ο in the "off" state; also sets the initial size of the driver 33 the timing circuit 35 in operation, the output variable (Fig. 2j) according to about 60 msec rises and "open" signals to the inputs of these gates 21, 22 and to the bistable Circuit 30 sets so that these signals now go along with the "opposite" ones from the driver available. In particular, the output variable of the time control circuit remains at a constant standby frequency (Fig. 2j) at a high level, while the output of the driver (Fig. 2h) at a low level Level remains so that the bistable circuit is in its "off" state due to the last-mentioned signal is held.

Remains the output of Zeitsteu- 2 ^r> erschaltung during normal tripping operation at high potential, the standby and trigger frequencies dal alternating with each other and fall time of about 30 msec, but the transition from the standby state to the trip state at the completion of the "A" -Period of the monostable circuit 31, the voltage at the integrator 32 begins to drop and after a predetermined period, for example 5 msec, the output of the driver 33 now goes to high potential j5 (Fig. 2h). If both signals are now at "high" potential, both gates 21, 22 are open and the bistable circuit 30 is ready for operation. Conversely, when the trip state changes to the standby state, this monostable 4 (1 circuit is again brought into the "on" state, whereupon the driver goes back to low potential after a short delay of 0.5 msec can be seen in Fig. 2h - during the modulated waveform there is only a short "window" of about 20 msec duration, during which the triggering can take place.

This period of 5 msec during which the standby frequency makes the subsequent Auslösefre- _V) frequency invalid, is important in terms of stability, especially where - the willingness frequency the escape rate is superimposed, since then the pulse duty of the waveform in - as mentioned above Fig. 2g could be irregular and cause the driver output to go high, which way the gates and the bistable output circuit are not blocked. The longer this period, the greater the degree of security, but of course the greater is the overall response _{delay of the circuit;} accordingly, 5 msec is chosen as a compromise.

The output of the monostable circuit 19 (Fig. 2 c) not only serves for actuating the monosta- _b5 bilen stand-by circuit 25 and the gate 20, but this output is also applied directly to the triggering gates 21, 22 and scans also the monostable trigger circuit 37 in the "on" state (Fig. 2 k), via the blanking gate 26, this gate then being blocked by this monostable circuit during its timing period and additionally blocked by the monostable triggering circuit 41 for a sufficiently long period in order to ensure that the trip one-shot circuit 37 recovers completely before actuating it again. The output variable of this monostable trigger circuit is applied to gate 21 (FIG. 21) after differentiation and inversion, the output variable of monostable circuit 19 only meeting at the triggering frequency and the resulting negative output variable is shown in FIG. 2m . This output variable scans the monostable circuit 42 into the "on" state (FIG. 2n) and the output variable of the circuit 42 is differentiated, inverted and fed to the trigger gate 22 (FIG. 2p), where it meets the output variable of the monostable circuit 19 again only takes place at the trigger frequency (FIG. 2q).

This output variable is used to "on" the bistable circuit 30 (FIG. 2r), which is used for so long >: A «state remains until it is again activated by the next output variable from gate 20 (FIG. 2f) in is brought to the "off" state during the standby frequency.

As already described above, the relay 48 is energized when this output variable occurs and the Delay circuit ensures that this remains the case for a predetermined period, which is extends over at least two modulation cycles so that the excitation is not canceled during the periods during which the standby frequency alternates with the trigger frequency.

After energizing the relay 48, a switch can be operated and the transmission line can be disconnected, whereupon the standby frequency is no longer transmitted; in this case causes the waveform remains at high potential in Fig. 2h, the »waste period of the timing device 35, the, As mentioned above, about 30 msec, the blocking of the gates 21,22 and holds the bistable circuit 30 in the "off" state. In this way the initial conditions are restored at the receiver.

In this described system, the trip frequency becomes twice during its 20 msec period measured before the relay is energized and the trigger frequency is repeatedly transmitted to also at to ensure safe operation in the presence of noise; these factors work together the safety circuits used make the system extremely reliable and stable in operation. Farther the system is "fail-safe" insofar as the output relay 48 is switched off after a signal failure will.

Although this system with reference to a specific embodiment shown in the drawing has been described, it should be noted that various changes and modifications can be made.

For example, in addition to the output formed by the relay 48, a "logical" output can be used be provided which represents the changes in the bistable output circuit 30 by a Relay provided in the collector circuit of transistor 49

809 515/103

hen is. Furthermore, both the sender and the receiver can be equipped with alarm circuits to prevent signal failure or signaling indicate at which the signal drops below an acceptable level. In the case of the transmitter, this can expediently be achieved by using the output size of the Schmitt trigger 14 rectifies and an alarm relay, depending on the situation, via a stable transistor amplifier energized or switched off. A clamping circuit can be provided on the receiver to to keep the bistable output circuit in the "off" state, and essentially around the second trip gate lock in the same way as the timing circuit; this clamping circuit itself is included during the presence of an output signal by a Schmitt trigger, for example with the Amplifier 16 connected. In addition, a timing control circuit can be provided, with the signal for there must be at least one second before the clamping circuit is locked, but what this Circuit enabled to be operational essentially instantaneously when the signal stops to be.

The general mode of operation of the receiver (FIG. 1 B) can now be described in summary will. The signal received on line 3 is filtered and then passed through circuits 16 to 19 shaped and made rectangular and a pulse train (Fig. 2c) is generated. The trigger signal is by means of a first delay circuit (circuits 24, 26 and 37 to 41), a first gate 21, a second delay circuit (circuits 42 to 44) and a second gate 22 are detected. The delay circuits have monostable circuits 37 and 42, respectively; the first Delay circuit also contains a further monostable circuit 41 and a control gate 26, to prevent the one-shot circuit 37 from returning to its normal state too soon is keyed again. These two delay circuits and gates cause a re-

10

fetched (double) detection of the trigger signal.

The ready signal is passed through a third delay circuit (Circuits 23, 25, 28 and 29) una ein uunu ^ ,,. ^, ZC Γ.: 'Σ: - * ~ "· ·" »! <» Bistabile Output circuit 30 is controlled by the outputs of the second (22) and third (20) gates and feeds the delay circuit 47, which during brief interruptions of the trigger signal keeps the output variable in a steady state.

The receiver only responds to a trigger signal closely following a ready signal. this is ensured by the timing control circuit 31 to 33 and 35. The circuits 31 to 33 generate a first timing signal (FIG. 2h), which begins approximately 7 msec after the ready signal has ended; the circuit 35 generates a second timing signal (Fig. 2j) which corresponds to the change in the first signal after a delay of approximately 60 msec follows, provided that the first signal is within this time has not regressed. So if the trip signal fails for at least 60 msec is preceded by a ready-to-use signal, the detection of the trigger signal is blocked. if the trigger signal would last long enough, the timing circuit 35 would be in its original State about 30 msec after switching back the driver 33 (this is not shown in Fig. 2) go back. These two signals together form a "window" during which the trigger signal can be determined; they are in the gates

21 and 22 are fed in to allow detection only during this window, and they become the bistable circuit 30 is supplied to prevent it from changing its state outside of this window. It should be noted that the second timing signal is actually the opposite polarity of the first possesses, so that the two directly into the gates 21 and

22 can be fed.

The gate 22 is also fed by an amplitude monitoring circuit (circuit 45) to prevent the detection of trip signals when the input signal is too large.

For this purpose 3 sheets of drawings

Claims (9)

Patent claims: 1. Receiver for a telemetry system for determining the occurrence of signals with a certain frequency representing a tripping state, the receiver being a square-wave converter circuit for converting the received signal into a square pulse train, characterized in that the Square pulse train of a first delay circuit (24, 37, 38, 39) can be fed that the Pulses of the square pulse train and the output signal of the first delay circuit (24, 37, 38, 39) can be fed to a first gate (21), the output signal of which is the input of a second delay circuit (42, 43, 44) can be fed that the pulses of the square-wave pulse train and the output of the second delay circuit (42, 43, 44) to a second Gates (22) can be fed and that the delays of the delay circuits (24, 37, 38, 39, 42, 43, 44) are chosen such that their Output signals with the pulses of the square-wave pulses at the specific, the trigger state represent frequency coincide in time. 2. Receiver according to claim 1, characterized in that each delay circuit (24,37, 38,39,42,43,44) a first monostable Circuit (37, 42) which is toggled into the astable state by an input signal and that an Inipulsformerschaltung (38, 43) with the output of the monostable multivibrator circuit (37, 42) is connected, which when tilting back the monostable circuit (37, 42) generates an output pulse. 3. Receiver according to claim 2, characterized in that the first delay circuit (24, 37, 38, 39) has a blanking gate (26) via which the pulses of the square pulse train the first monostable circuit (37) can be fed and that through the output of a further monostable circuit (41) is controlled by the output pulse of the first monostable Circuit (37) is tilted into the astable state and a renewed tilting of the first prevents monostable circuit (37) after tilting back. 4. Receiver according to claim 3, characterized in that the blanking gate (26) further receives the output signal of the first monostable circuit (37) at one input. 5. Receiver according to one of the preceding claims, characterized in that the received signal (Fig. 2a) fed to the input of an amplitude monitoring circuit (45) is, which blocks at least one of the first and second gates (21, 22) when the amplitude of the received signal is too large. 6. Receiver according to one of the preceding claims for determining the occurrence of a Trigger signal, which follows a ready signal with a different predetermined frequency, characterized in that the pulses of the square pulse train of a third delay circuit (23, 25, 28) and an input of a third gate (20) can be fed, the output signal of the third at a further input Delay circuit (23, 25, 28) receives that the delay of the third delay circuit (23, 25, 28) is chosen such that you Output signal with the pulses of the square pulse train at the frequency of the ready signal » coincides in time and that a bistable output circuit (30) is provided through the output signals of the second (21) and third (20) gate in the first and second state is switchable. 7. Receiver according to claim 6 for the determination of a triggering state representing vibration sequences, characterized by a delay circuit (47) created by the bistable circuit (30) is controlled and an output signal is generated when the bistable circuit (30) is in its first state during a period which is subject to a change in the second state follows and the length of any expected ready signal waveform exceeds. 8. Receiver according to one of claims 6 and 7, characterized by a time control circuit (31, 32, 33, 35) which is controlled by the third gate (20) and a first timing signal (Fig. 2a) generated which at least during a first predetermined period of time after End of any output signal sequence from the third gate (20) continues, and the a second Timing signal (Fig. 2j) generated, the all level changes of the first timing signal follows and lasts for at least corresponding predetermined times, and that the two Time control signals block the detection of the signals representing the tripping state. 9. Receiver according to claim 8, characterized in that the two timing signals the first and second gates (21, 22) and the bistable circuit (30) can be fed to changes in state then to prevent if one of the timing signals is not available.