DE2002564C3 - Receiver for a telemetry system - Google Patents

Description

The invention relates to a receiver for a telemetry system for detecting occurrence of signals with a certain frequency representing a trigger condition, the receiver a square-wave converter circuit for converting the received signal into a square-wave pulse train having.

In the case of a known receiver of this type (reference "Die Fernmess III" by Dipl.-Ing. S. John and G. Bergmann, Verlag G. Braun, Karlsruhe, 1963, pages 33 to 36) is used as a transmitting device a flip-flop is used which controls an oscillator via a keying circuit in such a way that this emits one of two possible frequencies depending on the switching status of the toggle switch. At the recipient these signals are passed through a filter that enables the transmission frequency to be recognized. The use of filters is undesirable in many cases for reasons of space requirements and costs and represents a considerable effort.

The invention is based on the object of creating a receiver of the type mentioned at the beginning.

in which the detection of signals of different frequencies without the use of expensive Filtering is possible.

This object is inventively achieved in that the rectangular pulse sequence of a first Verzö- "> is delay circuit can be fed, that the pulses of the square wave pulse train and the output signal of the first delay circuit are fed to a Eisten gate, whose output signal is fed to the input of a second delay circuit, that the pulses the square-wave pulse train and the output signal of the second delay circuit can be fed to a second gate and that the delays of the delay circuits are chosen such that their output signals coincide in time with the pulses of the square-wave pulses at the particular frequency representing the triggering state.

Further advantageous refinements and developments of the invention emerge from the subclaims.

Due to the inventive design of the receiver, the occurrence of signals with a specific frequency at the input of the receiver without the use of complex filters 2> can be detected and output signals are generated if one of the frequencies for which the receiver is designed to appear at the entrance of this receiver.

The invention is described below with reference to in jo Exemplary embodiments shown in the drawing are explained in more detail. It shows

Figure 1A is a block diagram of a transmitter for use with the receiver for a telemetry system,

IB shows a block diagram of an embodiment of the receiver,

FIG. 2 shows a group of waveforms for explaining the mode of operation of the receiver according to FIG Fig. IB,

Figure 3 is a circuit diagram of the delay circuit used in the receiver.

The telemetry arrangement shown in Figures 1A and 1B uses seven channels in the audio frequency range with center frequencies from 600 Hz to 3480 Hz with a spacing of 480 Hz; the information from all transmitter units is via a common two-wire control input 3 via suitable isolating circuits to the corresponding receivers transmitted, although, of course, the transmission could alternatively take place by radio.

Since all transmitters and receivers work in the same way, only one transmitter unit and one receiver unit are shown; the transmitter shown should, for example, have a center frequency of 2040 Hz. Frequency shift keying modulation is used and the information transmitted by the transmitter is transmitted either as a continuous alternating current signal 100 Hz below the center frequency (ready signal) or as a changing _b o alternating current signal 100 Hz below and above (trigger signal) the above-mentioned center frequency, the first signal being is transmitted when the protected or monitored line is in the correct state, while ^ ₁ the last-mentioned signal is transmitted when an error occurs.

If a fault is found affecting the line, a trip contact is made in the transmitter unit 4 closed. Closing this contact sets a time control device 5 in operation, which: drives an astable multivibrator 6 and a NAND gate 8 for a predetermined period of time opens, during which the output of the multivibrator varies between positive and negative levels changes, the duty cycle being changeable. The time control device resets itself automatically and can operate during this period regardless of the period during which the contact 4 is closed; alternatively, the timing device can either be during this period or work during the period during which the contact is closed, depending on which period is longer.

The alternating pulse output is applied directly: to one input of a bistable multivibrator 9 and via an inverter 10 to another input, so that the output of this bistable circuit changes between two levels, in accordance with the multivibrator 6 during the timing period. During the entire period during which the timing device is not in operation, the NAND grid 8 remains closed and a constant potential is applied to the bistable circuit 9, so that its output remains at only one level.

An oscillator 12 is controlled by the bistable circuit 9 and oscillates at the standby frequency, 2040 Hz minus 100 Hz when the bistable circuit 9 is at its one level; the oscillator 12, on the other hand, oscillates at the trigger frequency, 240 Hz plus 100 Hz if the bistable circuit 9 is at its other level. In this way, during which period changes during which the timing device is in operation, the frequency of the oscillator successively between 2140 Hz and 1940 Hz for, for example, 20 msec and 60 msec, respectively, as determined by the multivibrator 6 is, in the switched-off state of the timing device (standby state) the oscillator generates on the other hand only the standby frequency of 1940 Hz and its output variable is via a filter circuit 13 applied to the control line.

Those moments at which the oscillator frequency changes from one to the other are controlled in such a way that they always occur at a certain point in the output waveform at which the switching surges are minimal; This is achieved by applying the oscillator output to a Schmitt trigger 14, which only triggers "On" when the instantaneous amplitude of the sine waveform assumes a certain level, which is expediently the positive zero transition, with trigger 14 then "Off" triggers when the amplitude drops below this level. The output of the Schmitt trigger is differentiated by RC circuits which are connected to each input of the bistable circuit 9; the diodes D ensure that the input pulses from the NAND gate 8 do not influence this bistable circuit until the moment has come when the Schmitt trigger is "on".

A filter 15 is provided on the receiving side,; hay, soft causes the adaptation to the control line and a passband in the corresponding frequency range

owns. The received signals are amplified in circuit 16 and square in circuit 17 shaped, then differentiated at 18 and finally to a monostable multivibrator 19 created.

The output of this monostable multivibrator 19 is separately sent directly to a standby frequency-N AND gate 20, first and second trigger frequency NAND gates 21, 22 (i.e. first and second gaiter for the trigger frequency) and separately differentiated at 23, 24 and then on a monostable multivibrator 25 or a "blanking" NAND gate 26 is applied.

For the standby frequency, the output variable of the monostable multivibrator 25 is differentiated at 28, im Inverter 29 inverted and sent to the standby frequency gate 20 as the other input variable applied, with each output variable occurring at the gate 20 for the "off" keying of a bistable multivibrator 30 serves.

A further circuit acts on this bistable circuit 30, namely a time control stage which is responsive to the output variable of the gate 20. This time control stage has a monostable multivibrator 31, the output variable of which is integrated at 32 and is used via a driver stage 33 to block the trigger frequency gates 21, 22, and also keeps the bistable circuit 30 in the "off" state. The integrated output variable is also applied to a timing control circuit 35 which, after a predetermined delay period, reopens these circuits, ie the gates 21, 22 and the bistable circuit 30. The purpose of this timing circuit is to effectively prevent a trip from occurring when a standby frequency is present; Such a trip could occur, for example, due to disturbances or interference or due to incorrect operation, etc., where the trip frequency is superimposed on the standby frequency, etc.; The purpose of the time control stage is also to only allow tripping if

a) the standby frequency was previously available and

b) the trigger frequency follows the standby frequency within a certain period.

The route of the trigger frequency is described below. Each output variable of the touch gate 26 is applied to a monostable multivibrator 37, the output variable of which is differentiated at 38, inverted in an inverter 39 and applied to the first trigger frequency gate 21 as a different input variable. The output variable of the monostable multivibrator 37 is also differentiated at 40 in order to control a further monostable multivibrator 41, the output variable of which is applied to the gate 26 as a further input variable; Finally, another input variable is applied to this gate 26 from the other output of the monostable circuit 37.

Each output variable of the gate 21 is supplied to a monostable multivibrator 42, the output variable of which in turn is differentiated at 43, inverted in an inverter 44 and applied to the second trigger frequency gate 22 as a further input variable. A further input variable is fed to this gate 22 through a limiting circuit which has a Schmitt trigger 45, which receives its input variable directly from the filter 15 and is then keyed to this gate

to block when the noise or other stray signals reduce the level of the operating signals by a certain amount exceed the correct value.

The output of this gate 22 is used by the bistable circuit 30 in its "on" state zi bring.

Each output of this bistable circuit 3C is integrated at 46 and fed to a delay circuit. device 47 is applied, the function of which is to eir output relay 48 in the event of triggering conditions in the energized state to hold, namely during those periods when the standby frequencies; is present alternating in time with the trigger frequency. In detail, if there is a trigger condition (in the tripped state) the transistor 49 (Fig. 3 not conductive and causes the transistor 50 to exercise: Diode 51 becomes conductive and energizes the relay. At the same time, a capacitor 52 is across a resistor 53 charged. Now, during the 60 msec period during which the standby frequency is au the trigger frequency follows, the transistor 49 is lei tend, so that the transistor 50 is now not driven via diode 51; the voltage drop However, the collector of this transistor 49 is transferred via the capacitor 52 to generate a further Tran switch off sistor 54, so that transistor 50 now remains conductive through diode 55.

The time constant of the capacitor 52 and its: associated resistors is chosen such that de Transistor 50 remains conductive for a period that remains on for at least two modulation cycles stretches.

To the mode of operation of the logic circuit de: receiver and its response to the release and standby frequencies to explain further, we <in the following to the oscillation shown in FIG forms referenced, where the order of the signals during the presence of a trigger state: are shown.

Fig. 2a shows the received before an error occurs tene standby frequency, followed by the error sequence, the trigger frequency (20 msec), the standby frequency frequency (60 msec), the trigger frequency (20 msec) whereupon the standby frequency is restored will provide.

Fig. 2b shows the output variable of the differentiator circuit 18, which together with the negative going zero transitions of the applied signal falls; In contrast, FIG. 2c shows the output variable of the monostable multivibrator 19.

In this context, it should be remembered that the output variable of this monostable multivibrator 19 is applied directly to one input of gate 2 (and also the multivibrator 2i (Fig. 2d) switches to the "on" state, di <output variable of the Multivibrator 25 after differentiation and inversion is applied to the other input of the gate 20 (Fig. 2e) It should also be mentioned here that the reversal of the monostable circuit 25 is followed by a limited period, for example half a cycle, during which its "inertia" is sufficient to prevent the differentiated <input variable from causing it to be switched on again Gate 20 is shown in Fig. 2f; this output variable

is applied directly to the bistable circuit 30 to to bring this into the "off" state, and it is fed to the timing stage, where it is the monostable Brings circuit 31 (Fig. 2g) into the "F.in" state.

The integrated output of this monostable circuit 31 loads the driver 33 almost instantaneously (for example with a 0.5 msec delay), the output variable (Fig. 2h) of which drops to the gate 21, 22 to block and to keep the bistable circuit 30 in the "off" state; also sets the initial size of the driver 33 the timing control circuit 35 in operation, the output variable (Fig. 2j) according to about 60 msec rises and "open" signals to the inputs of these gates 21, 22 and to the bistable Circuit 30 sets so that these signals now go along with the "opposite" ones from the driver available. In particular, the output variable of the time control circuit remains at a constant standby frequency (Fig. 2j) is high, while the output of the driver (Fig. 2h) is low Level remains, so that the bistable circuit by the latter Signa! in their "off" state is held.

Furthermore, the output of the timing control circuit remains during normal trip operation at high potential, since the readiness and release frequencies alternate with each other and the Fall time is approximately 30 msec, but when transitioning from the standby state to the trip state when the "on" period of the monostable circuit 31 ends, the voltage at the integrator 32 begins to decrease and after a predetermined period, for example 5 msec, the output variable of the driver 33 now goes to high potential (Fig. 2h). If both signals are now at a »high «Potential, both gates 21, 22 are open and the bistable circuit 30 is ready for operation. Conversely, this monostable applies when changing from the triggered state to the standby state Circuit is again brought into the "on" state, whereupon after the short delay of 0.5 msec the driver again goes to low potential. As a result - as can be seen in Fig. 2h can - during the modulated waveform only a short "window" of about 20 msec duration available during which the release can take place.

This period of 5 msec during which the standby frequency is the subsequent trigger frequency ineffective is important in terms of stability, especially where - as mentioned above - the standby frequency is superimposed on the trigger frequency, since then the pulse duty factor the waveform in Fig. 2g could be irregular and the driver output at high potential lets go, in which way the gates and the bistable output circuit are not blocked. The longer this period, the greater the degree of security, but of course also the greater the total response delay of the circuit; accordingly, 5 msec is chosen as a compromise.

The output of the monostable circuit 19 (Fig. 2c) is not only used to operate the monostable Stand-by circuit 25 and the gate 20, but this output variable is also sent directly to the Trigger gate 21,22 is applied and also scans the mo-

unstable tripping circuit 37 into the "on" state (FIG. 2 k) via the blanking gate 26, where this gate is then blocked by this monostable circuit during its Zcitstcucreason and additionally by the monostable trigger circuit 41 is blocked for a sufficiently long period to ensure that the monostable Trigger circuit 37 fully recovered before actuating again. The output of this monostable Trigger circuit is applied to gate 21 (FIG. 21) after differentiation and inversion, wherein a coincidence with the output of the monostable circuit 19 only at the trigger frequency takes place and the resulting negative output variable is shown in Fig. 2m. This output variable the monostable circuit 42 samples the "on" state (FIG. 2n) and the output variable of the Circuit 42 is differentiated, inverted and fed to trip gate 22 (Fig. 2p) where they meet with the output of the monostable circuit 19 again only at the trigger frequency (Fig. 2q) takes place.

This output variable is used to "on" the bistable circuit 30 (FIG. 2r), which is used for so long The "on" state remains until it is turned into by the next output from gate 20 (FIG. 2f) is brought to the "off" state during the standby frequency.

As already described above, the relay 48 is energized when this output variable occurs and the Delay circuit ensures that this remains the case for a predetermined period, which is extends over at least two modulation cycles so that the excitation is not canceled during the periods during which the standby frequency alternates with the trigger frequency.

After energizing the relay 48, a switch can be operated and the transmission line can be disconnected, whereupon the standby frequency is no longer transmitted; in this case causes the waveform in Fig. 2h remains high, the "fall" period of the timing device 35, the. As mentioned above, about 30 msec, the blocking of the gates 21,22 and holds the bistable circuit 30 in the "off" state. In this way the initial conditions are restored at the receiver.

In this described system, the trip frequency becomes twice during its 20 msec periodc measured before the relay is energized and the trigger frequency is repeatedly transmitted to also at to ensure safe operation in the presence of noise; these factors work together the safety circuits used make the system extremely reliable and stable in operation. Farther the system is "fail-safe" insofar as the output relay 48 is switched off after a signal failure will.

Although this system with reference to a specific embodiment shown in the drawing has been described, it should be noted that various changes and modifications can be made.

For example, in addition to the output formed by the relay 48, a "logical" output can be used be provided which represents the changes in the bistable output circuit 30 by a Relay provided in the collector circuit of transistor 49

hen is. Furthermore, both the transmitter and the receiver can be equipped with alarm circuits be to indicate a signal loss or signal deterioration at which the signal has reached a level drops below an acceptable level. In the case of the transmitter, this can be done appropriately achieve that one rectifies the output of the Schmitt trigger 14 and an alarm relay depending on the situation, it is energized or switched off via a stable transistor amplifier. At the recipient A clamping circuit can be provided to close the bistable output circuit in the "off" state hold, and around the second trip gate in substantially the same manner as the timing circuit / u lock; this clamping circuit itself is in this case during the presence of an output signal connected to amplifier 16, for example, by a Schmitt trigger. In addition, a timing control circuit be present, the signal must be present for at least one second before the Clamping circuit is locked, which, however, enables this circuit, essentially instantaneously to be operational when the signal stops.

The general mode of operation of the receiver (FIG. 1 B) can now be described in summary will. The signal received on line 3 is filtered and then passed through circuits 16 to 19 shaped and made rectangular and a pulse train (Fig. 2c) is generated. The trigger signal is by means of a first delay circuit (circuits 24, 26 and 37 to 41), a first gate 21, a second delay circuit (circuits 42 to 44) and a second gate 22 are detected. The delay circuits have monostable circuits 37 and 42, respectively; the first Delay circuit also contains a further monostable circuit 41 and a control gate 26, to prevent the one-shot circuit 37 from returning to its normal state too soon is keyed again. These two delay circuits and gates cause a repetition (double) detection of the trigger signal.

The ready signal is generated by a third delay circuit (Circuits 23, 25, 28 and 29) and a third gate 20 are detected. The bistable Output circuit 30 is controlled by the outputs of the second (22) and third (20) gates and feeds the delay circuit 47, which during brief interruptions of the trigger signal keeps the output variable in a steady state.

The receiver only speaks to a ready signal closely following trigger signal. This is done by the timing control circuits 31 to 33 and 35 guaranteed. The circuits 31 to 33 generate a first timing signal (Fig. 2h) which is approximately Begins 7 msec after the ready signal has ended; the circuit 35 generates a second timing signal (FIG. 2 j) which corresponds to the change in the first signal after a delay of approximately 60 msec follows, provided that the first signal is within this time has not regressed. So if the trip signal fails for at least 60 msec is preceded by a ready-to-use signal, the detection of the trigger signal is blocked. if the trigger signal would last long enough, the timing circuit 35 would be in its original State about 30 msec after switching back the driver 33 (this is not shown in Fig. 2) go back. These two signals together form a "window" during which the trigger signal can be determined; they are in the gates

21 and 22 are fed in to allow detection only during this window, and they become the bistable circuit 30 is supplied to prevent it from changing its state outside of this window. It should be noted that the second timing signal is actually the opposite polarity of the first possesses, so that the two directly into the gates 21 and

22 can be fed.

The gate 22 is also fed by an amplitude monitoring circuit (circuit 45) to prevent the detection of trip signals when the input signal is too large.

For this purpose 3 sheets of drawings

Claims (9)

Patent claims: 1. Receiver for a telemetry system for determining the occurrence of signals with a certain frequency representing a tripping state, the receiver being a square-wave converter circuit for converting the received signal into a square pulse train, characterized in that the '0 Square pulse train of a first delay circuit (24, 37, 38, 39) can be fed that the Pulses of the square pulse train and the output signal of the first delay circuit (24, 37, 38, 39) feed to a first gate (21) bar, the output signal of which is connected to the input of a second delay circuit (42, 43, 44) can be supplied that the pulses of the square pulse train and the output signal of the second Delay circuit (42, 43, 44) can be fed to a second gate (22) and that the delays of the delay circuits (24, 37, 38, 39, 42, 43, 44) are chosen such that their Output signals with the pulses of the square-wave pulses at the specific, the trigger state represent frequency coincide in time. 2. Receiver according to claim 1, characterized in that each delay circuit (24,37,38,39,42,43,44) a first monostable Has circuit (37, 42) which is toggled into the astable state by an input signal and that a pulse shaping circuit (38, 43) with the output of the monostable multivibrator circuit (37, 42) is connected, which when tilting back the monostable circuit (37, 42) generates an output pulse. 3. Receiver according to claim 2, characterized in that the first delay circuit (24, 37, 38, 39) has a blanking gate (26) via which the pulses of the square pulse train the first monostable circuit (37) can be fed and that through the output of a further monostable circuit (41) is controlled by the output pulse of the first monostable Circuit (37) is tilted into the astable state and a renewed tilting of the first prevents monostable circuit (37) after tilting back. 4. Receiver according to claim / 3, characterized in that that the blanking gate (26) continues to ™ the output signal of the first at one input monostable circuit (37) receives. 5. Receiver according to one of the preceding claims, characterized in that the received signal (Fig. 2a) the input of a -> i Amplitude monitoring circuit (45) is supplied, which at least one of the first and second gate (21, 22) blocks if the amplitude of the received signal is too large. 6. Recipient according to one of the preceding (, 0 Claims for determining the occurrence of a trigger signal, which is based on a ready signal with another predetermined frequency follows, characterized in that the pulses of the Square pulse train of a third delay "-, circuit (23, 25, 28) and an input of a third gate (20) can be fed to a another input receives the output signal of the third delay circuit (23, 25, 28), that the delay of the third delay circuit (23, 25, 28) is chosen such that you Output signal with the pulses of the square pulse train at the frequency of the ready signal coincides in time and that a bistable output circuit (30) is provided through the output signals of the second (21) or second (20) gate in the first or second state is switchable. 7. Recipients according to claim 6 for determination of oscillation sequences representing a trigger state, characterized by a delay circuit (47) which is controlled by the bistable circuit (30) and an output signal then generated when the bistable circuit (30) is in its first state, namely during a period following a change in the second state and the length of any the expected readiness signal oscillation sequence exceeds. 8. Receiver according to one of claims 6 and 7, characterized by a time control circuit (31, 32, 33, 35) which is controlled by the third gate (20) and a first timing signal (Fig. 2a) generated which at least during a first predetermined period of time after End of any output signal sequence from the third gate (20) continues, and the a second Timing signal (Fig. 2j) generated, the all level changes of the first timing signal follows and lasts for at least corresponding predetermined times, and that the two Time control signals block the detection of the signals representing the tripping state. 9. Receiver according to claim 8, characterized in that the two timing signals the first and second gates (21, 22) and the bistable circuit (30) can be fed to changes in state then to prevent if one of the timing signals is not available.