DE1224070B - Device for the integrating counting of certain characteristics of signals - Google Patents

Description

Device for integrating counting of certain characteristics of Signals The invention relates to a device for integrating counting of certain Characteristics of signals sent by a multiphase signal generator with each change a physical quantity by a certain unit value depending on the positive or negative sense of change in size in a certain sequence of combinations of states or in reverse order to more than one output line.

Multi-phase signal generators are known which emit sequences of combinations of states on several output lines for each change in the monitored variable by a certain unit value, which unambiguously characterize the change in the variable by means of their phase sequence. So are z. B. two-phase encoders are known that emit electrical "yes-no" signals on two output lines, which correspond to the following combination sequence for one sense of count per change in the input variable by a certain unit value (increment value): First line: Off -On-On Off, ie 0 -LL- 0 etc. Second line: Off -Off-On-On, ie0-0-L-Lusw. The reverse cycle of the four possible combinations of states then results for the opposite sense of change of the input variable: First line: Off - Off - On - On, ie 0 - 0 - L - L etc. Second line: Off-On-On-Off, ie 0 - L - L - 0 etc. Such a signal can advantageously be called a two-phase binary signal.

The output signals of such encoders do not have to be electrical Be nature; you can z. B. also optical or hydraulic or pneumatic Be nature.

There are also means for integrally counting the above explained signal sequences, d. H. Up / down counter for counting signed Known incremental signals. They are often used to measure physical quantities used, which are freely and alternately in increasing as well as decreasing Can change senses, such as B. lengths and angles, temperatures, etc. known Up-down counters comprise a chain of binary counting or storage stages each with a reversible bistable switching element, e.g. B. a relay or a so-called transistor flip-flop, and each of these number levels is with means for Reversal of the counting direction depending on the current state of a binary Equipped with a sign signal, for example at the input of the counting stage chain depending on the direction of the mutual phase shift of the measured variable supplied two-phase binary signal is generated and fed to each counting stage. The character of the input signal is already shown at the input of the counting stage chain fundamentally changed by only those appearing on one signal line Square pulses are counted. This has the disadvantage that the number of countable Change steps of the measured variable compared to the number of the two-phase signal transmitter indicated change steps of the measurand, d. H. Increments, becomes four times smaller, d. H. the resolution of the measured variable is four times greater. This also makes the Joining together counting stages of the same type made more difficult because they are always different from the previous ones Counting stages also the binary sign signal must be accepted. Another A major disadvantage is the fact that these known up-down counters inevitable glitches affecting the input or an intermediate stage in some way the counting chain are fed in capacitively or inductively or in some other way, with the switched on -Counting sense, so that the counter reading is accordingly is falsified and has to be checked and corrected relatively often.

The known electronic up / down counters hang the sense of counting each bistable switching element from the charges of two coupling capacitors which in turn depend on the current state of the sign signal and at must be changed each time the sign changes. Such a charge exchange from Capacitors take a relatively long time. In addition, in the case of the known up / down counters with each change of sign, first all step couplings to the new counting sense be reversed before the subsequent incremental signal, d. H. the next impulse, may enter the counting step chain. This latter property in particular known up-down counter is the cause that in up-down counters so far the possible counting speed, d. H. the processable pulse repetition rate, is orders of magnitude smaller than pure up counters with electronic transistor flip-flop stages.

- Another disadvantage of the known up / down counters is that relative to the true-to-form transmission of the pulses or pulse trains to be counted high demands have to be made, because not going through a given limit value per se, but the steepness of the pulse edges the overturning the relevant counting level. In this regard, after a prior art proposal improvements are achieved in that the counting stages be coupled to one another in terms of direct current. This well-known proposal relates does not rely on an up / down counter for processing a two-phase Binary signal sequence, but for processing a square-wave pulse series with variable Pulse repetition rate, but shows a possibility of generating a two-phase Binary signal sequence at the output of a DC-coupled flip-flop reduction stage.

The present invention now particularly relates to one Device for integrating counting of certain characteristics of signals that from a multi-phase signal transmitter with every change in a physical variable by a certain unit value depending on the positive or negative sense of change the size in a certain order of combinations of states or vice versa Order to be delivered to more than one output line. Through the invention are significant improvements of such up / down counters compared to the State of the art aimed for and achieved.

These improvements mainly concern the possibility of also having a to be able to process extremely high repetition frequency of the input signals without interference and to avoid the counting of glitches with practically certain certainty. The general and essential inventive idea is to be seen in the fact that to achieve this If all binary counting stages of an up-down counter are designed in such a way that that each of them has the two-phase or multi-phase binary signal system supplied to it unchanged in character, only with a whole number multiplied period length forwards or, in other words, that each counting stage is ideally one mechanical gear reduction gear corresponds in which the direction of rotation of the driven input shaft is automatically transferred to all partial reduction stages will.

According to the invention it is provided that the counting stages of a binary counting stage containing counting stage chain for each output line of the multiphase signal generator or the upstream counting stage each contain a reversible bistable switching element, which switching elements with each other and with the input and output lines of the relevant counting stages are logically linked in such a way that each counting stage in turn as a corresponding multi-phase encoder for signals of the same type and sequence of Combinations of states like the input signals, but each with an integer multiplied Period length is effective.

So there are no special requirements for the waveforms of the signals must be made, the bistable switching elements are advantageous in itself coupled in a known manner in terms of direct current, d. i.e., there will be between counting levels no coupling elements are used, such as capacitors and transmitters, which only change state of the preceding link transferred, but the states in themselves are about Transmit direct current connections. Even with hydraulic and pneumatic counting devices such a coupling is possible.

A counting device according to the invention advantageously counts as Event not the individual "on-off" periods on the input lines, but rather complete sequences or cycles of combinations of states of the various input lines, whereby it is achieved that individual interfering signals that erroneously change from an »on« state to an »off« state or vice versa on an input line pretend not to be counted. This provides the required immunity to interference achieved.

In the following, logical links according to Boolean algebra are often written in a somewhat simplified notation. The following rules apply throughout: A, B, etc .: Real, ie affirmative states of binary state variables, which can have the values 0 = no or L = yes.

Ä, etc .: inverted, i.e. negative states of the binary state variables A, B etc.

A, B, C etc., ie product spelling: subjunctive "and" or "both-and" link of the relevant state variables. A + B + C etc., that is, sums: disjunctive "or", linking the state variables.

For two-phase input signals, e.g. B. to solve the given problem, the following system of equations can be set up in Boolean algebra: R = R (A-T + # I -b @ + SS = R (A-U + Ä-T) + RT = B. (A-R + Ä-S) + UP = B- (AS + Ä-R) + T in which, for example, four output transistors R, S, T, U are provided, which are either conductive or non-conductive, ie they are in the states L, 0 , are, depending on whether their associated input pairs A, B, befndeni If 0 in the above equation system, the input lines or their state possibilities with A, or in the state L or; are designated I, or B, or U and if one makes use of the fact that the output transistors act in pairs as flip-flop elements with the outputs Aa or Äa or Ba or U ", the following simultaneously valid simplified equation pairs result: In the following, this simplified form of representation is used for the definitions of the logical links between the sub-levels of the individual counting levels.

It is known that such circuit logic conditions can occur Parallel arrangements of relay contacts connected in series or by corresponding Combinations of "and" or "or" gate circuits at the input of electronic, hydraulic or pneumatic flip-flop elements.

With relatively simple additives, an inventive, counting device containing only binary counting steps into a decadic counting device transform. For this purpose it is only necessary to have one group of four consecutive Binary counting stages that are combined to form a counting decade, an auxiliary control or Assign the switching stage to those of the sixteen possible combinations of positions of the four binary counting stages only selects ten and uses them, so that a corresponding Code for decadic digits is created.

In the case of a two-phase binary counting stage chain, for example, between the first and the second binary counting stage of each counting decade, an auxiliary control stage designed as a two-phase switching device can be switched on, which is influenced by the input signals A., B, the counting decade, the output signals A1, Bi of the first binary counting stage Decade and the one output signals B3 or B ¢ of the third and fourth binary counting stages of the counting decade to the second binary counting stage for each sequence of ten complete input combination sequences first two periods of the output combinations of the first binary counting stage, then six periods of the input combinations of the first binary counting stage and then again forwarded two periods of the output combinations of the first binary counting stage. To achieve this goal, it is sufficient if the two-phase switching device satisfies the following conditions with regard to its signal values Al * and Bi * in Boolean algebra, which are forwarded to the second binary counting stage: Al * = H3 # U4 # A1 + Ao # (B3 + B4) B1 * - -U3 'H4 # Bi + BO # (B3' + 'B4) A very advantageous decade code is achieved by adding the combinations of the switching states of the bistable switching elements A1, A2, A3, A4 of the four binary counting stages of each counting decade to the ten digits are assigned to a decade according to the following code table: weight Decade digit 4 2 1 2 1 Switching elements Aa I As I Az I Ai 0 0 0 0 0 1 0 0 0 L. 2 0 0 L 0 3 0 L 0 L 4 0 LL 0 5 L 0 0 L 6 L 0 L 0 7 LL 0 L 8 LLL 0 9 LLLL This code fulfills all the requirements previously placed on such code representations of decimal digits, namely: 1. The binary numbers shown grow monotonically. 2. By swapping all L in 0 and all 0 in L in the code representation of a digit, the code representation of the supplementary digit for digit 9 is created.

3. He is by a clear weight assignment to the individual Codes are easy to read or easy to convert into analog values.

4. The last digit clearly decides whether the digit is even or odd (0 = even, L = odd).

5. The first digit clearly decides whether the digit is less than or greater than 5 (first digit 0: digit <5; first digit L: Digit> 5).

6. Digits encoded in this way can be viewed as four-digit binary numbers and added as such. A correction, but only in one place, is necessary if the output of the adder concerned is to be fed to a digital-to-analog converter. It may be desirable to be able to count the algebraic sums of two signal transmitters in the counting device according to the invention, for example for the continuous formation of the variable difference between a target value determined by a first transmitter and an actual value of a physical variable to be controlled by a second transmitter for the purpose the open-loop or closed-loop control of the variable in question after converting the difference value into a control variable. This can be done in a simple manner by using a multiphase adder which is analogous in its action to a mechanical differential gear. So z. B. the output lines X, Y of a two-phase adder, which is connected to the output line pairs AB and CD of two two-phase signal generators, can be connected directly to the two inputs of a two-phase counter according to the present invention. With a two-phase adder, z. B. the following conditions must be fulfilled according to Boolean algebra: X = AU-IY + Ä-C-D + B # U-D + li-CD Y = AB-D + A-Ii-C +; 1-li-D + Ä- BC Embodiments of signal counting devices according to the invention in electrical design and application examples in combination with additional circuit arrangements are shown in the drawing.

In Fig. 1 shows an example of a two-phase electrical signal generator IG to illustrate the principle, which has a sliding contact Kg connected to one positive pole of a DC voltage source, rotatable around the shaft W, either clockwise or counterclockwise, and two sliding contacts Kg, each extending over 180 °, against each other Contains contact paths K ", Kb rotated by 90 °. These contact paths are each connected to earth via a relay Ao and B, respectively. The two relays are thus turned clockwise when the sliding contact Kg is continuously rotated, ie in the direction of the arrow -I-« , according to the 2 subscribed time charts g in F i. Since o and Db o alternately turned on and turned off. in this case the diagram Db o identical approaches with the diagram D "" but this is actuated by a quarter of a period length Po before. the two-phase signal generator IG So if the setting angle a of its sliding contact Kg changes in the direction of the arrow -f- a its output relays Ao, B, one after the other in the following combination cycles: 00 - OL - LL- L0 etc.

and in the case of an opposite rotary movement in combination cycles 00 - L0 -LL-OL etc. They are optical-electrical two-phase signal transmitters for angle changes known which on their two output lines for very small angular steps generate the same combination cycles and for precise digital measurement of rotary movements can be used in place of the IG encoder shown.

It is known that any two-phase rotating field system can be converted into a three-phase, and vice versa. In Fig. 3 is e.g. B. in the same way as in FIG. 1 shows a three-phase signal transmitter IG * , the three contact paths K, *, Kb *, K, * and connected to one relay Ao *, B o *, Co " each rotated by 120 ° against each other, each extending over 180 ° comprises a sliding contact Kg * rotatable about the shaft Wg *.

In Fig. 1 shows a two-phase binary counting stage for the signed counting of the combination cycles Ao, Ba of the encoder IG. It comprises two output relays Al, Bi as electrically reversible bistable elements, which are connected to the positive poles and earth of the said direct voltage source via contact arrangements with contacts ao, bo of the transmitter relays A0, B, and their own contacts a1, bi. It is easy to verify that with the in Fig. 2 contact arrangement shown the two relays Al. Bi according to the timing diagrams Da i, Db 1 of F i g. 2 are energized when the transmitter relays Ao, BO are actuated according to the diagrams Da o, Db o. The two relays Al, Bi are operated according to a two-phase combination cycle, which corresponds exactly to that of the transmitter relays Ao, BO in type and phase sequence, while the period length P1 of the output combination cycle is twice as large as the period length of the input combination cycle, which is a Reduction of the counting speed in a ratio of 1: 2.

The actuation of the relays A1 and Bi in the function of the actuation of the transmitter relays Ao, BO corresponds to the following table: AO Bo AI Bi Explanations and remarks 0 0 0 0 Starting position according to Fig. 1 0 L 0 0 Kg accumulates on Kb. BO is excited L- L 0 L Bi over ao-bo2-a11-Bi- Wb1 L 0 0 L Bi stays above bi, -Bi - Wb 1 * 0 0 LL Al over ao-boi-b12-A1- wal * * 0 LLL Al holds up above a13 - Wa l LLL 0_ Bi over a. - bot - a11- Wb 1 shorted L 0 L 0 0 0 0_ 0 A1 short-circuited via ao-boi-b12-Wai 0 0 0 0 Starting position according to Fig. 1 L 0 L 0 A1 via a0 - b02 -bii-Ai-Wai LL L_ 0 Al stays above a13-A.-W., *** 0 LLL Bi over ao-boi-a, 2-Bi-Wbi 0 0 LL Bi stays above b "- Bi - Wb 1 L 0 0_ L Al short-circuited via ao - bot - bii - Wa 1 LL 0 L 0 L 0 0_ Bi short-circuited via a. - at - a12 - Wb 1 p 0 0 0 0 Faults that falsely simulate excitation of the Aö or Bö relay outside of the normal combination cycle or, conversely, suppress the display of excitation of one of the two relays, can cause the output relays Al, Bi to switch, but when the malfunction disappears, the relays Al are switched back , Bi in the previous state.

If z. For example, if a wrong A. pulse were received at the position marked with * in the table above (Ao drops out too late, for example!), Then the status of the previous line would be retained until .; this false impulse ultimately disappears. However, if such a wrong A. pulse would occur at the point marked with **, the Bi relay would be short-circuited as in the next line, ie the next state phase would be reached too early; but if the wrong A. impulse disappeared again, there would be a fall back into the correct state as at the point in the table marked with ***. However, this demonstrates that the illustrated two-phase binary counter stage is very insensitive to interference. It is also easy to see that in such a two-phase binary counting stage, the occurrence of individual impulses is not counted as events, but only a complete combination cycle of four sub-steps, and that the sense of change of the input signal sequences is simultaneously also transmitted to the output of the binary counting stage with a reduction ratio of 1: 2 is transmitted, exactly the same as would be the case with a correspondingly reduced mechanical transmission connection.

If behind the in F i g. 1 a further, similar binary counting stage with output relays A2, B2 is added, in which contacts of relays Al, Bi play the same role as the contacts of relays A., B, in the stage shown, this results in a two-phase chain of binary counting stages, each of which is exactly the same for the following, as the pulse generator IG for the in FIG. 1 shown binary counting stage is effective.

In the binary counting stage according to FIG. 1 is controlled with the help of DC-coupled relays A., B, and Al . Bi and its contacts an arrangement with two inputs A o, B, and two outputs Al, B1 has been created which, according to Boolean algebra, meets the following conditions: A1 = -qo-Bo-Bl + Ao-Bo-BI + A1 = Bo- (Ä, 0 'Bl + Aa-1J1) + A1 _Z1 = Ä0. BO . B1 + A0 . BO . B1 +; '1 = BO . J0. lf1 + A0 . B1) + i 1 Bi + AO-BO- # TI + B1 = BO - (ÄO-A1 + A0-711) + B1 B1 = J0 - BO - Ä'1 + A0 - BO # Al + B1 = BO - ( Ä O - _T1 + A0 - A,) + B1 with respect to the circuit arrangement according to FIG. 1 in the above system of equations, Ao, BO denotes the real states of the relays belonging to the pulse generator IG, Al, Bi denotes the real states of the relays belonging to the first binary counting stage, while Ä0, NO or Ä1, Hl denote the respectively nonexistent, ie opposite relay states are designated. Of course, it is possible to design a two-phase pulse generator and to link it to a binary counter stage corresponding to the circuit logic of FIG. 1 without having to be assigned to pulse generator A., B.

The same circuit logic and thus also the same counting effect can also be used with two-phase binary counting stages according to FIG. 4 can be achieved, which contain as electrically reversible bistable switching elements Fhp-flop stages of a known type with two transistor circuits Tat, Tat or Tb2, T'b2 with output lines A2, Ä2 or B2, $ 2 and two input lines A1 ,; il, or Bi, B1 are connected. The link is made according to the Boolean conditions listed above by means of “and” gates U and “or” gates 0r, which are also made up of diode arrangements that are also known per se. It should be noted that in this circuit, with pnp transistors, the "off" states mean the corresponding switched-off state of the relevant line (voltage 0) and the "on" states mean the presence of a negative voltage of at least 6 volts.

Such purely electronic counting stages naturally allow a considerably higher counting speed than relay-equipped counting stages according to FIG. 1. It should be noted that in FIG. 4 the inputs A1, A1 and B7, lil the role of the inputs A., A, or B., B, the arrangement according to FIG. 1 and the outputs A2,; 2 or B2, B2 the role of the outputs A1, A1 or B2, B2 of the arrangement according to FIG. 1 play. Furthermore, in the scheme according to FIG. 1 shows a continuous reset line R, via which the binary counting stage can be reset to the idle state (0 position).

Also for three-phase sensors according to FIG. 3 can be used with counter chains three DC-coupled bistable switching elements per counter stage in such a way create a logical link that each counting stage again as a three-phase signal generator, but works with twice the period length.

F i g. 5 shows a binary counter chain connected to the output wires A0, B ″ of a two-phase pulse generator IG with the binary counting stages BS1, BS2, BS3, BS4, which are designed either according to FIG. 1 or 4, and output wires A1, B1 or A2, B2 or A3, B3 or A4, B4. The group of these four binary counting stages forms a decade stage of a decade signal counter with the help of an auxiliary control stage HST. The output wires A. , B, of the pulse generator IG, the output wires Al, Bi of the first binary counting stage BSl and the one output wires B3 and B4 of the binary counting stages BS3 and BS4 are connected, the corresponding "yes" signals of the output wires B3, B4 each being a relay B3 or Excite B4 The output lines A1, B1 of the auxiliary control stage HST, which form the input wires of the binary counter stage BS2, are connected to the named inputs through contacts of the said relays gsadern linked according to the following Boolean conditions: A1 * $ 3-N4-A1 + A0- (B3 + B4) B7 * = B3 - B4. - B1 + BO - (B3 + B4) This means. that, the outputs Al *, Bi *, of the auxiliary control stage, ie the inputs of the second binary counter BS2, are connected either to the outputs Ao, Ba of the signal generator IG or to the outputs A1, Bi of the first binary counter BSi, depending on whether at least one of the output wires B3, B4 or none of them is energized. This leads to a sequence of operations for the output or input lines of the four binary numbers and the auxiliary control stage according to the following table: Decimal_ IG BS, HST BSG BS. BS4 worth AO BO Al - @. BI Al * Bl * A2 B2 As Bs A4 B4 # 0 0- 0 0 0 0 0 0 0 0 0 0 0 L 0 0 0 0 0 0 0 0 0 0 0 L L 0 L 0 L 0 0 0 0 0 0 L 0 0 L 0 L 0 0 0 0 0 0 0 0 LLLL 0 L 0 0 0 0 1 0 LLLLL 0 L 0 0 0 0 L - LL 0 L 0 0 L 0 0 0 0 L 0 L 0 L 0 0 L 0 0 0 0 0 0 0 0 0 0 LL 0 L 0 0 0 L 0 0 0 LLL 0 L 0 0 LL 0 LLLL 0 0 L 0 0 L 0 0 LL 0 L 0 0 L 0 0 0 0 LL 0 0 0 0 LL 0 L. 0 LLL 0 L 0 0 LL 0 L LLL 0 L - L 0 LLL 0 L L 0 L 0 L-- 0 0 LLL 0 L 0 0 .0 0 0 0 LLL 0 0 L 0 L 0. 0.: -L @ LLL 0 0 L LL 0 L "` L 'LL 0 L 0 0 L L 0 0 LL 0 L 0 L 0 0 L 0 0 LL 0 0 0 0 0 0 LL 0 LLL 0 L 0 0 0 0 LL LLL 0 LL 0 L 0 0 LL L 0 L 0 L 0 0 L 0 0 LL 0 0 0 0 0 0 LL 0 LLL 0 L 0 0 0 LLL 0 LLL. LL 0 LLLL 0 0 LLL L 0 0 LL 0. L 0 0. LLL 0 - 0 LL 0 0 0 0 LLL 0 `7 0 LLL 0 L 0 0 LLL 0 LLL 0 LL 0 LLLL 0 L 0 L 0 L 0 0 LLLL 0 0 0 0 0 0 0 LLL 0 L 0 0 L 0 0 0 0 LLL 0 L 0 LL 0 L 0 LLLL 0 L 0 L 0 0 L 0 LLLL 0 L 0 0 0 LLLLL 0 L 0 0 L. 0 LLLLLL 0 L 0 L 0 LLL 0 L 0 L 0 L 0 L 0 L 0 L 0 L 0 L 0 L 0 L 0 The sub-stages A1, A2, A3 and A4 of the four binary counting stages BSi, BS2, BS3, BS4 assigned to the A lines are thus. through ten subsequent complete cycles of the input signal combinations according to the combination sequence defined in the introduction (column 6) in the "off" state (0) or into the "on" state (L), so that the there defined code representation for decimal digits results.

F i g. 6 shows a possible implementation of the auxiliary control stage HST for decade coding with the help of "and" gates U or "or" gates 0r, which each consist of diode circuit arrangements in a manner known per se and each to a bistable flip-flop element with transistors TI., Tza or Tzb, Tzb act.

In. F i g. 7 shows how the two-phase output signals A, B and C, D from two IG and 1G2 according to FIG. 1 can be combined additively or subtractively on a pair of output lines X, Y of a two-phase adding unit. This adder corresponds in its function to a mechanical differential gear, whereby the rotational movements of one input shaft are simulated by the signal sequences A, B of the first signal generator and the rotational movements of the second input shaft by the signal sequences C, D of the second pulse generator, while the resulting rotational movements of the output shaft of the Differential gear can be simulated by the output signal sequences of the adder. Such a two-phase adder is necessary, for example, for determining a variable difference value between a variable setpoint value of a variable and a likewise variable actual value of the variable. The resulting difference value can then also be used in a two-phase counter according to FIG. 1 or 4 are continuously counted and, if necessary after conversion into an analog variable, are used as a control variable for an adjusting device which automatically adjusts the actual value of the variable in question to the setpoint value.

The logical combination of the output lines X, Y with the two input line pairs AB and CD of the two pulse generators 1G1 and 1G2 in the two-phase addition circuit Add with relay contacts a, b, c, d according to FIG. 7 satisfies the following conditions according to Boolean algebra: X = A-Z7-D + BC-D + Ä-C-D + BCD Y = Ä - $ - D + Ä-B-C + A-BJD + ABC . B. also the link according to the following conditions: X = Ä-D-C + Ä-B-D + AB-C + ABD Y = BC-D + Ä-C-D + BC-D + A @ CD For a total Measures would have to be taken between the output signals of the two signal generators IG and 1G2 in order to make the precise temporal coincidence between the two output signal sequences impossible.

In Fig. 8 is a schematic diagram of a counter with two decade counting stages DSi and DS2, which are each shown in FIG. 5 each consist of four binary counting stages BSi + BS4 and one auxiliary control stage HST each, with the output signals Xo, Ya of a two-phase adding unit Add according to FIG. 7 are directed. The output signals AB and CD from two two-phase signal generators IG and 1G2 are fed to the input lines of the two-phase adder.

The two decade counters DSi and DS2 form sensors for two-phase signal sequences X, ', Yö or Xö', Yö 'of the same type and combination sequence as the input signals Xo, Yo, but each scaled down in a ratio of 1:10 and 1: 100 are.

In Fig. 9 finally shows how a two-phase adder instead of relay contacts according to FIG. 7 with “and” gates U and “or” gates 0r and two flip-flop stages X, X; Y, Y can be realized.

Claims (7)

Claims: 1. Device for integrating counting of certain Characteristics of signals sent by a multiphase signal generator with each change a physical quantity by a certain unit value depending on the positive or negative sense of change in size in a certain sequence of combinations of states or in reverse order to more than one output line, : characterized by the fact that the counting stages (BS) contain a binary counting stage Counting step chain for each output line of the multiphase signal generator or the upstream counting stage each contain a reversible bistable switching element, which switching elements with each other and with the input and output lines of the relevant counting stages are logically linked in such a way that each counting stage in turn as a corresponding multi-phase encoder for signals of the same type and sequence of Combinations of states like the input signals, but each with an integer multiplied Period length is effective. 2. Counting device according to claim 1, characterized in that that the bistable switching elements of all counting stages are direct current in a manner known per se are coupled to each other. 3. Counting device according to claims 1 and 2, characterized characterized in that it is used to count complete cycles of the combinations of states the various output lines of the encoder is formed. 4. Counting device according to claim 3, characterized in that in each counting stage (BS) a complete cycle as an event (0 0 LL 0 etc.) (0 LL 0 0 etc.) for one sense of counting and the reverse cycle, (0 LL 0 0 etc.) (0 0 LL 0 etc.) counted for the opposite counting sense and, scaled down in an integer ratio, is passed on to the following counting stage. 5. Counting device according to claim 4 for counting the cycles of two-phase signal generators, characterized in that the DC-coupled bistable switching elements of each counting stage are logically linked to each other and to the input and output lines of the relevant counting stage in such a way that, according to Boolean or equivalent algebra, the following pairs of simultaneously valid conditions are met: Aa = $ e. (Ae.Ua + Äe.Ba) +, Aa Äa (Ae'Ba + Äe'Ua) + Äm Ba = De. (Ae . Ä «+ Äe . Aa) + Ba Na = Be (Ae-Aa + Äe-Äa) + UQ where with Ae, B, or Aa, Ba the real states of the input lines or the output lines and with Äe , De and Ä ", $ a denote the opposite states of the lines in question. 6. Counting device according to claim 1, characterized in that a group of at least four successive binary counting stages (BSi + BS4) of the counting stage chain with an associated auxiliary control stage (HST) is combined to form a counting decade (DS) of a decadic counting device, said auxiliary control stage from selects ten of the possible combinations of states of the binary counting stages for utilization. 7. Counting device according to claims 5 and 6 with four binary counting stages per counting decade, characterized in that between the first and the second counting decade an auxiliary control stage (HST) designed as a two-phase switching device is switched on, which under the control influence of one output signal (B3 or B4 ) the third or fourth binary counting stage of the counting decade alternately transmits either the input signals (A0, BO) of the first binary counting stage of the counting decade or the output signals (A1, Bi) of the first binary counting stage to the second binary counting stage, in such a way that the combinations of states associated with the one phase bistable switching elements (A) of the four binary counting levels correspond to the ten decade digits according to the following code table: weight Decades 4 2 1 2 1 digit switching elements Aa I As, Az, AI eauu 0 0 1 # 0 0 1 0 I 0 0 L 2 0 0 L 0 3 0 L 0 L 4 0 LL 0 5 L 0 0 L 6 L 0 L 0 7 LL 0 i, 8 LLL 0 9 LLLL B. Counting device according to Claim 7, characterized in that the auxiliary control stage, with respect to its signals (Ai *, Bl *) forwarded to the second binary counting stage of the counting decade, is dependent on the one output signals (B3, B4) of the third and fourth binary counting stages and the input signals ( A., BO) of the first binary counting stage and its output signals (A1, Bi) meet the following conditions: Al * = AiB3-B4 + Au. (Ba + B4) Bi * = Bi ' B3 ' B4 + B1 - (B3 + -B4 9. Counting device according to claim 1, characterized in that for the additive or subtractive combination of the output signal cycles (A, B or C, D) of two signal generators with polyphase output lines on a polyphase output line, a multi-phase adder which is analogous in its effect to a mechanical differential gear (Add) is used. 10. Counting device according to claims 5 and 9, characterized in that the output line (X, Y) of the adder (Add), which in turn are connected to the first binary counting stage of the subsequent counting chain. are linked with the output lines (A, B or C, D) of two two-phase sensors (JG, or JG2) according to the following or equivalent conditions in Boolean algebra: X = A-Z7-D + Ä-C-D + BC. D + BCIS Y = AB-D + AB-C + Ä-B.D + Ä.B.Z7 Considered publications: German Auslegeschrift No. 1111669; Electronics, 1960, no. 7, pp. 209 to 214.