DE1223881B - Circuit arrangement for the separate evaluation of temporally overlapping arriving information elements and for displaying information elements that overlap completely or almost completely - Google Patents

Description

FEDERAL REPUBLIC OF GERMANY

GERMAN

PATENT OFFICE

EDITORIAL

Int. Cl .:

H03k

German class: 21 al-36/20

Number: 1 223 881

File number: S 92482 VIII a / 21 al

Filing date: August 5, 1964

Opening day: September 1, 1966

The problem on which the subject matter of the main patent is based consists in evaluating information elements arriving at a time overlapping time separately and in a consistent manner and also recognizing if a subsequent information element η + 1 within a time period T, calculated from the beginning of the preceding information element η occurs. Individual inputs are to be understood as meaning, for example, separate lines or also keyboards with electrical evaluation, which are used to input information elements into message processing machines.

To solve this problem, according to the main patent, a switching means is assigned to each input, and all these switching means are activated in the idle state by a criterion which is canceled by an incoming information element at the assigned switching means. To register this process, intermediate memories are provided, which are queried by a common timing element applied via a control element at the beginning of the information element after a certain time T has elapsed. Furthermore, a control circuit is arranged which, after the time T has elapsed, checks the intermediate memory to determine whether more than one output signal is present. This means that a switching means and a buffer are assigned to each input. The beginning of an information element present at the input is registered in the buffer memory. With the storage, a timing element common to all switching means and thus also to intermediate storage is excited, which, after a time T has elapsed, triggers a control that checks whether (within the time span T) an unevaluated information element is switched on at more than one input. If the result is positive, the message in the buffer is evaluated.

Each switching means is preferably used at the same time as a buffer for the assignment of the inputs exploited. Magnetic cores with a rectangular hysteresis loop are used as switching means, for example.

The output signals obtained in the circuit arrangement according to the main patent are separated amplified by transistors and fed to an evaluation arrangement, which these signals for example converted into a binary code. The present invention is based on the object of this relatively to simplify complex further processing of the output signals. This task is carried out in Further development of the circuit arrangement according to the

Circuit arrangement for the separate evaluation of temporally overlapping arriving and to Display of completely or almost completely overlapping information elements

Addition to registration: S 91725 VIII a / 21 al - Auslegeschrift 1215 759

Applicant:

Siemens & Halske Aktiengesellschaft, Berlin and Munich,
Munich 2, Witteisbacherplatz 2

Named as inventor:
Dipl.-Ing. Hartmut Gebhardt,
Großhesselohe near Munich

Main patent in which the switching means assigned to each input consist of magnetic cores with rectangular Hysteresis loop exist, solved according to the invention in that these switching means simultaneously for generating the output signals corresponding to the evaluated information elements serve in any code form. One or more are required for the coded evaluation of the output signals additional windings connected in series are arranged on the magnetic cores. That way will a separate coding circuit and the number of amplifier elements required reduced to a fraction.

The invention is explained using an exemplary embodiment.

Fig. 1 shows a scheme for the coding of the output signals,

Fig. 2 shows the invention in a representation accordingly F i g. 3 of the main patent.

The scheme in FIG. 1 is based on the assumption that there are 40 inputs Ta 1 to Ta 40. Furthermore, the evaluation should take place in the form of a 2-out-of-5 code (α) and a 1-out of 4 code (ß) . When the key TsI is pressed, an output signal αθ, al, ßl then arises.

'-'" 609 658/373

The representation in FIG. Apart from the code windings α and β on the magnetic cores, 2 corresponds in principle to FIG. 3 of the main patent. A direct current bias winding Wl runs through all magnetic cores Kl to Kn , through which a current flows which is limited by the resistor Rg and controls the cores, for example, on the positive side of the hysteresis loop. When closing z. B. the key TsI flows through the core Kl via the winding W2 and the resistor Rl a current to a control element Ag, which represents a current control. The control element Ag excited by this current controls a timing element Zg which, like the control element Ag, is common to all switching means. The working point of the core Kl is shifted to the positive remanence point by the current flowing through the winding W2 in the kernel. After a time T has elapsed, the timing element Zg sends out a current / 2 for the duration t , which flows via the interrogation windings W 3 of the cores £ 1 to Kn and via the resistor Rzg . With the start of the current / 2, the operating point on the hysteresis loop jumps from the positive remanence point to the negative branch of the hysteresis loop in the core K1 and reaches the negative remanence point after completion of / 2. In the cores K2 to Kn , however, the shifting of the operating point takes place only from the positive branch of the hysteresis loop to the positive remanence point and back again. This means that a voltage is induced only in the windings <x0, al and ßl on the core Kl. The change in the magnetic flux in the cores K 2 to Kn is too small to allow a sufficiently large output signal to arise in the corresponding α and / 9 windings. The output signals on the α and ^ lines are amplified in common amplifier groups V1, V2. If, for example, 40 keys (Tsη - 40) and 40 cores (Kn - 40) are used, the circuit arrangement according to the main patent requires 40 amplifiers in the form of transistors, while according to the present invention and the selected code example there are only nine amplifiers .

The control circuits KsI, Ks 2 following the amplifier groups F1, F 2 check whether more output signals, ie in the present case more than three, than one output signal in coded form

ίο correspond to occur. If this is the case, the output is blocked and a display, not shown, is switched on. In the present exemplary embodiment, the control circuit KsI checks whether more than one signal occurs on the four / J lines, and the control circuit Ks 2 checks whether more than two signals are present on the five α lines. ·

Claims (2)

Patent claims: 1. Circuit arrangement for separate, consistent Evaluation of information elements arriving at a time overlap via several individual inputs, for which each input assigned switching means made of magnetic cores with a rectangular hysteresis loop B5 stand, according to patent application S 91725 Villa / 21 ai (German Auslegeschrift 1215 759), characterized in that these switching means (Kl to Kn) serve at the same time to generate the output signals corresponding to the evaluated information elements in any code form. ■ 2. Circuit arrangement according to claim 1, characterized in that for the coded evaluation of the output signals one or more additional and series-connected windings («, ß) on the magnetic cores (Kl to Kn) are arranged, which are to common amplifier groups (Fl, F 2) to each of which a control circuit (KsI, Ks2) is connected. 1 sheet of drawings 609 658/373 8.66 © Bundesdruckerei Berlin